Revised December 2000 GTLP6C816 GTLP/TTL 1:6 Clock Driver General Description Features The GTLP6C816 is a clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. ■ Interface between LVTTL and GTLP logic levels Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. ■ Designed with edge rate control circuitry to reduce output noise on the GTLP port ■ VREF pin provides external supply reference voltage for receiver threshold adjustibility ■ Special PVT compensation circuitry to provide consistent performance over variations of precess, supply voltage and temperature ■ TTL compatible driver and control inputs ■ Designed using Fairchild advanced CMOS technology ■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs ■ Power up/down and power off high impedance for live insertion ■ 5V over voltage tolerance on LVTTL ports ■ Open drain on GTLP to support wired-or connection ■ A Port source/sink −24mA/+24mA ■ B Port sink +50mA ■ 1:6 fanout clock driver for TTL port ■ 1:2 fanout clock driver for GTLP port Ordering Code: Order Number GTLP6C816MTC Package Number Package Description MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Names Connection Diagram Description TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively) OEB Output Enable (Active LOW) GTLP Port (TTL Levels) OEA Output Enable (Active LOW) TTL Port (TTL Levels) VCCT.GNDT TTL Output Supplies (5V) VCC Internal Circuitry VCC (5V) GNDG OBn GTLP Output Grounds VREF Voltage Reference Input OA0–OA5 TTL Buffered Clock Outputs OB0–OB1 GTLP Buffered Clock Outputs © 2000 Fairchild Semiconductor Corporation DS500129 www.fairchildsemi.com GTLP6C816 GTLP/TTL 1:6 Clock Driver June 1998 GTLP6C816 Functional Description The GTLP6C816 is a clock driver providing TTL-to-GTLP clock translation, and GTLP-to-TTL clock translation in the same package. The TTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to-TTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting for both directions. Truth Tables Inputs Outputs TTLIN OEB H L L L L H X H High Z OBn Inputs Outputs OAn GTLPIN OEA H L L L L H X H High Z Logic Diagram www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VI) −0.5V to +7.0V Recommended Operating Conditions (Note 3) 4.75V to 5.25V Supply Voltage VCC DC Output Voltage (VO) Bus Termination Voltage (VTT) Outputs 3-STATE −0.5V to +7.0V GTLP 1.47V to 1.53V Outputs Active (Note 2) −0.5V to +7.0V VREF 0.98V to 1.02V DC Output Sink Current into Input Voltage (VI) on INA Port OA Port IOL 48 mA and Control Pins DC Output Source Current 0.0V to 5.5V HIGH Level Output Current (IOH) −48 mA from OA Port IOH −24 mA OA Port DC Output Sink Current into LOW Level Output Current (IOL) 80 mA OB Port in the LOW State IOL +24 mA OA Port DC Input Diode Current (IIK) +34 mA OB Port VI < 0V −50 mA DC Output Diode Current (IOK) VO < 0V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. −50 mA VO > VCC +50 mA ESD Rating > 2000V Storage Temperature (TSTG) −40°C to +85°C Operating Temperature (TA) Note 2: Io Absolute Maximum Rating must be observed. −65°C to +150°C Note 3: Unused input must be held HIGH or LOW. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL Min Test Conditions Typ VREF +0.05 GTLPIN Others 2.0 GTLPIN 0.0 VTT VREF −0.05 Others 0.8 VREF GTLP 1.0 (Note 5) GTL 0.8 VTT GTLP 1.5 (Note 5) GTL 1.2 VIK VOH VOL VOL II OAn Port OAn Port OBn Port TTLIN/ VCC = 4.75V II = −18 mA VCC = 4.75V IOH = −100 µA VCC−0.2 IOH = −18 mA 2.4 IOH = −24 mA 2.2 VCC = 4.75V VCC = 4.75V VCC = 5.25V VCC = 5.25V IOL = 100 µA 0.2 IOL = 18 mA 0.4 IOL = 24 mA 0.5 IOL = 100 µA 0.2 IOL = 34 mA 0.65 VI = 5.25V 5 −5 VI = VTT 5 VI = 0 −5 100 VCC = 0 VI or VO = 0V to 5.25V IOZH OAn Port VCC = 5.25V VO = 5.25V IOZL OAn Port VCC = 5.25V VO = 0 ICC OAn or VCC = 5.25V Outputs HIGH Outputs LOW 7 20 VI = VCC or GND Outputs Disabled 7 20 VCC = 5.25V VI = VCC−2.1 ∆ICC TTLIN 5 VO = 1.5V 5 −5 7 V V V µA µA µA µA µA 18 6 3 V V TTLIN OBn Ports V V IOFF OBn Port Units V −1.2 VI = 0V Control Pins GTLPIN Max (Note 4) mA mA www.fairchildsemi.com GTLP6C816 Absolute Maximum Ratings(Note 1) GTLP6C816 DC Electrical Characteristics Symbol (Continued) Min Test Conditions Typ Max Units (Note 4) CIN Control Pins/GTLPIN/ TTLIN VI = VCC or 0 3.7 COUT OAn Port VI = VCC or 0 7 OBn Port VI = VCC or 0 7 pF pF Note 4: All typical values are at VCC = 5.0V and TA = 25°C. Note 5: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Absolute IOL ratings. Similarly VREF can be adjusted to compensate for changes in V TT. AC Electrical Characteristics Over recommended range of supply voltage and operating free air temperature. VREF = 1.0V (unless otherwise noted). CL = 30 pF for OBn Port and CL = 50 pF for OAn Port. From To (Input) (Output) Min TTLIN OBn Typ Max Symbol tPLH Units 1.5 3.8 6.0 1.5 2.8 5.0 1.5 6.4 10.5 1.5 3.2 6.0 ns tPHL tPLH (Note 6) OEB OBn ns tPHL tRISE Transition Time, OB Outputs (20% to 80%) 2.3 ns tFALL Transition Time, OB outputs (20% to 80%) 2.3 ns tRISE Transition Time, OA outputs (10% to 90%) 2.0 ns tFALL Transition Time, OA outputs (10% to 90%) 2.0 ns tPZH, tPZL OEA OAn tPLH GTLPIN OAn 3.6 6.5 3.8 6.5 1.5 4.4 6.5 1.5 4.0 6.0 0.2 1.0 ns tPHL tOSHL, tOSLH (Note 7) 0.5 0.5 ns tPLZ, tPHZ Common Edge Skew ns Note 6: All typical values are at VCC = 5.0V and TA = 25°C. Note 7: Skew specs are given for specific worst case VCC Temp. Skew values between the OBn outputs could vary on the backplane due to loading and impedance seen by the device. www.fairchildsemi.com 4 Test Circuit for A Outputs Test Circuit for B Outputs Note A: CL includes probes and jig capacitance. Note A: CL includes probes and jig capacitance. Note B: For B Port CL = 30 pF is used for worst case. Voltage Waveforms Enable and Disable Times A Port Voltage Waveforms Propagation Delay (Vm = VCC/2 for A Port and 1.0 for B Port) 5 www.fairchildsemi.com GTLP6C816 Test Circuit and Timing Waveforms GTLP6C816 GTLP/TTL 1:6 Clock Driver Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6