Revised October 1998 GTLP16612 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver General Description Features The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. ■ Bidirectional interface between GTLP and TTL logic levels Fairchild’s GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V and the receiver threshold is 1.0V. ■ Designed with Edge Rate Control Circuit to reduce output noise ■ VREF pin provides external supply reference voltage for receiver threshold ■ Submicron Core CMOS technology for low power dissipation ■ Special PVT Compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature ■ 5V tolerant inputs and outputs on A-Port ■ Bus-Hold data inputs on A-Port to eliminate the need for external pull-up resistors for unused inputs ■ Power up/down high impedance ■ TTL compatible Driver and Control inputs ■ A-Port outputs source/sink −32 mA/+32 mA ■ Flow-through architecture optimizes PCB layout ■ Open drain on GTLP to support wired-or connection Ordering Code: Order Number Package Number GTLP16612MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide Package Description GTLP16612MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 1998 Fairchild Semiconductor Corporation DS012390.prf www.fairchildsemi.com GTLP16612 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver March 1995 GTLP16612 Pin Descriptions Pin Names Connection Diagram Description OEAB A-to-B Output Enable (Active LOW) OEBA B-to-A Output Enable (Active LOW) CEAB A-to-B Clock Enable (Active LOW) CEBA B-to-A Clock Enable (Active LOW) LEAB A-to-B Latch Enable (Transparent HIGH) LEBA B-to-A Latch Enable (Transparent HIGH) CLKAB A-to-B Clock Pulse CLKBA B-to-A Clock Pulse VREF GTLP Input Reference Voltage A1–A18 A-to-B TTL Data Inputs or B-to-A 3-STATE Outputs B1–B18 B-to-A GTLP Data Inputs or A-to-B Open Drain Outputs Functional Description The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched and clock mode. The functional operation is described in the truth table below. Truth Table (Note 1) Inputs CEAB OEAB LEAB CLKAB A X H X X X Output B Mode Z Latched L L L H X B0(Note 2) storage L L L L X B0(Note 3) of A data X L H X L L Transparent X L H X H H L L L ↑ L L Clocked storage L L L ↑ H H of A data H L L X X B0(Note 3) Clock inhibit Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low. Note 3: Output level before the indicated steady-state input conditions were established. www.fairchildsemi.com 2 GTLP16612 Logic Diagram 3 www.fairchildsemi.com GTLP16612 Absolute Maximum Ratings(Note 4) Supply Voltage (VCC , VCCQ) −0.5V to +7.0V DC Input Voltage (VI) −0.5V to +7.0V Recommended Operating Conditions (Note 6) Supply Voltage VCC DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 5) −0.5V to +7.0V −0.5V to VCC + 0.5V 64 mA on A-Port and Control Pins −64 mA −50 mA +50 mA +34 mA B-Port Operating Temperature (TA) −50 mA VO > VCC www.fairchildsemi.com +32 mA A-Port 80 mA VO < 0V ESD Performance −32 mA A-Port −40°C to +85°C Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristic tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC Output Diode Current (IOK) Storage Temperature (TSTG) 0.0V to 5.5V LOW Level Output Current (IOL) DC Input Diode Current (IIK) VI < 0V 1.35V to 1.65V HIGH Level Output Current (IOH) DC Output Sink Current into B-Port in the LOW State, IOL 4.75V to 5.25V Input Voltage (VI) DC Output Source Current from A-Port IOH 3.15V to 3.45V Bus Termination Voltage (VTT) DC Output Sink Current into A-Port IOL VCC VCCQ −65°C to +150°C Note 5: IO Absolute Maximum Rating must be observed. >2000V Note 6: Unused inputs must be held high or low. 4 Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (Unless Otherwise Noted). Symbol Test Conditions Min Typ Max Units (Note 7) VIH VIL B-Port VREF +0.1 Others 2.0 B-Port VTT VREF −0.1 0.0 Others V 0.8 VREF 1.0 VCC = 3.15V, VIK V V II = −18 mA V −1.2 V VCCQ = 4.75V VOH VOL A-Port A-Port VCC, VCCQ = Min to Max (Note 8) IOH = −100 µA VCC = 3.15V IOH = −8 mA VCC − 0.2 2.4 VCCQ = 4.75V IOH = −32 mA 2.0 V VCC, VCCQ = Min to Max (Note 8) IOL = 100 µA 0.2 VCC = 3.15V IOL = 32 mA 0.5 V VCCQ = 4.75V II B-Port VCC = 3.15V VCCQ = 4.75V IOL = 34 mA 0.65 V Control Pins VCC, VCCQ = 0 or Max VI = 5.5V or 0V ±10 µA A-Port VCC = 3.45V VI = 5.5V 20 VCCQ = 5.25V VI = VCC 1 VI = 0 B-Port VCC = 3.45V VI = VCCQ 5 VCCQ = 5.25V VI = 0 −5 IOFF A-Port VCC = VCCQ = 0 VI or VO = 0 to 4.5V II(hold) A-Port VCC = 3.15V, VI = 0.8V 75 VCCQ = 4.75V VI = 2.0V −20 A-Port VCC = 3.45V, VO = 3.45V 1 B-Port VCCQ = 5.25V VO = 1.5V 5 A-Port VCC = 3.45V, VO = 0 −20 B-Port VCCQ = 5.25V VO = 0.65V −10 A or B VCC = 3.45V, Outputs HIGH 30 40 Ports VCCQ = 5.25V, Outputs LOW 30 40 IOZH IOZL ICCQ (VCCQ) µA −30 100 µA µA µA µA µA mA IO = 0, ICC (VCC) VI = VCCQ or GND Outputs Disabled 30 40 A or B VCC = 3.45V, Outputs HIGH 0 1 Ports VCCQ = 5.25V, Outputs LOW 0 1 mA IO = 0, VI = VCCQ or GND Outputs Disabled 0 1 ∆ICC A-Port and VCC = 3.45V, One Input at 2.7V 0 1 (Note 9) Control Pins VCCQ = 5.25V, mA A or Control Inputs at VCC or GND CIN Control Pins VI = VCCQ or 0 8 CI/O A-Port VI = VCCQ or 0 9 CI/O B-Port VI = VCCQ or 0 6 pF Note 7: All typicaI values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C. Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 5 www.fairchildsemi.com GTLP16612 DC Electrical Characteristics GTLP16612 AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fCLOCK Max Clock Frequency tW Pulse Duration tS Setup Time tH Hold Time Min Max Unit 175 MHz LEAB or LEBA HIGH 3.0 ns CLKAB or CLKBA HIGH or LOW 3.2 A before CLKAB↑ 0.5 B before CLKBA↑ 3.1 A before LEAB↓ 1.3 B before LEBA↓ 3.7 CEAB before CLKAB↑ 0.4 CEBA before CLKBA↑ 1.0 A after CLKAB↑ 1.5 B after CLKBA↑ 0.0 A after LEAB↓ 0.5 B after LEBA↓ 0.0 CEAB after CLKAB↑ 1.5 CEBA after CLKBA↑ 1.7 ns ns AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B-Port and CL = 50 pF for A-Port. Symbol tPLH From To (Input) (Output) A B tPHL tPLH LEAB B tPHL tPLH CLKAB B tPHL tPLH OEAB B tPHL Min Typ 6.5 5.0 8.2 1.8 4.5 6.7 1.5 5.3 8.6 1.8 4.6 6.7 1.5 5.4 8.7 1.6 4.4 6.2 1.3 6.1 9.8 Transition time, B outputs (20% to 80%) 2.6 Transition time, B outputs (20% to 80%) 2.6 B A tPLH LEBA A tPHL tPLH CLKBA A tPHL tPZH, tPZL OEBA A tPHZ, tPLZ Note 10: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C. www.fairchildsemi.com 6 ns 4.3 1.0 tRISE tPHL Unit 1.0 tFALL tPLH Max (Note 10) ns ns ns ns 2.0 5.6 8.2 1.4 5.0 7.2 2.1 4.2 6.3 1.9 3.3 5.0 2.3 4.4 6.8 2.2 3.5 5.2 1.5 5.0 6.2 1.9 3.9 7.9 ns ns ns ns Test Circuit for B Outputs Test Circuit for A Outputs CL includes probes and jig capacitance. For B-Port outputs, CL = 30 pF is used for worst case edge rate. CL includes probes and jig capacitance. Voltage Waveforms Pulse Duration (Vm = 1.5V for A-Port and 1.0V for B-Port) Voltage Waveforms Propagation Delay Times (A-Port to B-Port) Voltage Waveforms Propagation Delay Times (B-Port to A-Port) Voltage Waveforms Setup and Hold Times (Vm = 1.5V for A-Port and 1.0V for B-Port) All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. Voltage Waveforms Enable and Disable Times (A-Port) Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. 7 www.fairchildsemi.com GTLP16612 Test Circuits and Timing Waveforms GTLP16612 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package, JEDEC MO-118 0.300” Wide Package Number MS56A www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide Package Number MTD56 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. GTLP16612 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver Physical Dimensions inches (millimeters) unless otherwise noted