ETC GTLP6C816L

GTLP6C816
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GTLP-to-TTL 1:6 Clock Driver
Features
Product Description
• Bidirectional interface between GTLP and TTL
logic levels
Pericom Semiconductor’s GTLP series of logic circuits are produced
using the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading performance.
• Designed with Edge Rate Control Circuit to
reduce output noise on the GTLP port
The GTLP6C816 is a clock driver that provides TTL to GTLP signal
level translation (and vice versa). The device provides a high-speed
interface between cards operating at TTL logic levels and a backplane
operating at GTLP logic levels. High-speed backplane operation is
a direct result of GTLP’s reduced output swing (<1V), reduced input
threshold levels, and output edge-rate control which minimizes bus
settling times.
• Power up/down high impedance for live insertion
• 1:6 fanout clock driver for TTL port
• Lower Drive (12mA) on TTL Port to reduce noise
• 1:2 fanout clock driver for GTLP port
• TTL compatible driver and control inputs
Pericom’s GTLP has internal edge-rate control. Its function is similar
to BTL or GTL but with different output levels and receiver threshold.
GTLP output low voltage is typically less than 0.5V, the output level
HIGH is 1.5V and the receiver threshold is 1.0V.
• Flow -through architecture optimizes PCB layout
• Open drain on GTLP to support wired-or connection
• Operating Temperature: –40°C to +85°C
• Package:
– 24-Pin 173 mil wide plastic TSSOP (L24)
Logic Block Diagram
PinConfiguration
OEB
TTLIN
OA0
GNDT
OA1
VCCT
OA2
GNDT
OA3
VCCT
OA4
GNDT
OA5
OB0
TTLIN
OB1
OEA
OA0
GTLP
Ports
OA1
TTL
Ports
GTLPIN
OA5
1
24
1
23
2
22
3
21
4
20
5
24-Pin
19
6
L
18
7
17
8
9
16
10
15
11
14
12
13
GNDT
OEB
OB0
GNDG
VREF
GNDG
VCC
OB1
GNDG
GTLPIN
OEA
GNDT
PS8426A
03/15/00
GTLP6C816
GTLP-to-TTL
1:6
Clock
Driver
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Functional Description
For the GTLP -to-TTL direction, the clock receiver path is a 1:6 buffer
with a single Enable control (OEA). Data polarity is inverting for
both directions.
The GTLP6C816 is a clock driver that provides TTL to GTLP clock
translation, and GTLP-to-TTL clock translation. The TTL-to-GTLP
direction is a 1:2 clock driver path with a single Enable pin (OEB).
Pin Descriptions
Pin Name s
De s cription
TTLIN, GTLPIN
Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW) GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW) TTL Port (TTL Levels)
VCCT, GNDT
TTL Output Supplies (5V)
VCC
Internal Circuitry VCC (5V)
GNDG
OBn GTLP Output Grounds
VREF
Voltage Reference Input
OA0 - OA5
TTL Buffered Clock Outputs
OB0 - OB5
GTLP Buffered Clock Outputs
Truth Table
Inputs
Outputs
TTLIN
OEB
OBn
H
L
L
L
L
H
X
H
High Z
GTLPIN
OEA
OAn
H
L
L
L
L
H
X
H
High Z
2
PS8426A
03/15/00
GTLP6C816
GTLP-to-TTL
1:6
Clock
Driver
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Absolute Maximum Ratings(1)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage (VCC) .......................................................... –0.5V to +7.0V
DC Input Voltage (VI ) .......................................................... –0.5V to +7.0V
DC Output Voltage (VO)
Outputs 3-State .................................................................. –0.5V to +7.0V
Outputs Active(2) ............................................................... –0.5V to +7.0V
DC Output Sink Current into OA-Port IOL ......................................... 32mA
DC Output Source Current into OA-Port IOH ........................................... –32mA
DC Output Sink Current into OB-Port in the LOW State IOL ............. 80mA
DC Input Diode Current (IIK)
VI < 0V ............................................................................................ –50mA
DC Output Diode Current (IOK)
VO < 0V .......................................................................................... –50mA
VO > VCC ........................................................................................ +50mA
ESD Rating ....................................................................................... >2000V
Storage Temperature (TSTG) ............................................. –65°C to +150°C
Recommended Operating Condition(3)
Supply Voltage VCC ............................................................................ 4.75V to 5.25V
Bus Termination Voltage (VTT)
GTLP .................................................................................. 1.47V to 1.53V
VREF .......................................................................................................... 0.98V to 1.02V
Input Voltage (VI) on INA-Port and Control Pins ....................0.0V to 5.5V
HIGH Level Output Current (IOH)
OA-Port .......................................................................................... –12mA
LOW Level Output Current (IOL)
OA-Port .......................................................................................... +12mA
OB-Port .......................................................................................... +34mA
Operating Temperature (TA) ............................................... –40°C to +85°C
Notes:
1. Absolute Maximum continuous ratings are those values beyond which
damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional
opertion under absolute maximum rated conditions is not implied.
2. IO Absolute Maximum Rating must be observed
3. Unused inputs must be held HIGH or LOW.
3
PS8426A
03/15/00
GTLP6C816
GTLP-to-TTL
1:6
Clock
Driver
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DC Electrical Characteristics
(Over the recommended Operating Free-Air Temperature Range, VREF = 1.0 (Unless otherwise noted)
Symbol
VIH
VIL
VREF(5)
VTT(5)
VOL
VOL
II
IOFF
IOZH
M in.
GTLPIN
VREF +0.05
Others
2.0
GTLPIN
0.0
Typ.(4)
0.8
1.0
GTL
0.8
GTLP
1.5
GTL
1.2
VCC = 4.75V
OAn- Port
VCC = 4.75V
VCC = 4.75V
II = –18mA
–1.2
IOH = –100mA
VCC –0.2
IOH = –8mA
2.4
IOH = –12mA
2.2
IOL = 100mA
0.2
IOL = 8mA
0.4
IOL = 12mA
0.5
IOL = 100µA
0.2
IOL = 34mA
0.65
OBn- Port
VCC = 4.75V
TTLIN/
Control Pins
VCC = 5.25V
VI = 5.25V
VI = 0V
5
–5
GTLPIN
VCC = 5.25V
VI = VTT
VI = 0V
5
–5
TTLIN
VCC = 0
VI or VO = 0V to 5.25V
100
VO = 5.25V
5
VO = 1.5V
5
VCC = 5.25V
VO = 0
–5
VCC = 5.25V
Outputs HIGH
7
18
Outputs LOW
7
20
VI = VCC or GND
Outputs Disabled
7
20
VCC = 5.25V
VI = VCC –2.1
OAn- Port
OBn- Port
IOZL
OAn- Port
ICC
OAn or
OBn Ports
DICC
TTLIN
CIN
Control Pins/
GTLPPIN/TTLIN
COUT
OAn- Port
OBn- Port
Units
VREF –0.05
GTLP
OAn- Port
M ax.
VTT
Others
VIK
VOH
Te s t Conditions
VCC = 5.25V
V
mA
mA
6
VI = VCC or 0
3.5
VI = VCC or 0
7
VI = VCC or 0
7
pF
Notes:
4. All typical values are at VCC = 5.0V and TA = 25°C
5. GTLP, VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are
noisy. In addition, VTT and RTERM can be adjusted to accommodate backplane impedances other than 50W , within the boundaries of not
exceeding the DC Absolute IOL ratings. Similarly, VREF can be adjusted to compensate for changes in VTT.
4
PS8426A
03/15/00
GTLP6C816
GTLP-to-TTL
1:6
Clock
Driver
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AC Operating Requirements
(Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0 (Unless otherwise noted)
CL = 30pF for OBn-Port and CL = 50pF for OAn-Port.
Symbol
From (Input)
To (Output)
M in.
Typ.(6)
M ax.
Units
tPLH
tPHL
TTLIN
OBn
0.5
0.5
3.8
2.8
4.5
3.5
ns
tPLH
tPHL
OEB
OBn
1.5
1.5
6.4
3.2
6.5
5.0
tRISE
Transition Time. OB Outputs (20% to 80%)
2.3
tFALL
Transition Time. OB Outputs (20% to 80%)
2.3
tRISE
Transition Time. OA Outputs (10% to 90%)
2.0
tFALL
Transition Time. OA Outputs (10% to 90%)
2.0
tPZH, tPZL
tPLZ, tPHZ
OEA
OAn
0.5
0.5
3.6
3.8
6.5
6.5
tPLH
tPHL
GTLPIN
OAn
1.5
1.5
3.0
3.0
5.5
5.5
0.15
0.25
tOSHL, tOSLH(7)
Common Edge Skew
Notes:
6. All typical values are at VCC = 5.0V and TA = 25°C
7 Skew specs are given for specific worst case VCC Temp. Skew values between the OBn outputs could vary on the
backplance owing to loading and impedance seen by the device.
5
PS8426A
03/15/00
GTLP6C816
GTLP-to-TTL
1:6
Clock
Driver
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Test Circuits and Timing Waveforms
Test Circuit for A Outputs
From
Output
Under
Test
CL = 50pF
Test Circuit for B Outputs
6V
1.5V (GTLP)
1.2V (GTL)
Open
Gnd
500Ω
From
Output
Under
Test
500Ω
(Note A)
Test S
tPLH/tPHLOpen
tPLZ/tPZH 6V
tPHZ/tPZHGND
25Ω
30pF
(Notes A & B)
Notes:
A. CL includes probes and jig capacitance.
B. For B-Port outputs, CL = 30pF is used for
worst case.
Note A: CL includes probes and jig capacitance
Voltage Waveforms Enable
and Disable Times A-Port
Voltage Waveforms Propagation Delay
(Vm = 1.5V for A-Port and 1.0 for B-Port)
3.0V
1.5V
3.0V
1.5V
tPZL
Input
Vm V
1.5V
VOL+0.3V
tPZH
VOH-0.3V
1.5V
VOL
0V
tPHL
tPHL
VOH
Output
(1.5V for B-Port GTLP)
VOH
Vm V
(1.5V for B-Port GTLP)
VOL
VOH
VOL
24-Pin 173 Mil Wide Plastic TSSOP Package
24
.169
.177
1
4.3
4.5
.303
.311
7.7
7.9
.004
.008
.047
1.20
Max
.0256
BSC
0.65
.007
.012
0.19
0.30
.002
.006
0.45
0.75
SEATING
PLANE
0.09
0.20
.018
.030
.252
BSC
6.4
0.05
0.15
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
6
PS8426A
03/15/00