Revised December 2001 GTLP1B153 1-Bit LVTTL/GTLP Driver/Receiver Pair General Description Features The GTLP1B153 is a 1-bit bus buffer pair with separate bit paths, that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. ■ Interface between LVTTL and GTLP logic levels Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP’s I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are: VOL = 0.5V, VOH = 1.5V, and VREF = 1V. ■ Designed with edge rate control circuitry to reduce output noise in the GTLP port ■ VREF pin provides external supply reference voltage for receiver threshold adjustability ■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature ■ TTL compatible driver and control inputs ■ Designed using Fairchild advanced BiCMOS technology ■ Bushold data inputs on A Port to eliminate the need for external pull-up resistors for unused inputs ■ Power up/down and power off high impedance for live insertion ■ Open drain on GTLP to support wired-or connection ■ Flow through pinout optimizes PCB layout ■ A Port source/sink −24mA/+24mA ■ B Port sink +50mA Ordering Code: Order Number Package Number Package Description GTLP1B153M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] GTLP1B153MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] GTLP1B153K8X MAB08A (Preliminary) 8-Lead US8, 0.7mm x 3.1mm x 2.0mm [TAPE and REEL] Pin Descriptions Pin Names OEA Connection Diagrams US8 Description LVTTL Bit Level Output Enable (Active LOW for Receive) VCC, GND, VREF Device Supplies B O, B I B Port GTLP Outputs/ Inputs A O/ A I A Port LVTTL Outputs/ Inputs © 2001 Fairchild Semiconductor Corporation DS500485 SOIC www.fairchildsemi.com GTLP1B153 1-Bit LVTTL/GTLP Driver/Receiver Pair June 2001 GTLP1B153 Functional Description The GTLP1B153 is a 2-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting and the data flow in the B-to-A direction is controlled by the OEA pin. Functional Table Inputs OEA Outputs BI Description AO L L L L H H A Output Data Bit Enabled H X Z A Output Data Bit High Impedance OEA AI BO X L X H L A Output Data Bit Enabled B Output Data Bit Enabled H B Output Data Bit Enabled (Note 1) Note 1: Denotes that the bit would be in high impedance mode if there was no pull-up circuit due to open drain nature of the GTLP output. Logic Diagram www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions Outputs 3-STATE −0.5V to +4.6V Outputs Active (Note 3) −0.5V to +4.6V Bus Termination Voltage (VTT) DC Output Sink Current into GTLP 1.47V to 1.53V VREF 0.98V to 1.02V Input Voltage (VI) A Port IOL 48 mA on A Port and Control Pins DC Output Source Current from −48 mA A Port IOH 0.0V to VCC HIGH Level Output Current (IOH) −24 mA A Port DC Output Sink Current into LOW Level Output Current (IOL) 100 mA B Port in the LOW State, IOL +24 mA A Port DC Input Diode Current (IIK) +50 mA B Port VI < 0V −50 mA VO < 0V Note 2: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −50 mA >2000V ESD Rating −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) Storage Temperature (TSTG) 3.15V to 3.45V Supply Voltage VCC DC Output Voltage (VO) −65°C to +150°C Note 3: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL Min Test Conditions Typ B Port VREF + 0.05 Others 2.0 B Port 0.0 VTT VREF − 0.05 Others VREF B Port VTT B Port VIK VOH VOL A Port A Port B Port II Control Pins 0.8 0.7V 1.0 VREF + 50 mV 1.5 VCC = 3.15V II = −18 mA VCC = Min to Max (Note 5) IOH = −100 µA VCC = 3.15V IOH = −8 mA 2.4 IOH = -24 mA 2.2 IOFF V V V IOL = 100 µA 0.2 IOL = 8 mA 0.4 VCC = 3.15V IOL = 24 mA 0.5 VCC = 3.15V IOL = 40 mA 0.4 IOL = 50 mA 0.55 VCC = 3.45V VCC = 3.45V V V VCC VCC = 3.15V VCC = 3.45V V −1.2 VCC = Min to Max (Note 5) VI = 3.45V 5 −5 VI = 3.45V 10 VI = 0V B Port 1.3V Units VCC - 0.2 VI = 0V A Port Max (Note 4) −10 VI = 3.45V 5 V V µA µA µA VI = 0 −5 VCC = 0 VI or VO = 0 to 3.45V 30 µA B Port VCC = 0 VI or VO = 0 to 3.45V 30 µA A Port VCC = 3.15V VI = 0.8V A Port, Control Pins II (HOLD) IOZH A Port B Port VCC = 3.45V 75 VI = 2.0V −75 VO = 3.45V 10 VO = 3.45V 5 3 µA µA www.fairchildsemi.com GTLP1B153 Absolute Maximum Ratings(Note 2) GTLP1B153 DC Electrical Characteristics Symbol IOZL A Port (Continued) Min Test Conditions VCC = 3.45V B Port Typ Max (Note 4) VO = 0V −10 VO = 0V −5 IPU/PD All Ports VCC = 0 to 1.5V VI = 0 to 3.45V 30 ICC A Port VCC = 3.45V Outputs HIGH 11 or B Port µA IO = 0 Outputs LOW 11 Outputs Disabled 11 One Input at VCC 2 mA 3 pF A Port and VCC = 3.45V, (Note 6) Control Pins A or Control Inputs at VCC or GND −0.6V CO µA VI = VCC/VTT or GND ∆ICC Ci Units mA Control Pins VI = VCC, A and B Port VTT or 0 A Port VI = VCC or 0 5 pF B Port VI = VTT or 0 5 pF Note 4: All typical values are at VCC = 3.3V and TA = 25°C. Note 5: For conditions shown as Min, use the appropriate value specified under recommended operating conditions. Note 6: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Note: GTLP V REF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50Ω, but must remain within the boundaries of the DC Absolute Maximum Ratings. Similarly, VREF can be adjusted to optimize noise margin. AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tPLH tPHL tPLH tPHL From To (Input) (Output) A B B A Min Typ Max (Note 7) 1.2 2.9 7.3 0.8 2.0 4.5 1.4 2.5 4.4 1.6 2.7 5.0 Unit ns ns tRISE Transition Time, B Outputs (20% to 80%) 1.5 tFALL Transition Time, B Outputs (80% to 20%) 1.8 ns tRISE Transition Time, C Outputs (10% to 90%) 2.5 ns tFALL Transition Time, C Outputs (90% to 10%) tPZH, tPZL tPHZ, tPLZ OEA A Note 7: All typical values are at VCC = 3.3V, and TA = 25°C. www.fairchildsemi.com 4 ns 2.2 ns 1.2 2.7 5.3 1.4 2.8 4.9 ns Test Circuit for A Outputs Test Test Circuit for B Outputs S tPLH/tPHL OPEN tPLZ/tPZL Note: CL includes probes and Jig capacitance. Note: For B Port, CL = 30 pF is used for worst case. 6V tPHZ/tPZH GND Note: C L includes probes and Jig capacitance. Voltage Waveforms Propagation Delay Voltage Waveform Enable and Disable Times A or LVTTL Pins B or GTLP Pins VINHIGH VCC 1.5 VINLOW 0.0 0.0 VM VCC/2 1.0 VX VOL + 0.3V N/A VY VOH − 0.3V N/A Note: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Note: All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. 5 www.fairchildsemi.com GTLP1B153 Test Circuits and Timing Waveforms GTLP1B153 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A www.fairchildsemi.com 6 GTLP1B153 1-Bit LVTTL/GTLP Driver/Receiver Pair Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead US8, 0.7mm x 3.1mm x 2.0mm Package Number MAB08A Preliminary Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com