HD151BF853 2.5 V PLL Clock Buffer for DDR Application ADE-205-692B (Z) Preliminary Rev.2 Sep. 2002 Description The HD151BF853 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically designed for use with DDR (Double Data Rate) PC mother board application. Features • • • • • • • Designed for DDR200/266/333/400 PC mother board clock buffering Supports 60 MHz to 210 MHz operation range Distributes one to ten differential clock outputs pairs Spread spectrum clock compatible External feedback pin (FBIN) is used to synchronize the outputs to the clock input Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD151BF853SSEL SSOP-48 pin SS EL (1,000 pcs / Reel) Note: Please consult the sales office for the above package availability. HD151BF853 Key Specifications • Supply voltages: VDD = AVDD = 2.5 V±0.2 V • Output clock cycle to cycle jitter = ±75 ps • Output clock pin to pin skew = 150 ps max Function Table Inputs Outputs AVDD CLK Yn Yn FBOUT PLL GND L L H L Bypass / Off GND H H L H Bypass / Off 2.5 V (typ.) L L H L Running 2.5 V (typ.) H H L H Running H: High level L: Low level Rev.2, Sep. 2002, page 2 of 10 HD151BF853 Pin Arrangement 48 GND GND 1 Y0 2 47 Y5 Y0 3 46 Y5 45 VDD VDD 4 Y1 5 44 Y6 Y1 6 43 Y6 GND 7 42 GND GND 8 41 GND Y2 9 40 Y7 Y2 10 39 Y7 38 VDD VDD 11 NC 12 37 NC CLKIN 13 36 NC NC 14 35 FBIN VDD 15 34 VDD AVDD 16 33 FBOUT AGND 17 32 NC 31 GND GND 18 Y3 19 30 Y8 Y3 20 29 Y8 28 VDD VDD 21 Y4 22 27 Y9 Y4 23 26 Y9 GND 24 25 GND (Top view) Rev.2, Sep. 2002, page 3 of 10 HD151BF853 Logic Diagram AVCC CLKIN 16 Test Logic 13 PLL FBIN 35 Note: All inputs and outputs are associated with VDDQ = 2.5 V. Rev.2, Sep. 2002, page 4 of 10 3 2 Y0 5 6 Y1 10 9 Y2 20 19 Y3 22 23 Y4 46 47 Y5 44 43 Y6 39 40 Y7 29 30 Y8 27 26 Y9 33 FBOUT Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 HD151BF853 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VDD –0.5 to 3.6 V Input voltage VI –0.5 to VDD+0.5 V Output voltage *1 VO –0.5 to VDD+0.5 V Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VDD 0.7 W –65 to +150 °C Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Tstg Conditions Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. Recommended Operating Conditions Item Symbol Min Typ Max Unit Conditions Supply voltage AVDD 2.3 2.5 2.7 V Output supply voltage VDD 2.3 2.5 2.7 V –0.3 — VDD+0.3 V All pins DC input signal voltage High level input voltage VIH 1.7 — 3.6 V CLKIN High level input voltage VIH 1.7 — VDD+0.3 V FBIN Low level input voltage VIL –0.3 — 0.7 V CLKIN, FBIN Output differential cross point voltage VOX 0.5×VDD –0.2 — 0.5×VDD +0.2 V Output current IOH — — –12 mA IOL — — 12 Input clock slew rate SR 1 — — V/ns Operating temperature Ta 0 — 70 °C Note: Unused inputs must be held high or low to prevent them from floating. Rev.2, Sep. 2002, page 5 of 10 HD151BF853 Electrical Characteristics Item Symbol Min Typ *1 Max Unit Test Conditions Input clamp voltage (All inputs) VIK — — –1.2 V II = –18 mA, VDD = 2.3 V Output voltage VOH VDD–0.2 — — V IOH = –100 µA, VDD = 2.3 to 2.7 V 1.7 — VDD IOH = –12 mA, VDD = 2.3 V — — 0.2 IOL = 100 µA, VDD = 2.3 to 2.7 V — — 0.6 IOL = 12 mA, VDD = 2.3 V VOL Input current II –10 — 10 µA VI = 0 V or 2.7 V, VDD = 2.7 V, CLKIN, FBIN Analog supply current AICC — — 12 mA VDD = AVDD = 2.7 V, 170 MHz Dynamic supply current DICC — 250 300 mA VDD = AVDD = 2.7 V, 170 MHz All Yn, Yn, = open CI 2.5 — 3.5 pF CLKIN and FBIN CDi –0.25 — 0.25 pF Input capacitance*2 2 Delta input capacitance* Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Target of design, not 100% tested in production. Rev.2, Sep. 2002, page 6 of 10 HD151BF853 Switching Characteristics Ta = 25°C, VDD = AVDD = 2.5V Item Symbol Min Typ Max Unit Test Conditions & Notes Period jitter tPER –75 0 75 ps *7, 8 Half period jitter tHPER –120 0 120 ps *8 Cycle to cycle jitter tCC –75 0 75 ps Static phase offset tsPE –150 — 150 ps Output clock skew tsk — — 150 ps Operating clock frequency fCLK(O) 60 — 210 MHz *1, 2 Application clock frequency 80 166 210 MHz *1, 3 Slew rate 1.0 — 2.0 V/ns 20% to 80% Stabilization time — — 0.1 ms fCLK(A) *4, 5 *6 Notes: Target of design, not 100% tested in production. 1. The PLL must be able to handle spread spectrum induced skew. (the specification for this frequency modulation can be found in the latest Intel PC100 Registered DIMM specification) 2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 3. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 4. Assumes equal wire length and loading on the clock output and feedback path. 5. Static phase offset does not include jitter. 6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of it’s feedback signal to it’s reference signal after power on. 7. Period jitter defines the largest variation in clock period, around a nominal clock period. 8. Period jitter and half period jitter are separate specifications that must be met independently of each other. Rev.2, Sep. 2002, page 7 of 10 HD151BF853 Zo = 60 Ω Yn *1 RT = 120 Ω C = 14 pF Zo = 60 Ω Yn *1 C = 14 pF Note: 1. SDRAM Cin 3.5 pF ×4 Figure 1 Clock outputs test circuit Yn Yn tcycle n tcycle n+1 t CC = (tcycle n) - (tcycle n+1) Figure 2 Cycle to cycle jitter Yx Yx Yy Yy tsk Figure 3 Output clock skew (Differential clock output) Rev.2, Sep. 2002, page 8 of 10 HD151BF853 Package Dimensions 15.85 ± 0.3 25 1 24 0.635 0.25 ± 0.1 0.15 0.13 M 0.10 Min 0.78 Max 0.15 ± 0.05 2.65 Max 7.50 ± 0.3 48 10.40 ± 0.4 1.45 0˚ - 10˚ 0.60 ± 0.2 Rev.2, Sep. 2002, page 9 of 10 HD151BF853 Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 7.0 Rev.2, Sep. 2002, page 10 of 10