King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 Preliminary Product Specification Product Name KB Doc. No. Command Interface 8M-Bit Mask ROM with Expansion I/O HF88M32 KB Product. No. HF88M32 - Table of Contents – 1. General Description _____________________________________________________2 2. Features ______________________________________________________________2 3. Functional block diagram ________________________________________________3 4. Pin Description_________________________________________________________3 5. Device Operation _______________________________________________________4 5.1. Retrieve data in Data File _________________________________________________ 6 5.2. Loading the Address Counter______________________________________________ 6 5.3. Sequential Read Mode and Auto Increment of Address Counter _________________ 7 5.4. Output data to External I/O _______________________________________________ 7 5.5. Reading Input pin status__________________________________________________ 7 5.6. Retrieving the Contents of Expansion I/O registers ____________________________ 8 6. Timing Diagrams _______________________________________________________8 6.1. Data File Read Cycle _____________________________________________________ 8 6.2. Interrupted by I/O when Loading Address Counter ___________________________ 9 6.3. Setting and Reading the I/O Mode for P0 and P1 _____________________________ 9 6.4. Reading P0 and P1 in Mixed-I/O Mode______________________________________ 9 6.5. Reading the input pins __________________________________________________ 10 6.6. Output to P0 and P1 ____________________________________________________ 10 7. Absolute Maximum Rating ______________________________________________ 11 8. AC Electrical Characteristics ____________________________________________ 11 9. DC Electrical Characteristics ____________________________________________12 10. Application Circuit Diagram ___________________________________________12 April 28, 2003 1 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 1. General Description The HF88M32 is a command interfaced 4M x 8 bit Mask ROM. It features command mode interface with external CPU or MCU. In other words, it uses only 8-bit data bus and a few additional control pins to load addresses and provide the ROM access as well as expansion I/O ports capability. This design not only reduces pin count required to access data in ROM dramatically but also allows for systems expansion to higher capacity memories while using the existing board design. The application areas include voice, graphic, data storage in consumer product. 2. Features 9 9 9 9 9 9 9 Data File Mode with only 11 pin interface Sixteen-bit Expansion I/O pins with three-state mode Voltage range: 2.4 ~ 3.6V Organization Memory Cell Array: 4M x 8 Sequential Read Operation in Data File Operation Mode Sequential Access : 100 ns (min.) at VDD = 3.3V Command/Address/Data Multiplexed I/O port Low Operation Current (Typical) 10 µA standby mode current. 30 mA active read current at 100 ns cycle time. 9 Package: bare chip - April 28, 2003 2 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 3. Functional block diagram X BUFFER & DECODER Y BUFFER & DECODER MEMORY CELL ARRAY SENSE AMP. CEn CONTROL LOGIC OEn WEn AC0 AC1 AC2 P0 P1 DIR0 DIR1 [A21..A0] RS2..RS0 [D7.. D0] [P00..P07] [P10..P17] 4. Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 RS2 RS1 P07 P06 P05 P04 P03 P02 P01 P00 CE GND OE D0 NC D1 NC D2 NC D3 NC NC WE P10 P11 P12 P13 P14 P15 P16 P17 RS0 NC GND NC D7 NC D6 NC D5 NC D4 VCC 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 HF88M32 Symbol RS0~RS2 Pin No. I/O Description 33, 2, 1 I Register Select pins RS2 ~ RS0 for accessing ROM data, Address Counter, as well as expansion I/O ports. P07 ~ P00 3 ~ 10 I/O Bi-directional I/O port P0. April 28, 2003 3 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 Symbol CEn GND OEn VCC D7 ~ D0 P17 ~ P10 WEn 億 電 子 股 份 有 限 公 司 HF88M32 Pin No. I/O Description 11 I The CEn (Chip Enable) input is the device selection and power control for internal Mask ROM array. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode and the contents of the ROM and registers can be accessed. Please note that only accesses to the internal registers are inhibited, but the status of I/O registers are not affected by the CEn pin and will remain unchanged. CEn is also useful to uniquely select a certain device for applications where multiple-chip array is required. 12, 31 P Negative power supply input pin. 13 I OEn (Output Enable) is the output control which gates ROM array data, expansion I/O ports, Direction Registers to the data I/O pins D7 ~ D0. The internal Address Counter will automatically increment by one with each rising edge of OEn pin in Sequentially Read mode. 22 P Postive power supply input pin. 14, 16, I/O The Bi-directional Data I/O pins are used to set starting 18, 20, addresses, set the Extension I/O Direction and Output Registers, 23, 25, and to output ROM array data during read operations, contents 27, 29 of I/O Registers and status of input pins. The D7 ~ D7 float to high-impedance when the chip is deselected (CEn high) or when the outputs are disabled. 34 ~ 41 I/O Bi-directional I/O port P1. 42 I WEn controls writing to internal registers such as the Output Port Registers, Direction Registers, Address Counter and Data on D7 ~ D0 are latched on the rising edge of the WE pulse. 5. Device Operation The device provides the capability of accessing the contents of ROM array by external MCU not through standard address and data bus configuration but through minimal number of 8-bit data bus and control pins. Only 11 pins D7 ~ D0, CEn, OEn, WEn are required to use the device as a Data File device. By fixing the RS2 to ‘0’, only CEn, WEn, OEn and D0 ~ D7 are required to access the ROM array data. The CEn pin is device selection pin to uniquely select one device when more than one device are used in parallel and control the access to Mask ROM contents and internal registers. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode. Therefore, when accessing contents of ROM is not intended, CEn should stay at ‘1’ to conserve the power. April 28, 2003 4 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 In addition to Data File mode, the device also provides the expansion I/O capability. Two ports of I/O pins (8 bit each) are provided. The I/O ports can be configured to function as output pin or high-impedance input pins. Only 14 pins, CEn, WEn, OEn, RS2, RS1 and D0 ~ D7 are required to provide the Data File function and full access to two I/O ports. There are seven internal registers used to provide the functionality of Data file as well as Expansion I/O capability. These registers are selected by RS2 ~ RS0. All registers are 8-bit wide except AC2. AC2 ~ AC0 are write-only and constitute the complete 22-bit Address Counter used as pointer to the data. While the P0, P1, DIR0 and DIR1 can be read as well as written. Their initial values are as indicated in the following table. When RS2 = ‘0’, the RS1 ~ RS0 are ignored, the Address Counter can be loaded or contents of Data File can be read. This is to reduce the required pin needed for external MCU to interface with the Device and also simplify the procedure for loading the address counter. The P0, P1, DIR0, and DIR1 are used for expansion I/O registers. The P0 and P1 are output registers of Expansion I/O and DIR0 and DIR1 are the Direction Registers that determine the I/O mode of P0 and P1. Each pin can be configured as output or input mode individually by setting or resetting the corresponding pin of the DIR registers. Initially, both P0 and P1 are D0 DIR00 DIR00 Q DIR10 D D RS = 100 & OEn = '0' RS = 110 & OEn = '0' P00 P00 Q Q P10 D D Q 1 1 0 P10 RS = 101 & OEn = '0' RS = 111 & OEn = '0' 0 default to input mode at ‘Hi’ state. April 28, 2003 5 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 The accesses to the internal registers will be inhibited when CEn is ‘1’. However, the status of internal registers, such as expansion I/O ports, will not be affected. For example, if a certain pin is in output mode and driving ‘Hi’, it will not change when CEn pin goes to ‘1’ state. Therefore, the users are advised to take care of the power down condition of I/O ports when entering sleep mode to prevent unnecessary power drain. RS2RS1RS0 Symbol 0xx AC2 AC1 AC0 100 P0 101 DIR0 110 P1 111 DIR1 Type R W W W R/W R/W R/W R/W Description Read data by Indirect access Address latch 2 for A21 ~ A16 Address latch 1 for A15 ~ A8 Address latch 0 for A7 ~ A0 Port 0 Output Register Direction Register 0 Port 1 Output Register Direction Register 0 Initial Value “--------“ “--------“ “--------“ “11111111“ “00000000“ “11111111“ “00000000“ 5.1. Retrieve data in Data File Accesses to the ROM contents, expansion I/O, Address Counter and Direction registers are made through 8 Data I/O pins – D7 ~ D0. With Register Selection RS = “0xx”, the starting addresses can be written through Data I/Os by bringing WEn to low and back to high. Addresses are latched on the rising edge of WEn. Once the starting address of data block is latched into the Address Counter, data may be read out by sequentially pulsing OEn with CEn staying low. When at ‘0’, the OEn gate the data of the selected address unto Data I/O pin D7 ~ D0. With the rising edge of OEn, the internal Address Counter is incremented by one automatically. 5.2. Loading the Address Counter Before the data can be retrieved, the Address Counter must be initialized with the starting address, then the contents of ROM pointed to by Address Counter (AC) can be accessed through D7 through D0. In order to simplify the procedure of loading 22-bit Address Counter (AC), a internal pointer is implemented and used to point to next register to write in the up to three-cycle address loading sequence. Initially, with RS = “0xx” CEn goes from ‘1’ to ‘0’ and the AC pointer is initialized. The pointer is then incremented to point to next register with falling edge of each WEn pulse. So when randomly accessing data within a 256-byte page, or within a 64K-byte block mode, then only one or two-cycle address reload process is needed to access different locations within a page or block. April 28, 2003 6 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 The Address Counter pointer will be held in reset state in the following conditions: 1. 2. When CEn is '1' (the device is deselected). By the Read pulse (OEn is '0') and RS2 = '0' (ROM is being accesses). The inclusion of the 3rd condition is to force the address loading to start from LSB of Address Counter once the read cycle is initiated. However, the AC Pointer will not be reset when reading or writing from/to expansion I/O registers (P0, P1, DIR0, DIR1). This design is useful in certain application scenarios where in the midst of the multi-byte address loading process, an interrupt to the MCU main loop occurs. And in the interrupt service routine, manipulation of expansion I/O registers is performed, i.e., key board is scanned using P0 and P1. When the execution of program returns to main loop after interrupt service routine completed, the loading of address can still resume from where it was interrupted. 5.3. Sequential Read Mode and Auto Increment of Address Counter With each read access to the ROM data (RS = “0xx”), the Address Counter is incremented automatically by one with rising edge of OEn to facility sequential access to a block of ROM data and avoid repeated loading of addresses. 5.4. Output data to External I/O The device’s 16-bit Expansion I/O capability provides additional I/O ports for applications where the I/O pin are heavily used. To use as a certain pin as output pin, the corresponding bit in Direction Register must be set to ‘1’. Please refer to the following example where output 0x00 to P0 to ‘0’ is intended. 1. 2. 3. 4. 5. 6. Set RS to “101” (DIR0). Keep D7 ~ D0 at 0xff (all bits in output mode). Pulse the WEn to low then high to write to write contents of D-bus to DIR0. Set RS to “100” (P0 Output Register). Set D7 ~ D0 to 0x00. Pulse the WEn to low then high to write contents of D-bus to P0 and drive all bits in P0 to low. 5.5. Reading Input pin status To use expansion I/O ports as input pins and read the status from them, the corresponding bit April 28, 2003 7 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 in direction register must be set to ‘0’. Please see the following example where reading inputs from of P1 is intended. 1. 2. 3. 4. 5. 6. Set RS to “111” (DIR1). Set D7 ~ D0 to 0x00. Pulse the WEn to low then high to set DIR1 to all High-Impedance input mode. Set RS to “110” (P1 Output Register). Pulse the OEn to low. Read P1 then set the OEn back to high. There is one thing should be noted. For any unused (open) expansion I/O pin, it is advisable to set the port to output mode either at ‘0’ or ‘1’ state to prevent it from floating or fix it at VCC or GND if it is set to input mode. Otherwise, the noise might cause the unnecessary power consumption. 5.6. Retrieving the Contents of Expansion I/O registers The contents of all four registers can be read through data bus. The ability to access the contents of registers avoids the necessity of using the RAM as mirror to keep the current status of latches in applications. However, extra care should be taken when reading P0 and P1. To read the contents of P0 and P1, the DIR0 and DIR1 should be set to output mode. Otherwise, the pin status instead of P0 and P1 will be read. The same precaution should be applied in Read-Modify-Write sequence that read back the contents of the output latch of output mode pins and input status of input mode pins. 6. Timing Diagrams 6.1. Data File Read Cycle April 28, 2003 8 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 6.2. Interrupted by I/O when Loading Address Counter 6.3. Setting and Reading the I/O Mode for P0 and P1 6.4. Reading P0 and P1 in Mixed-I/O Mode April 28, 2003 9 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 6.5. Reading the input pins 6.6. Output to P0 and P1 April 28, 2003 10 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HF88M32 7. Absolute Maximum Rating Items Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VCC VIN TOPR TSTR Rating 2.4 ~ 3.6 V -0.3 to Vdd+0.3 V -0 to 70 °C -55 to 125 °C 8. AC Electrical Characteristics READ CYCLE: There are two ways of accessing the ROM data. The first one is to assert the valid address on the Address Bus, then assert CEn “low” to enable the ROM array. The access time in this mode is specified as tACE. The advantage of this access mode is that power consumption can be lowered. The second access mode keeps the CEn “low” while changes the addresses to access the contents of ROM data. The access time in this way is specified as tAA. Item Read Cycle Time Symbol tRC Chip Enable Access Time tACE Address Access Time tAA Output Enable Time Output or Chip Disable to Output High-Z tOE tDF April 28, 2003 Min 100 120 11 Max Unit ns 100 120 100 120 50 20 ns ns Condition VCC = 3.0 V, no load VCC = 2.4V, no load VCC = 3.0 V, no load VCC = 2.4V, no load VCC = 3.0 V, no load VCC = 2.4V, no load ns ns V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 Output Hold from Address Change 股 份 有 限 0 tOH 公 司 HF88M32 ns 9. DC Electrical Characteristics (GND = 0V, VCC = 3.0V, TOPR = 25°C unless otherwise noted) Parameter Supply Voltage Operating Current Standby Current Input voltage Input current leakage P0, P1 Output High Voltage P0, P1 Output Low Voltage D Output High Voltage D Output Low Voltage Symbol Min. Typical Max. Unit VCC ICC ISTBY VIH VIL IIL VOH 2.4 2/3 0 2.4 30 10 - 3.6 1 1/3 +/- 10 - V mA µA Condition No load, tRC@ 100 ns No load VCC VCC = 2.4V ~ 3.6V µA V IOH = 0.3 mA VOL - - 0.4 V IOL = 2.1 mA VOH VOL 2.4 - - 0.4 V V IOH = 1.4 mA IOL = 3 mA 10. Application Circuit Diagram This application circuit illustrates that how KB83760 MCU uses two external HF88M32s for ROM expansion as well as keyboard scan functions. April 28, 2003 12 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 HF88M32 司 PWMP PWMN COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 D1 D2 D5 D3 D4 VDD HF88M32 R2 330K R3 330K R4 330K R5 330K R1 VDD R2 R3 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 R4 D2 1N4148 K2 K1 1 D3 1N4148 K3 D4 1N4148 K4 D4 VDD D5 1N4148 K5 2 D1 SXI SXO TSTP FXI FXO RSTP OPO OPIP OPIN DAO D5 C7 C6 C5 C4 C3 C2 C1 VDD R1 330K D6 HF88M32 1 D0 D1 D2 D3 D4 D5 D6 D7 KTONE SDO DTMFO MUTE D7 1 D3 OEn D0 D6 D6 1N4148 K6 D7 1N4148 K7 1N4148 2 D2 CE2n D7 WEn 1 D1 RS0 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 2 OEn D0 NC WE P10 P11 P12 P13 P14 P15 P16 P17 RS0 NC VSS NC D7 NC D6 NC D5 NC D4 VCC RS2 RS1 P07 P06 P05 P04 P03 P02 P01 P00 CE VSS OE D0 NC D1 NC D2 NC D3 NC 1 PRT110 PRT111 PRT112 PRT113 PRT114 PRT115 PRT116 PRT117 PRT100 PRT101 PRT102 PRT103 PRT104 PRT105 PRT106 PRT107 RS0 RS1 RS2 OEn WEn CE1n CE2n U3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 WEn R1 R2 R3 R4 R5 2 KB83760 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 PRT110 PRT111 PRT112 PRT113 PRT114 PRT115 PRT116 PRT117 PRT100 PRT101 PRT102 PRT103 PRT104 PRT105 PRT106 PRT107 PRTC0 PRTC1 PRTC2 PRTC3 PRTC4 PRTC5 PRTC6 PRTC7 PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 KEYTONE SDO DTMFO MUTE VDD SXI SXO TSTP FXI FXO RSTP OPO OPIP OPIN DAO NC WE P10 P11 P12 P13 P14 P15 P16 P17 RS0 NC VSS NC D7 NC D6 NC D5 NC D4 VCC RS2 RS1 P07 P06 P05 P04 P03 P02 P01 P00 CE VSS OE D0 NC D1 NC D2 NC D3 NC 2 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 U2 2 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LC1 LC2 LV1 LV2 LV3 LR4 LR3 LR2 LR1 LR0 LVG GND VO SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 PWMN PWMP C7 C6 C5 C4 C3 C2 C1 CE2n 2 RS2 RS1 U1 1 2 3 Auto Erase M1 M6 K8 K9 K10 K11 K12 K13 K14 4 5 6 Pause UP M2 M7 K15 K16 K17 K18 K19 K20 K21 7 8 9 Flash DOWN M3 M8 K22 K23 K24 K25 K26 K27 K28 * 0 # Redial Name M4 M9 K29 K30 K31 K32 K33 K34 K35 Mute HF HOLD Dial M5 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 VO R5 PGM M10 C10 1uF VDD C7 C8 C9 1uF 1uF C1 1uF C2 1uF C3 1uF C4 1uF C5 1uF C6 1uF 1uF April 28, 2003 13 V1.0 This specification is subject to change without notice. Please contact sales person for the latest version before use.