KB HF88M08

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HF88M08
- Table of Contents 1
Function Description______________________________________________________________2
2
Features ________________________________________________________________________2
3
Functional block diagram __________________________________________________________3
4
Pin Description __________________________________________________________________4
5
Pad Location ____________________________________________________________________5
6
Device Operation _________________________________________________________________6
7
6.1
Retrieve data in Data File ____________________________________________________________8
6.2
Loading the Address Counter _________________________________________________________8
6.3
Sequential Read Mode and Auto Increment of Address Counter ____________________________9
6.4
Output data to External I/O __________________________________________________________9
6.5
Reading Input pin status _____________________________________________________________9
6.6
Retrieving the Contents of Expansion I/O registers _______________________________________9
Timing Diagrams ________________________________________________________________10
7.1
Data File Read Cycle _______________________________________________________________11
7.2
Interrupted by I/O when Loading Address Counter______________________________________12
7.3
Setting and Reading the I/O Mode for P0 and P1 ________________________________________13
7.4
Reading P0 and P1 in Mixed-I/O Mode ________________________________________________14
7.5
Reading the input pins ______________________________________________________________15
7.6
Output to P0 and P1 Ports___________________________________________________________16
8
Absolute Maximum Rating ________________________________________________________16
9
AC Electrical Characteristics ______________________________________________________16
10
DC Electrical Characteristics ____________________________________________________17
11
Application Circuit Diagram _______________________________________________________17
12
Updated History _______________________________________________________________19
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1 Function Description
The HF88M08 is a command interfaced 1M x 8 bit Mask ROM. It features command mode interface with
external CPU or MCU. In other words, it uses only 8-bit data bus and a few additional control pins to
load addresses and provide the ROM access as well as expansion I/O ports capability. This design not
only reduces pin count required to access data in ROM dramatically but also allows for systems
expansion to higher capacity memories while using the existing board design. The application areas
include voice, graphic, data storage in consumer product.
2 Features
9
9
9
9
9
9
9
Data File Mode with only 11 pin interface
Sixteen-bit Expansion I/O pins with three-state mode
Voltage range 2.4V ~ 5.5V
Organization
Memory Cell Array: 1M x 8
Sequential Read Operation in Data File Operation Mode
Sequential Access : 120ns (min.) at VDD = 5.0V
Command/Address/Data Multiplexed I/O port
Low Operation Current (Typical)
-
10µA Standby mode Current
10mA Active Read Current
9 Package bare chip, PLCC32
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3 Functional block diagram
X BUFFER &
DECODER
Y BUFFER &
DECODER
MEMORY
CELL
ARRAY
SENSE
AMP.
CEn
CONTROL
LOGIC
OEn
WEn
AC0
AC1
AC2
P0
P1
DIR0
DIR1
[AC18..A0]
RS2..RS0
[D7.. D0]
[P00..P07]
[P10..P17]
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HF88M08
P14
P17
RS0
WE
VDD
RS2
RS1
4
3
2
1
32
31
30
4 Pin Description
P16
P15
P10
P11
P13
OE
P12
CE
D7
P07
P06
P05
P04
P03
P02
P01
P00
D0
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
D1
D2
VSS
D3
D4
D5
D6
5
6
7
8
9
2
11
12
13
HF88M08-PLCC32
Symbol
VDD
VSS
CEn
Pin No. I/O
Description
32
P Positive power supply input pin.
16
P Gound pin.
22
I The CEn (Chip Enable) input is the device selection and power control for
internal Mask ROM array. Whenever CEn goes high, the internal Mask
ROM will enter standby (power saving) mode and accesses to internal
registers are inhibited. Otherwise, it is in active mode and the contents of
the ROM and registers can be accessed. Please note that only accesses to
the internal registers are inhibited, but the status of I/O registers are not
affected by the CEn pin and will remain unchanged. CEn is also useful to
uniquely select a certain device for applications where multiple-chip array is
required.
WEn
1
I WEn controls writing to internal registers such as the Output Port Registers,
Direction Registers, Address Counter and Data on D7 ~ D0 are latched on
the rising edge of the WE pulse.
OEn
24
I OEn (Output Enable) is the output control which gates ROM array data,
expansion I/O ports, Direction Registers to the data I/O pins D7 ~ D0. The
internal Address Counter will automatically increment by one with each
rising edge of OEn pin in Sequentially Read mode.
RS2~RS0
I Register Select pins RS2 ~ RS0 for accessing ROM data, Address Counter,
as well as expansion I/O ports.
P17 ~ P10
I/O Bi-directional I/O port P1.
P07 ~ P00
I/O Bi-directional I/O port P0.
D7 ~ D0
21 ~ 17, IO The Bi-directional Data I/O pins are used to input Starting Address, setting
15 ~13
the Expansion I/O direction and Output Registers, and to output ROM array
data during read operations, contents of I/O Registers and status of input
pins. The D7 ~ D7 float to high-impedance when the chip is deselected (CEn
high) or when the outputs are disabled.
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5 Pad Location
P14 P17
RS0
WEN
VDD VDD VDD
RS2
RS1
P16
P15
P10
P07
P11
P13
P06
P05
P04
NC
NC
NC
NC
NC
P03
P02
P01
P00
OEN
P12
D0
CEN
VSS
D1
January 16, 2004
D2
VSS
VSS D3
Page 5 of 19
D4
D5
D6
D7
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HF88M08
Die Size: X= 2870 µm, Y=4840 µm, and substrate is connected to GND.
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pad Name
WEN
RS0
P17
P14
P07
P06
P05
P04
NC
NC
NC
NC
NC
P03
P02
P01
P00
D0
D1
D2
VSS
X Coord. Y Coord.
1028.23
4726.24
836.35
4726.24
495.57
4722.3
308.13
4722.3
108.33
4097.34
108.33
3743.44
108.33
3262.4
108.33
3071.78
108.33
2786.78
108.33
2598.09
108.33
2315.6
108.33
2127.68
108.33
1843.32
108.33
1656.15
108.33
1357.04
108.33
1169.6
108.33
758.2
108.33
403.24
395.97
109.14
583.13
109.14
985.16
190.94
Pad No.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Pad Name
VSS
VSS
D3
D4
D5
D6
D7
CEN
P12
OEN
P13
P11
P10
P15
P16
RS1
RS2
VDD
VDD
VDD
X Coord. Y Coord.
1222.34
140.91
1501.38
108.09
1664.02
109.14
1851.18
109.14
2038.62
109.14
2225.78
109.14
2725.87
105.79
2725.87
340.24
2725.87
537.52
2725.87
730.47
2728.88
3911.29
2728.88
4116.11
2728.88
4318.77
2728.87
4531.23
2728.87
4725.13
2107.66
4736
1908.12
4736
1578.76
4688.71
1404.34
4688.71
1229.92
4688.71
6 Device Operation
The device provides the capability of accessing the contents of ROM array by external MCU not through
standard address and data bus configuration but through minimal number of 8-bit data bus and control
pins. Only 11 pins D7 ~ D0, CEn, OEn, WEn are required to use the device as a Data File device. By
fixing the RS2 to ‘0’, only CEn, WEn, OEn and D0 ~ D7 are required to access the ROM array data.
The CEn pin is device selection pin to uniquely select one device when more than one device are used in
parallel and control the access to Mask ROM contents and internal registers. Whenever CEn goes high,
the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are
inhibited. Otherwise, it is in active mode. Therefore, when accessing contents of ROM is not intended,
CEn should stay at ‘1’ to conserve the power.
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In addition to Data File mode, the device also provides the expansion I/O capability. Two ports of I/O
pins (8 bit each) are provided. The I/O ports can be configured to function as output pin or
high-impedance input pins. Only 14 pins, CEn, WEn, OEn, RS2, RS1 and D0 ~ D7 are required to
provide the Data File function and full access to two I/O ports.
There are seven internal registers used to provide the functionality of Data file as well as Expansion I/O
capability. These registers are selected by RS2 ~ RS0. All registers are 8-bit wide except AC2. AC2
~ AC0 are write-only and constitute the complete 20-bit Address Counter used as pointer to the data.
While the P0, P1, DIR0 and DIR1 can be read as well as written. Their initial values are as indicated in
the following table. When RS2 = ‘0’, the RS1 ~ RS0 are ignored, the Address Counter can be loaded or
contents of Data File can be read. This is to reduce the required pin needed for external MCU to
interface with the Device and also simplify the procedure for loading the address counter.
The P0, P1, DIR0, and DIR1 are used for expansion I/O registers. The P0 and P1 are output registers of
Expansion I/O and DIR0 and DIR1 are the Direction Registers that determine the I/O mode of P0 and P1.
Each pin can be configured as output or input mode individually by setting or resetting the corresponding
pin of the DIR registers. Initially, both P0 and P1 are default to input mode at ‘Hi’ state.
D0
DIR00
DIR00
Q
DIR10
D
D
RS = 100 & OEn = '0'
RS = 110 & OEn = '0'
P10
P00
P00
Q
Q
D
D
Q
1
1
0
P10
RS = 101 & OEn = '0'
RS = 111 & OEn = '0'
0
The accesses to the internal registers will be inhibited when CEn is ‘1’. However, the status of internal
registers, such as expansion I/O ports, will not be affected. For example, if a certain pin is in output
mode and driving ‘Hi’, it will not change when CEn pin goes to ‘1’ state. Therefore, the users are
advised to take care of the power down condition of I/O ports when entering sleep mode to prevent
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unnecessary power drain.
RS2RS1RS0 Symbol
0xx
AC2
AC1
AC0
100
P0
101
DIR0
110
P1
111
DIR1
Type
R
W
W
W
R/W
R/W
R/W
R/W
Description
Read data by Indirect access
Address latch 2 for A19 ~ A16
Address latch 1 for A15 ~ A8
Address latch 0 for A7 ~ A0
Port 0 Output Register
Direction Register 0
Port 1 Output Register
Direction Register 0
Initial Value
“--------“
“--------“
“--------“
“11111111“
“00000000“
“11111111“
“00000000“
6.1 Retrieve data in Data File
Accesses to the ROM contents, expansion I/O, Address Counter and Direction registers are made through
8 Data I/O pins – D7 ~ D0. With Register Selection RS = “0xx”, the starting addresses can be written
through Data I/Os by bringing WEn to low and back to high. Addresses are latched on the rising edge of
WEn.
Once the starting address of data block is latched into the Address Counter, data may be read out by
sequentially pulsing OEn with CEn staying low. When at ‘0’, the OEn gate the data of the selected
address unto Data I/O pin D7 ~ D0. With the rising edge of OEn, the internal Address Counter is
incremented by one automatically.
6.2 Loading the Address Counter
Before the data can be retrieved, the Address Counter must be initialized with the starting address, then
the contents of ROM pointed to by Address Counter (AC) can be accessed through D7 through D0. In
order to simplify the procedure of loading 20-bit Address Counter (AC), a internal pointer is implemented
and used to point to next register to write in the up to three-cycle address loading sequence. Initially,
with RS = “0xx” CEn goes from ‘1’ to ‘0’ and the AC pointer is initialized. The pointer is then
incremented to point to next register with falling edge of each WEn pulse. So when randomly accessing
data within a 256-byte page, or within a 64K-byte block mode, then only one or two-cycle address reload
process is needed to access different locations within a page or block.
The Address Counter pointer will be held in reset state in the following conditions:
1. When CEn is '1' (the device is deselected).
2. By the Read pulse (OEn is '0') and RS2 = '0' (ROM is being accesses).
The inclusion of the 3rd condition is to force the address loading to start from LSB of Address Counter
once the read cycle is initiated. However, the AC Pointer will not be reset when reading or writing
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from/to expansion I/O registers (P0, P1, DIR0, DIR1). This design is useful in certain application
scenarios where in the midst of the multi-byte address loading process, an interrupt to the MCU main
loop occurs. And in the interrupt service routine, manipulation of expansion I/O registers is performed,
i.e., key board is scanned using P0 and P1. When the execution of program returns to main loop after
interrupt service routine completed, the loading of address can still resume from where it was interrupted.
6.3 Sequential Read Mode and Auto Increment of Address Counter
With each read access to the ROM data (RS = “0xx”), the Address Counter is incremented automatically
by one with rising edge of OEn to facility sequential access to a block of ROM data and avoid repeated
loading of addresses.
6.4 Output data to External I/O
The device’s 16-bit Expansion I/O capability provides additional I/O ports for applications where the I/O
pin are heavily used. To use as a certain pin as output pin, the corresponding bit in Direction Register
must be set to ‘1’. Please refer to the following example where output 0x00 to P0 to ‘0’ is intended.
1.
2.
3.
4.
5.
6.
Set RS to “101” (DIR0).
Keep D7 ~ D0 at 0xff (all bits in output mode).
Pulse the WEn to low then high to write to write contents of D-bus to DIR0.
Set RS to “100” (P0 Output Register).
Set D7 ~ D0 to 0x00.
Pulse the WEn to low then high to write contents of D-bus to P0 and drive all bits in P0 to low.
6.5 Reading Input pin status
To use expansion I/O ports as input pins and read the status from them, the corresponding bit in direction
register must be set to ‘0’. Please see the following example where reading inputs from of P1 is
intended.
1.
2.
3.
4.
5.
6.
Set RS to “111” (DIR1).
Set D7 ~ D0 to 0x00.
Pulse the WEn to low then high to set DIR1 to all High-Impedance input mode.
Set RS to “110” (P1 Output Register).
Pulse the OEn to low.
Read P1 then set the OEn back to high.
There is one thing should be noted. For any unused (open) expansion I/O pin, it is advisable to set the
port to output mode either at ‘0’ or ‘1’ state to prevent it from floating or fix it at VDD or VSS if it is set
to input mode. Otherwise, the noise might cause the unnecessary power consumption.
6.6 Retrieving the Contents of Expansion I/O registers
The contents of all four registers can be read through data bus.
January 16, 2004
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The ability to access the contents of
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registers avoids the necessity of using the RAM as mirror to keep the current status of latches in
applications. However, extra care should be taken when reading P0 and P1. To read the contents of P0
and P1, the DIR0 and DIR1 should be set to output mode. Otherwise, the pin status instead of P0 and P1
will be read. The same precaution should be applied in Read-Modify-Write sequence that read back the
contents of the output latch of output mode pins and input status of input mode pins.
7 Timing Diagrams
Symbol
TCE
TWEL
TWEH
TDHeld
TOLZ
TACE
TOEL
TOEH
TCEHeld
TACER
TORL
TORH
TRCEL
TRCEH
January 16, 2004
Parameter
Chip selected to active width
WEn active low width
WEn inactive low width
Written data hold time
Read-Write mode transient time
ROM data file available time
Output enable low duty for access ROM
Output enable low duty for access ROM
Chip selection signal holding time
Register data available time
Output enable low duty for access register
Output enable low duty for access register
RS signal setup time
RS signal hold time
Page 10 of 19
Min.
0
100
100
50
200
50
250
150
50
30
100
100
50
50
Typ.
50
-
Max.
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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7.1 Data File Read Cycle
tCEHeld
tCE
tWEL
tWEH
CEn
tOLZ
tOEL
tOEH
WEn
OEn
tDHeld
D[7:0]
Internal
Memory
Address
Internal
Memory
Data
tACE
AC0
AC1
AC2
34
56
07
xxxx34
xx5634
ZZ
ZZ
3C
ZZ
075635
075634
1E
tRCEL
RS[2:0]
1E
ZZ
3C
78
075636
ZZ
78
ZZ
075637
ZZ
tRCEH
RS2=0, RS1 and RS0 can be any value.
Data File Read Cycle
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7.2 Interrupted by I/O when Loading Address Counter
CEn
WEn
tORL
tORH
tACER
OEn
AC0
D[7:0]
AC1
3Dh
00h
Internal
Memory
Address
RS[2:0]
P0_Data
P0_DIR
P1_Data
P1_DIR
ZZ
00h
55h
ZZ
BBh
78h
xxxx3Dh
000b
101b
111b
AC2
00h
xx783Dh
100b
110b
00783Dh
000b
FFh
FFh
00h
FFh
FFh
00h
Interrupted by I/O when Loading Address Counter
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7.3 Setting and Reading the I/O Mode for P0 and P1
CEn
W En
tO R L
tA C E R
OEn
D [ 7 :0 ]
R S [ 2 :0 ]
F0h
000b
0Fh
101b
P 0 _ D a ta
FFh
P 1 _ D a ta
FFh
P 0 _ D IR
P 1 _ D IR
tO R H
00h
111b
F0h
101b
ZZ
0Fh
ZZ
111b
F0h
00h
0Fh
S e t t in g a n d R e a d in g t h e I /O M o d e f o r P 0 a n d P 1
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7.4 Reading P0 and P1 in Mixed-I/O Mode
CEn
W En
tO R L
tA C E R
OEn
F0h
D [7 :0 ]
R S [2 :0 ]
000b
0Fh
101b
P 0 _ D a ta
FFh
P 1 _ D a ta
FFh
P 0 _ D IR
P 1 _ D IR
tO R H
111b
F5h
ZZ
100b
AFh
ZZ
110b
F0h
00h
00h
0Fh
R e a d in g P 0 a n d P 1 in M ix e d -I /O M o d e
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7.5 Reading the input pins
CEn
W En
OEn
D [7 :0 ]
R S [2 :0 ]
00h
000b
101b
P 0 _ D a ta
FFh
P 1 _ D a ta
FFh
P 0 _ D IR
P 1 _ D IR
00h
111b
55h
100b
ZZ
AAh
ZZ
110b
00h
F0h
0Fh
00h
R e a d in g th e In p u t P in s
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7.6 Output to P0 and P1 Ports
CEn
W En
OEn
FFh
D [7 :0 ]
R S [ 2 :0 ]
000b
FFh
101b
111b
100b
AAh
ZZ
110b
55h
P 1 _ D a ta
P 1 _ D IR
ZZ
FFh
P 0 _ D a ta
P 0 _ D IR
55h
FFh
AAh
FFh
00h
00h
FFh
O u tp u t to P 0 a n d P 1 P o r ts
8 Absolute Maximum Rating
Items
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
VDD
VIN
TOPR
TSTR
Rating
-0.3 to 6 V
-0.3 to Vdd+0.3 V
-0 to 70 °C
-55 to 125 °C
Condition
9 AC Electrical Characteristics
READ CYCLE
There are two ways of accessing the ROM data. The first one is to assert the valid address on the
Address Bus, then assert CEn “low” to enable the ROM array. The access time in this mode is specified
as tACE. The advantage of this access mode is that power consumption can be lowered. The second
access mode keeps the CEn “low” while changes the addresses to access the contents of ROM data. The
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access time in this way is specified as tAA. In this device, the Address Access Time decrease
monotonically with increasing voltage, and it is shorter than Chip Enable Access Time when the
Operation Voltage is higher then 4.5 V. Therefore in Vop higher than 4.5 Volts, it is more advisable to
use the Address Access Mode to achieve faster access to ROM data when the power consumption is not a
concern.
Item
Symbol 2.4V 3.0V 3.3V 3.6V 4.5V 5.0V 5.5V
Chip Enable Access Time
tACE
240 210 190 180 210 250
Address Access Time
tAA
480 230 200 180 150 140 130
Unit
ns
ns
Remark
Min
Min
10 DC Electrical Characteristics
(VSS = 0V, VDD = 5.0 V, TOPR = 25°C unless otherwise noted)
Parameter
Supply Voltage
Operating Current
Standby Current
Input voltage
Input current leakage
P0, P1 Output High
Voltage
P0, P1 Output Low
Voltage
D Output High Voltage
D Output Low Voltage
Symbol
VDD
IDD
IDD
VIH
VIL
IIL
VOH
Min.
2.4
2/3
0
2.4
Typical
10
10
-
Max.
5.5
1
1/3
+/- 10
-
Unit
V
mA
µA
VDD
Condition
No load
No load
VDD = 4V ~ 6V
µA
V
IOH = 0.4 mA
VOL
-
-
0.4
V
IOL = 2.1 mA
VOH
VOL
2.4
-
-
0.4
V
V
IOH = 14 mA
IOL = 3 mA
11 Application Circuit Diagram
This application circuit illustrates that how KB83760 MCU uses two external HF88M08s for ROM
expansion as well as keyboard scan functions.
January 16, 2004
Page 17 of 19
V1.11
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
HF88M08
司
D7
2
K27
K34
K5
K12
K19
K26
K33
K4
K11
K18
K25
K32
K3
K10
K17
K24
K31
M9
M10
K20
M8
K13
M7
K6
M5
M4
2
D5
3
1N4148
Dial
HOLD
HF
2
#
D0
1
9
5
6
7
8
9
2
11
12
13
D3
Redial
1N4148
Flash
2
Pause
1
Name
D4
6
D2
D1
DOWN
2
1N4148
UP
1
Erase
D6
D5
D4
D3
Auto
D6
D5
D4
D3
VSS
D2
D1
RS1
RS2
VDD
WE
RS0
P17
P14
K35
M1
P16
P15
P10
P11
P13
OE
P12
CE
D7
WEn
RS0
K28
M3
1
1N4148
20
19
18
17
16
15
14
K21
M2
U3
P07
P06
P05
P04
P03
P02
P01
P00
D0
VDD
30
31
32
1
2
3
4
K14
D6
HF88M08-PLCC32
RS1
RS2
K7
M6
1N4148
29
28
27
26
25
24
23
22
21
OEn
CE2n
D7
1
K16
K23
K30
D2
8
0
Mute
*
PGM
R4
R5
5
2
K29
7
D6
D5
D4
D3
1
K8
R5
D2
D1
R4
330K
P07
P06
P05
P04
P03
P02
P01
P00
D0
R5
K22
2
1N4148
C7
C6
C5
C4
C3
C2
C1
WEn
RS0
20
19
18
17
16
15
14
R3
29
28
27
26
25
24
23
22
21
1
K1
D6
D5
D4
D3
VSS
D2
D1
RS1
RS2
VDD
WE
RS0
P17
P14
K15
D1
P16
P15
P10
P11
P13
OE
P12
CE
D7
VDD
30
31
32
1
2
3
4
K9
4
K2
U2
HF88M08-PLCC32
RS1
RS2
2
1N4148
R2
R1
R2
R4
OEn
R3
CE1n
D7
1
5
6
7
8
9
2
11
12
13
R3
330K
C7
C6
C5
C4
C3
C2
C1
D0
R2
330K
R1
330K
330K
R1
VDD
C6
1uF
VDD
SXI
SXO
TSTP
FXI
FXO
RSTP
OPO
OPIP
OPIN
DAO
D0
D1
D2
D3
D4
D5
D6
D7
KTONE
SDO
DTMFO
MUTE
1uF
C4
U1
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
PRT110
PRT111
PRT112
PRT113
PRT114
PRT115
PRT116
PRT117
PRT100
PRT101
PRT102
PRT103
PRT104
PRT105
PRT106
PRT107
RS0
RS1
RS2
OEn
WEn
CE1n
CE2n
C5
1uF
PRT110
PRT111
PRT112
PRT113
PRT114
PRT115
PRT116
PRT117
PRT100
PRT101
PRT102
PRT103
PRT104
PRT105
PRT106
PRT107
PRTC0
PRTC1
PRTC2
PRTC3
PRTC4
PRTC5
PRTC6
PRTC7
PRTD0
PRTD1
PRTD2
PRTD3
PRTD4
PRTD5
PRTD6
PRTD7
KEYTONE
SDO
DTMFO
MUTE
VDD
SXI
SXO
TSTP
FXI
FXO
RSTP
OPO
OPIP
OPIN
DAO
KB83760
PWMP
PWMN
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
1uF
VO
GND
LVG
LR0
LR1
LR2
LR3
LR4
LV3
LV2
LV1
LC2
LC1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
VO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C2
1uF
C1
1uF
C10
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
1uF
VDD
C7
C8
C9
1uF 1uF 1uF
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SET49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
PWMP
PWMN
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
C3
January 16, 2004
Page 18 of 19
V1.11
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
HF88M08
12 Updated History
Version
1.10
1.11
Date
2003/8/27
2004/1/16
January 16, 2004
Update Description
Timing diagrams modified.
Add the die size
Page 19 of 19
V1.11
This specification is subject to change without notice. Please contact sales person for the latest version before use.