KB SF23C3200B

King Billion Electronics Co., Ltd SF23C3200B
駿
億
電
子
股
份
有
限
公
司
- Table of Contents 1.
General Description_______________________________________________________________2
2.
Features ________________________________________________________________________2
3.
Functional block diagram __________________________________________________________2
4.
Pin Description __________________________________________________________________3
5.
Pad Location ____________________________________________________________________5
6.
Absolute Maximum Rating _________________________________________________________6
7.
AC Electrical Characteristics _______________________________________________________6
8.
DC Electrical Characteristics _______________________________________________________7
December 8, 2003
Page 1 of 7
V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd SF23C3200B
駿
億
電
子
股
份
有
限
公
司
1. General Description
The SF23C3200B is a fully static, 32 Mbit CMOS Mask Programmable ROM. This device operates in
wide operating range. It requires no external clock for its operation and suitable for use with
microprocessor program memory, and data memory (speech, graphic, etc).
2. Features
9 Operating range: 2.4V ~ 3.6V
9 Organization
- Memory Cell Array: 4M x 8 or 2M x 16 selectable by BYTEB pin
9 Low Operation Current (Typical)
10 µA standby mode current.
30 mA active read current at 100 ns cycle time.
9 Fully static operation
9 Tri-state outputs
9 Package: bare chip
-
3. Functional block diagram
X BUFFER &
DECODER
[A20..A-1]
CEn
OEn
Y BUFFER &
DECODER
CONTROL
LOGIC
MEMORY
CELL
ARRAY
SENSE AMP.
BYTEB
[Q15..Q0]
December 8, 2003
Page 2 of 7
V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd SF23C3200B
駿
億
電
子
股
份
有
限
公
司
4. Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BY TE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
SF23C3200
Symbol
A18, A17
A7 ~ A0
CEn
Pin No.
1, 2
3 ~ 10
11
GND
OEn
12
13
Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7,
Q8,
Q9,
Q10,
Q11,
Q12,
Q13,
Q14,
Q15A-1,
14,
16,
18,
20,
23,
25,
27,
29
15,
17,
19,
21,
24,
26,
28,
30
VCC
22
December 8, 2003
I/O
Description
I Mask ROM Address input pins.
I Mask ROM Address input pins.
I The CEn (Chip Enable) input is the device selection and power control for
internal Mask ROM array. Whenever CEn goes high, the internal Mask
ROM will enter standby (power saving) mode. Otherwise, it is in active
mode and the contents of the ROM can be accessed.
P Negative power supply input pin.
I OEn (Output Enable) is the output control which gates ROM array data onto
the data output pins Q7 ~ Q0 in Byte mode (BYTEB pin is at “low” state) or
Q15A-1, Q14 ~ Q0 in Word mode (BYTEB pin is at “high” state).
O, Mask ROM array Data lower byte outputs drive Q7 ~ Q0 pins during read
O, operations (CEn and OEn are “low”). The Q7 ~ Q0 pins stay in high-Z when
O, the chip is deselected (CEn high) or when the outputs are disabled (OEn
O, high).
O,
O,
O,
O,
O, Mask ROM data higher byte output pins when Word mode is selected
O, (BYTEB is at “high” level) during read operations (CEn and OEn are
O, “low”). They will be tri-stated when Byte mode is selected (BYTEB at
O, “low” level), the chip is deselected (CEn high), the outputs are disabled
O, (OEn high).
O,
O,
O/I, Q15A-1 is Mask ROM MSB Data output pin in Word mode and LSB
address pin in Byte mode.
P Positive power supply input pin.
Page 3 of 7
V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd SF23C3200B
駿
GND
BYTEB
A16 ~ A8
A19, A20
31
32
P
I
33 ~ 41
42, 43
I
I
December 8, 2003
億
電
子
股
份
有
限
公
司
Negative power supply input pin.
Byte/Word mode selection input pin. Byte mode is selected when it is at
“low” state, otherwise Word mode is selected.
Mask ROM Address input pins.
Mask ROM Address input pins.
Page 4 of 7
V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd SF23C3200B
駿
億
電
子
股
份
有
限
公
司
5. Pad Location
December 8, 2003
Page 5 of 7
V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd SF23C3200B
駿
Pad No. Pad Name
1 NC
2 BYTEB
3 A16
4 A15
5 A14
6 A13
7 A12
8 A11
9 A10
10 A9
11 A8
12 A19
13 GND
14 NC
15 GND
16 NC
17 GND
18 A20
19 A18
20 A17
21 A7
22 A6
23 A5
24 A4
25 A3
26 A2
27 A1
28 A0
29 CEN
30 NC
億
電
子
股
份
X Coord. Y Coord. Pad
-1941.5
3231.86
-1941.5
3008.86
-1941.5
2785.86
-1941.5
2562.86
-1941.5
2339.86
-1941.5
2116.86
-1941.5
1893.86
-1941.5
1670.86
-1941.5
1447.86
-1941.5
1224.86
-1941.5
1001.86
-1941.5
778.86
-1941.5
555.86
-1941.5
332.86
-1941.5
-34.78
-1941.5
-257.78
-1941.5
-480.78
-1941.5
-703.78
-1941.5
-926.78
-1941.5
-1149.78
-1941.5
-1372.78
-1941.5
-1595.78
-1941.5
-1818.78
-1941.5
-2041.78
-1941.5
-2264.78
-1941.5
-2487.78
-1941.5
-2710.78
-1941.5
-2931.48
-1941.5
-3152.18
-1941.5
-3372.88
有
限
公
司
No.
Pad Name
31 GND
32 GND
33 GND
34 OEN
35 D0
36 D8
37 D1
38 D9
39 D2
40 D10
41 D3
42 D11
43 VDD
44 GND
45 VDD
46 GND
47 VDD
48 GND
49 D4
50 D12
51 D5
52 D13
53 D6
54 D14
55 D7
56 D15A_1
57 GND
58 GND
59 GND
X Coord. Y Coord.
1941.5
-3262.78
1941.5
-3039.78
1941.5
-2816.78
1941.5
-2593.78
1941.5
-2370.78
1941.5
-2140.78
1941.5
-1917.78
1941.5
-1687.78
1941.5
-1464.78
1941.5
-1234.78
1941.5
-1011.78
1941.5
-781.78
1941.5
-558.78
1941.5
-335.78
1941.5
-112.78
1941.5
110.22
1941.5
333.22
1941.5
712.16
1941.5
935.16
1941.5
1165.16
1941.5
1388.16
1941.5
1618.16
1941.5
1841.16
1941.5
2071.16
1941.5
2294.16
1941.5
2517.16
1941.5
2740.16
1941.5
2963.16
1941.5
3186.16
6. Absolute Maximum Rating
Items
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
VCC
VIN
TOPR
TSTR
Rating
2.4 to 3.6 V
-0.3 to Vdd+0.3 V
-0 to 70 °C
-55 to 125 °C
7. AC Electrical Characteristics
READ CYCLE:
December 8, 2003
Page 6 of 7
V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd SF23C3200B
駿
億
電
子
股
份
有
限
公
司
There are two ways of accessing the ROM data. The first one is to assert the valid address on the Address
Bus, then assert CEn “low” to enable the ROM array. The access time in this mode is specified as tACE.
The advantage of this access mode is that power consumption can be lowered. The second access mode
keeps the CEn “low” while changes the addresses to access the contents of ROM data. The access time in
this way is specified as tAA.
Item
Symbol
tRC
Read Cycle Time
Chip Enable Access Time
tACE
Address Access Time
tAA
Output Enable Time
Output or Chip Disable to Output High-Z
Output Hold from Address Change
tOE
tDF
tOH
Min
100
120
Max
100
120
100
120
50
20
0
Unit
Condition
ns VDD = 3.0 V, no load
VDD = 2.4V, no load
ns VDD = 3.0 V, no load
VDD = 2.4V, no load
ns VDD = 3.0 V, no load
VDD = 2.4V, no load
ns
ns
ns
8. DC Electrical Characteristics
(GND = 0V, VCC = 3.0 V, TOPR = 25°C unless otherwise noted)
Parameter
Supply Voltage
Operating Current
Standby Current
Input voltage
Input current leakage
P0, P1 Output High Voltage
P0, P1 Output Low Voltage
D Output High Voltage
D Output Low Voltage
December 8, 2003
Symbol
Min.
Typical
Max.
Unit
VCC
ICC
ISTBY
VIH
VIL
IIL
VOH
VOL
VOH
VOL
2.4
2/3
0
2.4
2.4
-
30
10
-
3.6
1
1/3
± 10
0.4
0.4
V
mA
µA
No load, tRC@ 100 ns
No load
VDD
VDD = 2.4V ~ 3.6V
µA
V
V
V
V
IOH = 0.4 mA
IOL = 2.1 mA
IOH = 1.4 mA
IOL = 3 mA
Page 7 of 7
Condition
V1.1
This specification is subject to change without notice. Please contact sales person for the latest version before use.