HYS64D64020GDL DDR-SDRAM SO-DIMM Modules 2.5 V 200-pin DDR Small Outline SDRAM Modules 512MB Modules PC1600, PC2100 & PC2700 Preliminary Datasheet Rev. 0.9 • All inputs and outputs SSTL_2 compatible • 200-pin Unbuffered 8-Byte Dual-In-Line DDR-I SDRAM non-parity Small Outline Modules • Serial Presence Detect with E2PROM • Two bank 64Mx64 organization • Jedec standard form factor: 67.60 mm × 31.75 mm × 3.00 / 3.80 mm • JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) • Jedec standard reference layout Raw Card A • Gold plated contacts • Single + 2.5 V (± 0.2 V) power supply • Built with 512 Mbit DDR-I SDRAMs organised as x 16 in 66-Lead TSOPII packages • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh Performance: -6 -7 -8 Unit Component Speed Grade DDR333 DDR266A DDR200 Module Speed Grade PC2700 PC2100 PC1600 fCK Clock Frequency (max.) @ CL = 2.5 166 143 125 MHz fCK Clock Frequency (max.) @ CL = 2 133 133 100 MHz The HYS64Dxx0x0GDL are industry standard 200-pin 8-byte Small Outline Dual in-line Memory Modules (DIMMs) organized as 64M x 64. The memory array is designed with Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. INFINEON Technologies 1 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Ordering Information Type Compliance Code Description SDRAM Technology PC2700-25330-A two banks 512 MB SO-DIMM 512 MBit (x16) PC2100-20330-A two banks 512 MB SO-DIMM 512 MBit (x16) PC1600-20220-A two banks 512 MB SO-DIMM 512 MBit (x16) PC2700 (CL=2.5): HYS64D64020GDL-6-A PC2100 (CL=2): HYS64D64020GDL-7-A PC1600 (CL=2): HYS64D64020GDL-8-A Note: All part numbers end with a place code, designating the silicon-die revision. Reference information available on request. Example: HYS 64D32020GDL-8-A, indicating Rev.A die are used for DDR-SDRAM components. The Compliance Code which is printed on the module labels describes the speed sort class (“f.e. PC2100”), the latencies (f.e. 20330 means CAS latency = 2, trcd latency = 3 and trp latency = 3) and the Raw Card used for this module INFINEON Technologies 2 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Pin Definitions and Functions A0 - A12 Address Inputs CS0, CS1 *) Chip Selects BA0, BA1 Bank Selects VDD Power (+ 2.5 V) DQ0 - DQ63 Data Input/Output VSS Ground RAS Row Address Strobe VDDQ I/O Driver power supply CAS Column Address Strobe VDDID VDD Indentification flag WE Read/Write Input VREF I/O reference supply CKE0 - CKE1 Clock Enable VDDSPD Serial EEPROM power supply DQS0 - DQS8 SDRAM low data strobes SCL Serial bus clock CLK0 - CLK1, SDRAM clock (positive lines) SDA Serial bus data line CLK0 - CLK1 SDRAM clock (negative lines) SA0 - SA2 slave address select DM0 - DM8 data masks NC no connect DQS0 - DQS8 data strobes DU Dont use, reserved for future use *) CKE1 and CS1 are used on two bank modules only Address Format Density Organization Memory SDRAMs Banks # of SDRAM SDRAMs density # of row/ Refresh bank/ columns bits Period Interval 512 MB 64M × 64 2 8 13/2/10 64 ms 7.8 µs INFINEON Technologies 32M x 16 512Mbit 3 8k 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Pin Configuration Pin # Front Side 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 Pin # Back Side 2 VREF 4 VSS 6 DQ4 8 DQ5 10 VDD 12 DM0 14 DQ6 16 VSS 18 DQ7 20 DQ12 22 VDD 24 DQ13 26 DM1 28 VSS 30 DQ14 32 DQ15 34 VDD 36 VDD 38 VSS 40 VSS 42 DQ20 44 DQ21 46 VDD 48 DM2 50 DQ22 Pin # Front Side Pin# 51 VSS 52 53 DQ19 54 55 DQ24 56 57 VDD 58 59 DQ25 60 61 DQS3 62 63 VSS 64 65 DQ26 66 67 DQ27 68 69 VDD 70 71 (CB0) 72 73 (CB1) 74 75 VSS 76 77 (DQS8) 78 79 (CB2) 80 81 VDD 82 83 (CB3) 84 85 DU 86 87 VSS 88 89 (CK2) 90 91 (CK2) 92 93 VDD 94 95 CKE1 96 97 DU 98 99 A12 100 Back Side Pin # VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD (CB4) (CB5) VSS (DM8) (CB6) VDD (CB7) DU VSS VSS VDD VDD CKE0 DU A11 Front Side Pin # Back Side 101 A9 102 A8 103 VSS 104 VSS 105 A7 106 A6 107 A5 108 A4 109 A3 110 A2 111 A1 112 A0 113 VDD 114 VDD 115 A10/AP 116 BA1 117 BA0 118 RAS 119 WE 120 CAS 121 CS0 122 CS1 123 DU 124 DU 125 VSS 126 VSS 127 DQ32 128 DQ36 129 DQ33 130 DQ37 131 VDD 132 VDD 133 DQS4 134 DM4 135 DQ34 136 DQ38 137 VSS 138 VSS 139 DQ35 130 DQ39 141 DQ40 142 DQ44 143 VDD 144 VDD 145 DQ41 146 DQ45 147 DQS5 148 DM5 149 VSS 150 VSS Pin # Front Side Pin # 151 DQ42 152 153 DQ43 154 155 VDD 156 157 VDD 158 159 VSS 160 161 VSS 162 163 DQ48 164 165 DQ49 166 167 VDD 168 169 DQS6 170 171 DQ50 172 173 VSS 174 175 DQ51 176 177 DQ56 178 179 VDD 180 181 DQ57 182 183 DQS7 184 185 VSS 186 187 DQ58 188 189 DQ59 190 191 VDD 192 193 SDA 194 195 SCL 196 197 Vddspd 198 199 Vddid 200 Back Side DQ46 DQ47 VDD CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU pin 199 pin 39 pin 41 pin 40 pin 42 front side pin 200 pin 1 pin 2 Note: Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 89 and 91 are reserved for x72 variants of this module and are not used on the x64 . versions. Pin 86 is reserved for a registered variant of this module and is not used on the unbuffered version back side INFINEON Technologies 4 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules CS1 CS0 CS DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDM LDQS LDM I/O 0 I/O 0 I/O 1 I/O 1 I/O 2 I/O 2 I/O 3 I/O 3 I/O 4 I/O 4 D0 I/O 5 I/O 5 I/O 6 DQS4 DM4 D4 I/O 7 I/O 7 UDQS UDM UDQS UDM I/O 8 I/O 8 I/O 9 I/O 9 I/O 10 I/O 10 I/O 11 I/O 11 I/O 12 I/O 12 I/O 13 I/O 13 I/O 14 I/O 14 I/O 15 I/O 15 CS LDQS LDQS LDM LDM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 D5 I/O 5 I/O 6 I/O 7 UDQS UDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS3 DM3 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 6 CS DQS2 DM2 CS CS LDQS D1 CS LDQS LDM LDQS LDM I/O 0 I/O 0 I/O 1 I/O 1 I/O 2 I/O 2 I/O 3 I/O 3 I/O 4 I/O 4 D2 I/O 5 I/O 6 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 7 UDQS UDM UDQS UDM I/O 8 I/O 8 I/O 9 I/O 9 I/O 10 I/O 10 I/O 11 I/O 11 I/O 12 I/O 12 I/O 13 I/O 13 I/O 14 I/O 14 I/O 15 I/O 15 CS LDQS LDQS LDM LDM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 D3 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS7 DM7 D6 I/O 6 CS DQS6 DM6 I/O 5 I/O 7 D7 Serial Presence Detect (SPD) SCL SA0 A0 SA1 A1 SA2 A2 SDA WP Unless otherwise noted, resistor values are 22 Ohm with +/- 5% tolerance BA0-BA1 SDRAMS D0-D7 A0-AN SDRAMS D0-D7 RAS SDRAMS D0-D7 CK0 4 loads CK 0 CAS SDRAMS D0-D7 CK1 WE SDRAMS D0-D7 CK 1 CKE0 SDRAMS D0-D3 CKE1 SDRAMS D4-D7 V DD SPD SPD V REF SDRAMS D0-D7 V DD SDRAMS D0-D7 V SS SDRAMS D0-D7, SPD 4 loads Note: DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. V DD ID strap connections: V DD and V DD Q Strap out (open): VDD = VDDQ V DD ID Block Diagram: Two Bank 64M x 64 DDR-SDRAM SO-DIMM Modules using x16 Organized SDRAMs on Raw Card Version A INFINEON Technologies 5 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Input / Output voltage relative to VSS VIN, VOUT – 0.5 3.6 V Power supply voltage on VDD /VDDQ to VSS VDD, VDDQ – 0.5 3.6 V Storage temperature range TSTG -55 +150 o Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA C Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability Supply Voltage Levels Parameter Symbol Limit Values Unit Notes min. nom. max. Device Supply Voltage VDD 2.3 2.5 2.7 V - Output Supply Voltage VDDQ 2.3 2.5 2.7 V 1) Input Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 2) Termination Voltage VTT VREF – 0.04 VREF VREF + 0.04 V 3) EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V 1 Under all conditions, VDDQ must be less than or equal to VDD 2 Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ . 3 VTT of the transmitting device must track VREF of the receiving device. DC Operating Conditions (SSTL_2 Inputs) (VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS) Parameter Symbol Limit Values Unit Notes VDDQ + 0.3 V 1) min. max. DC Input Logic High VIH (DC) VREF + 0.15 DC Input Logic Low VIL (DC) – 0.30 VREF – 0.15 V – Input Leakage Current IIL –5 5 µA 1) Output Leakage Current IOL –5 5 µA 2) 1) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). 2) For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component. INFINEON Technologies 6 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Operating, Standby and Refresh Currents (PC2700, PC2100, PC1600) 512MB x64 2bank -6 512MB x64 2bank -7 512MB x64 2bank -8 Unit Notes Symbol Parameter/Condition MAX MAX MAX IDD0 Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 1080 920 840 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. 1140 960 880 mA 1, 3 IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX; tCK = tCK MIN 144 112 96 mA 2 IDD2F Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. 480 400 320 mA 2 IDD2Q Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. 320 224 200 mA 2 IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM. 184 144 128 mA 2 IDD3N Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 600 560 400 mA 2 IDD4R Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA 1260 1040 860 mA 1, 3 IDD4W Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN 1220 1020 840 mA 1 1 4 IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 1620 1480 1360 mA IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN 20 20 20 mA IDD7 Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 1900 1760 1600 mA 1, 3 1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C INFINEON Technologies 7 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) Symbol DDR333 -6 Parameter DDR266A -7 DDR200 -8 Unit Notes + 0.8 ns 1-4 + 0.8 ns 1-4 0.45 0.55 tCK 1-4 0.45 0.55 tCK 1-4 Min Max Min Max Min Max DQ output access time from CK/CK - 0.7 + 0.7 − 0.75 + 0.75 − 0.8 DQS output access time from CK/CK - 0.6 + 0.6 − 0.75 + 0.75 − 0.8 tCH CK high-level width 0.45 0.55 0.45 0.55 tCL CK low-level width 0.45 0.55 0.45 0.55 tHP Clock Half Period tAC tDQSCK tCK CL = 2.5 min (tCL, tCH) min (tCL, tCH) min (t CL, tCH) ns 1-4 6 12 7 12 8 12 ns 1-4 7.5 12 7.5 12 10 12 Clock cycle time tCK ns 1-4 tDH DQ and DM input hold time CL = 2.0 0.45 0.5 0.6 ns 1-4 tDS DQ and DM input setup time 0.45 0.5 0.6 ns 1-4 tIPW Control and Addr. input pulse width (each input) 2.2 2.2 2.5 ns 1, 10 tDIPW DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1-4, 11 tHZ Data-out high-impedence time from CK/CK - 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 tLZ Data-out low-impedence time from CK/CK - 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 0.75 1.25 tCK 1-4 tDQSQ DQS-DQ skew (for DQS & associated DQ signals) + 0.6 ns 1-4 tQHS Data hold skew factor + 1.0 ns 1-4 tQH Data Output hold time from DQS tDQSL,H + 0.45 + 0.5 + 0.55 DQS input low (high) pulse width (write cycle) + 0.75 tHP-tQHS tHP-tQHS tHP-tQHS ns 1-4 0.35 0.35 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 0.2 tCK 1-4 tMRD Mode register set command cycle time 2 2 2 tCK 1-4 tWPRES Write preamble setup time 0 0 0 ns 1-4, 7 tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 0.25 tCK 1-4 0.75 0.9 1.1 ns tIS tIH Address and control input setup time Address and control input hold time fast slew rate 0.60 0.40 0.60 0.40 0.60 slow slew rate 0.8 1.0 1.1 ns fast slew rate 0.75 0.9 1.1 ns slow slew rate 0.8 1.0 1.1 2-4, 10,11 ns tRPRE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 42 70,000 45 120,000 50 120,000 ns 1-4 tRC Active to Active/Auto-refresh command period 60 65 70 ns 1-4 tRFC Auto-refresh to Active/Auto-refresh command period 72 75 80 ns 1-4 INFINEON Technologies 8 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) Symbol DDR333 -6 Parameter Min Max DDR266A -7 Min Max DDR200 -8 Min Unit Notes Max tRCD Active to Read or Write delay 18 20 20 ns 1-4 tRP Precharge command period 18 20 20 ns 1-4 tRRD Active bank A to Active bank B command 12 15 15 ns 1-4 tWR Write recovery time 15 15 15 ns 1-4 tDAL Auto precharge write recovery + precharge time tCK 1-4,9 (twr/tck) + (trp/tck) tWTR Internal write to read command delay 1 1 1 tCK 1-4 tXSNR Exit self-refresh to non-read command 75 75 80 ns 1-4 tXSRD Exit self-refresh to read command 200 tREFI Average Periodic Refresh Interval 200 7.8 512Mb based 200 7.8 7.8 tCK 1-4 µs 1-4, 8 1. Input slew rate >=1V/ns for DDR266 & DDR333 and = 1V/ns for DDR200. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10. These parameters guarantee device timing, but they are not necessarily tested on each device 11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac) INFINEON Technologies 9 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules SPD Codes for PC2700, PC2100 & PC1600 Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Description Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes 22 SDRAM Device Attributes: General 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-127 128-255 Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) Addr. and Command Setup Time Addr. and Command Hold Time Data Input Setup Time Data Input Hold Time Superset Information Minimum Core Cycle Time tRC Min. Auto Refresh Cmd Cycle Time tRFC Maximum Clock Cycle Time tck Max. DQS-DQ Skew tDQSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number – open for Customer use INFINEON Technologies 128 256 DDR-SDRAM 13 9 1/2 x64 0 SSTL_2.5 6ns / 7ns / 8ns 0.7ns / 0.75ns / 0.8ns non-ECC / ECC Self-Refresh,15.6ms x16 na 512MB x64 2bank -6 HEX 80 08 07 0D 0A 02 40 00 04 60 70 00 82 10 00 512MB x64 2bank -7 HEX 80 08 07 0D 0A 02 40 00 04 70 75 00 82 10 00 512MB x64 2bank -8 HEX 80 08 07 0D 0A 02 40 00 04 80 80 00 82 10 00 tccd = 1 CLK 01 01 01 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered Concurrent Auto Precharge, weak driver 7.5ns / 7.5ns / 10ns 0.7ns / 0.75ns / 0.8ns not supported not supported 18ns / 20ns / 20ns 12ns / 15ns / 15ns 18ns / 20ns / 20ns 42ns / 45ns / 50ns 64MByte 0.75ns / 0.9ns / 1.1ns 0.75ns / 0.9ns / 1.1ns 0.45ns / 0.5ns / 0.6ns 0.45ns / 0.5ns / 0.6ns – 60ns / 65ns / 70ns 72ns / 75ns / 80ns 12ns 0.45ns / 0.5ns / 0.6ns 0.55ns / 0.75ns / 1.0ns – Revision 0.0 – – – – – – – – – – 0E 04 0C 01 02 20 0E 04 0C 01 02 20 0E 04 0C 01 02 20 C1 C1 C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 2D 55 00 00 0A C1 INFINEON 75 75 00 00 50 3C 50 2D 40 90 90 50 50 00 41 4B 30 32 75 00 00 BC C1 INFINEON A0 80 00 00 50 3C 50 32 40 B0 B0 60 60 00 46 50 30 3C A0 00 00 B1 C1 INFINEON 10 2002-05-08 (rev. 0.9) HYS64D64020GDL DDR-SDRAM SO-DIMM Modules Package Outlines Raw Card A DDR-SDRAM SO-DIMM Modules Raw Card A 6 7 .6 ± 0.1 5 3 .8 m a x . 31.75 ± 0.13 6 3 .6 1 2 .1 5 39 1 1 .4 1 1 .5 5 2 .4 5 199 1± 0.1 2 .4 5 4 7 .4 4 .2 1 .0 40 2 .1 5 42 200 6 4 2 41 20 1 .8 4 0.25 0.2 -0.15 D e ta il o f C h a m fe r 2.55 D e ta il o f C o n ta cts 0 .4 5 0 .2 -0.1 5 0 .6 L-DIM-200-6 INFINEON Technologies 11 2002-05-08 (rev. 0.9)