HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules 256 MByte & 512 MByte Modules PC1600 & PC2100 • 184-pin Unbuffered 8-Byte Dual-In-Line DDR-I SDRAM non-parity and ECC-Modules for PC and Server main memory applications • Auto Refresh (CBR) and Self Refresh • One bank 32M × 64, 32M x 72 and two bank 64M x 64, 64M × 72 organization • Serial Presence Detect with E2PROM • All inputs and outputs SSTL_2 compatible • Jedec standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max. • JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) Single + 2.5 V (± 0.2 V) power supply • Jedec standard reference layout • Gold plated contacts • Built with 256 Mbit DDR-I SDRAMs organised as 32Mb x 8 in 66-Lead TSOPII package • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Performance: -7 -8 Unit Component Speed Grade DDR266A DDR200 Module Speed Grade PC2100 PC1600 fCK Clock Frequency (max.) @ CL = 2.5 143 125 MHz fCK Clock Frequency (max.) @ CL = 2 133 100 MHz The HYS64/72D32000GU and HYS64/72D64020GU are industry standard 184-pin 8-byte Dual inline Memory Modules (DIMMs) organized as 32M × 64 and 64M × 64 for non-parity and 32M x 72 and 64M x 72 for ECC main memory applications. The memory array is designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E 2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. INFINEON Technologies 1 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Ordering Information Type Compliance Code Description SDRAM Technology HYS64D32000GU-7-A PC2100-20330-B1 one bank 256 MB DIMM 256 MBit HYS64D32000GU-7-B PC2100-20330-A1 one bank 256 MB DIMM 256 MBit HYS72D32000GU-7-A PC2100-20330-B1 one bank 256 MB ECC-DIMM 256 Mbit HYS72D32000GU-7-B PC2100-20330-A1 one bank 256 MB ECC-DIMM 256 Mbit HYS64D64020GU-7-A HYS64D64020GU-7-B PC2100-20330-B1 two banks 512 MB DIMM 256 MBit HYS72D64020GU-7-A HYS72D64020GU-7-B PC2100-20330-B1 two banks 512 MB ECC-DIMM 256 MBit HYS64D32000GU-8-A PC1600-20220-B1 one bank 256 MB DIMM 256 MBit HYS64D32000GU-8-B PC1600-20220-A1 one bank 256 MB DIMM 256 MBit HYS72D32000GU-8-A PC1600-20220-B1 one bank 256 MB ECC-DIMM 256 Mbit HYS72D32000GU-8-B PC1600-20220-A1 one bank 256 MB ECC-DIMM 256 Mbit HYS64D64020GU-8-A HYS64D64020GU-8-B PC1600-20220-B1 two banks 512 MB DIMM 256 MBit HYS72D64020GU-8-A HYS72D64020GU-8-B PC1600-20220-B1 two banks 512 MB ECC-DIMM 256 MBit PC2100 (CL=2): PC1600 (CL=2): Note: All part numbers end with a place code, designating the silicon-die revision. Reference information available on request. Example: HYS 72D32000GU-8-A, indicating Rev.A dies are used for the SDRAM components. The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100”, the latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card used for this module. INFINEON Technologies 2 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Pin Definitions and Functions A0 - A12 Address Inputs S0, S1 Chip Selects BA0, BA1 Bank Selects VDD Power (+ 2.5 V) DQ0 - DQ63 Data Input/Output VSS Ground CB0 - CB7 Check Bits (x72 organization only) VDDQ I/O Driver power supply RAS Row Address Strobe VDDID VDD Indentification flag CAS Column Address Strobe VREF I/O reference supply WE Read/Write Input VDDSPD Serial EEPROM power supply CKE0 - CKE1 Clock Enable SCL Serial bus clock DQS0 - DQS8 SDRAM low data strobes SDA Serial bus data line CLK0 - CLK2, SDRAM clock (positive lines) SA0 - SA2 slave address select CLK0 - CLK2 SDRAM clock (negative lines) NC no connect DM0 - DM8 DQS9 - DQS17 SDRAM low data mask/ high data strobes note: S1 and CKE1 are used on two bank modules only Address Format Density Organization Memory Banks SDRAMs # of SDRAMs # of row/bank/ columns bits Refresh Period Interval 256 MB 32M x 64 1 32M x 8 8 13/2/10 8k 64 ms 7.8 µs 256 MB 32M x 72 1 32M x 8 9 13/2/10 8k 64 ms 7.8 µs 512 MB 64M × 64 2 32M x 8 16 13/2/10 8k 64 ms 7.8 µs 512 MB 64M × 72 2 32M x 8 18 13/2/10 8k 64 ms 7.8 µs INFINEON Technologies 3 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Pin Configuration PIN# Frontside Symbol PIN# Frontside Symbol PIN# Backside Symbol PIN# Backside Symbol 1 VREF 48 A0 93 VSS 140 NC / DM8/DQS17 2 3 DQ0 VSS 49 50 NC / CB2 VSS 94 95 DQ4 DQ5 141 142 A10 NC / CB6 4 5 DQ1 DQS0 51 52 NC / CB3 BA1 96 97 VDDQ DM0/DQS9 143 144 VDDQ NC / CB7 6 7 DQ2 VDD 53 KEY DQ32 98 99 DQ6 DQ7 145 KEY VSS 8 9 DQ3 NC 54 55 VDDQ DQ33 100 101 VSS NC 146 147 DQ36 DQ37 10 11 NC VSS 56 57 DQS4 DQ34 102 103 NC NC 148 149 VDD DM4/DQS13 12 13 DQ8 DQ9 58 59 VSS BA0 104 105 VDDQ DQ12 150 151 DQ38 DQ39 14 15 DQS1 VDDQ 60 61 DQ35 DQ40 106 107 DQ13 DM1/DQS10 152 153 VSS DQ44 16 17 CLK1 CLK1 62 63 VDDQ WE 108 109 VDD DQ14 154 155 RAS DQ45 18 VSS 64 DQ41 110 DQ15 156 VDDQ 19 20 DQ10 DQ11 65 66 CAS VSS 111 112 CKE1 VDDQ 157 158 S0 S1 21 22 CKE0 VDDQ 67 68 DQS5 DQ42 113 114 NC (BA2) DQ20 159 160 DM5/DQS14 VSS 23 24 DQ16 DQ17 69 70 DQ43 VDD 115 116 NC / A12 VSS 161 162 DQ46 DQ47 25 26 DQS2 VSS 71 72 NC DQ48 117 118 DQ21 A11 163 164 NC VDDQ 27 28 A9 DQ18 73 74 DQ49 VSS 119 120 DM2/DQS11 VDD 165 166 DQ52 DQ53 29 30 A7 VDDQ 75 76 CLK2 CLK2 121 122 DQ22 A8 167 168 NC (A13) VDD 31 32 DQ19 A5 77 78 VDDQ DQS6 123 124 DQ23 VSS 169 170 DM6/DQS15 DQ54 33 34 DQ24 VSS 79 80 DQ50 DQ51 125 126 A6 DQ28 171 172 DQ55 VDDQ 35 36 DQ25 DQS3 81 82 VSS VDDID 127 128 DQ29 VDDQ 173 174 NC DQ60 37 38 A4 VDD 83 84 DQ56 DQ57 129 130 DM3/DQS12 A3 175 176 DQ61 VSS 39 40 DQ26 DQ27 85 86 VDD DQS7 131 132 DQ30 VSS 177 178 DM7/DQS16 DQ62 41 42 A2 VSS 87 88 DQ58 DQ59 133 134 DQ31 NC / CB4 179 180 DQ63 VDDQ 43 44 A1 NC / CB0 89 90 VSS NC 135 136 NC / CB5 VDDQ 181 182 SA0 SA1 45 46 NC / CB1 VDD 91 92 SDA SCL 137 138 CK0 CK0 183 184 SA2 VDDSPD 139 VSS 47 NC / DQS8 Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC modules. A12 is used for 256Mbit based modules only INFINEON Technologies 4 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules S0 DQS0 DM0/DQS9 DQS4 DM4/DQS13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D0 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS CS DQS D4 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1 DQS D5 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D2 DQS3 DM3/DQS12 DQS D6 DQS7 DM7/DQS16 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D3 DQS D7 * Clock Wiring Serial PD SDA SCL A0 A1 A2 SA0 SA1 SA2 BA0 - BA1 BA0, BA1: SDRAMs D0 - D7 A0 -A11, A12 A0 - A11,A12: SDRAMs D0 - D7 RAS VDD, VDDQ D0 - D7 VREF D0 - D7 VSS D0 - D7 Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 2 SDRAMs 3 SDRAMs 3 SDRAMs * Wire per Clock Loading Table/W iring Diagrams RAS: SDRAMs D0 - D7 CAS CAS: SDRAMs D0 - D7 CKE0 CKE: SDRAMs D0 - D7 WE W E : SDRAMs D0 - D7 VDDID Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: One Bank 32M x 64 DDR-I SDRAM DIMM Module HYS64D32000GU using x8 organized SDRAMs INFINEON Technologies 5 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules S1 S0 DQS4 DM4/DQS13 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D0 CS DQS D8 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D1 CS DQS D9 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DQS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 CS DQS D5 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D6 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D14 DQS7 DM7/DQS16 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 DQS D7 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D15 * Clock W iring BA0, BA1 BA0, BA1: SDRAMs D0, D15 A0 - A12 A0 - A12: SDRAMs D0 - D15 VDD, VDDQ VREF VSS Serial PD SDA D0 - D15 SCL A0 A1 A2 SA0 SA1 SA2 Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 4 SDRAMs 6 SDRAMs 6 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams D0 - D15 D0 - D15 VDDID CKE1 CKE: SDRAMs D8 - D15 RAS RAS: SDRAMs D0 - D15 CAS CAS: SDRAMs D0 - D15 CKE0 CKE: SDRAMs D0 - D7 WE WE: SDRAMs D0 - D15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: Two Bank 64M x 64 DDR-I SDRAM DIMM Modules HYS64D64020GU using x8 Organized SDRAMs INFINEON Technologies 6 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules S0 DQS0 DM0/DQS9 DQS4 DM4/DQS13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS D0 DQS D4 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1 DQS D5 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D2 DQS3 DM3/DQS12 DQS D6 DQS7 DM7/DQS16 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D3 DQS D7 DQS8 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS D8 SDA SCL BA0, BA1 BA0, BA1: SDRAMs D0 - D8 A0 - A11,A12 A0 - A11, A12: SDRAMs D0 - D8 VDD, VDDQ VREF VSS Serial PD DQS D0 - D8 D0 - D8 D0 - D8 A0 A1 A2 SA0 SA1 SA2 * Clock W iring RAS RAS: SDRAMs D0 - D8 CAS CAS: SDRAMs D0 - D8 CKE0 CKE: SDRAMs D0 - D8 WE WE: SDRAMs D0 - D8 VDDID Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 3 SDRAMs 3 SDRAMs 3 SDRAMs * Wire per Clock Loading Table/W iring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: One Bank 32M x 72 DDR-I SDRAM DIMM Module HYS72D32000GU using x8 organized SDRAMs INFINEON Technologies 7 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules S1 S0 DQS4 DM4/DQS13 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D0 CS DQS D9 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D1 CS DQS D10 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS D2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D13 CS DQS D5 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D14 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D6 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D15 DQS7 DM7/DQS16 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS D4 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D12 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D7 CS DQS D16 DQS8 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D8 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D17 * Clock Wiring BA0, BA1 BA0, BA1: SDRAMs D0 - D17 A0 - A12 A0 - A12: SDRAMs D0 - D17 SDA VDD, VDDQ VREF VSS D0 - D17 Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 6 SDRAMs 6 SDRAMs 6 SDRAMs Serial PD SCL D0 - D17 A0 A1 A2 SA0 SA1 SA2 * Wire per Clock Loading Table/Wiring Diagrams D0 - D17 VDDID CKE1 CKE: SDRAMs D9 - D17 RAS RAS: SDRAMs D0 - D17 CAS CAS: SDRAMs D0 - D17 CKE0 CKE: SDRAMs D0 - D8 WE WE: SDRAMs D0 - D17 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: Two Bank 64M x 72 DDR-I SDRAM DIMM Modules HYS72D64020GU using x8 Organized SDRAMs INFINEON Technologies 8 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Clock Net Wiring 4 DRAM Loads 6 DRAM Loads DR AM 1 DR AM 1 DRAM2 CK DRAM2 R = 120 R =120 DRAM3 DIMM Connector Cap. DIMM Connector CK DR AM4 Cap. DR AM5 DR AM5 DR AM6 DRAM6 DR AM 1 3 DRAM Loads 2 DRAM Loads DR AM 1 Cap. Cap. R =120 R =120 Cap. DIMM Connector DR AM3 DIMM Connector Cap. Cap. DR AM5 DR AM5 Cap. Cap. Absolute Maximum Ratings Parameter Symbol Limit Values min. Unit max. Input / Output voltage relative to VSS VIN, VOUT – 0.5 3.6 V Power supply voltage on V DD/V DDQ to V SS VDD, VDDQ – 0.5 3.6 V Storage temperature range TSTG -55 +150 o Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA C Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability INFINEON Technologies 9 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Supply Voltage Levels Parameter Symbol Limit Values min. nom. max. Unit Notes Device Supply Voltage VDD 2.3 2.5 2.7 V – Output Supply Voltage VDDQ 2.3 2.5 2.7 V 1) Input Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 2) Termination Voltage VTT VREF – 0.04 VREF VREF + 0.04 V 3) EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V 1) 2) 3) Under all conditions, VDDQ must be less than or equal to VDD . Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT of the transmitting device must track VREF of the receiving device. DC Operating Conditions (SSTL_2 Inputs) (V DDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS) Parameter Symbol Limit Values min. Unit Notes max. DC Input Logic High VIH (DC) VREF + 0.15 VDDQ + 0.3 V 1) DC Input Logic Low VIL (DC) – 0.30 VREF – 0.15 V – Input Leakage Current IIL –5 5 µA 2) Output Leakage Current IOL –5 5 µA 2) 1) 2) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component- INFINEON Technologies 10 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Unit Notes typ. typ. 592 666 944 1062 mA 1,3 IDD1 Burst = 4; Reads; Refer to the detailed test conditions in the 568 639 920 1035 mA 1,3 Power-Down Standby Current: all banks idle; IDD2P Precharge power-down mode; CKE ≤ VIL MAX; tCK = 10 ns 88 99 176 198 mA 1,4 200 225 400 450 mA 1,4 IDD2Q idle; CKE ≥ VIH MIN; tCK = 10 ns,address and other control inputs 192 216 383 432 mA 1,4 Power-Down Standby Current: one bank active; IDD3P Active power-down mode; CKE ≤ V ; t = 10 ns 88 99 176 198 mA 1,4 352 396 704 792 mA 1,4 872 981 1224 1377 mA 1,3 872 981 1224 1377 mA 1,3 IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 984 1107 1968 2214 mA 1,4 IDD6 Self-Refresh Current: CKE ≤ 0.2V 15.2 17.1 30.4 34.2 mA 1,2,4 1456 1638 1808 2034 mA DRAM Technology: IDD0 Operating Current - One bank Active - Precharge; tRC = tRC MIN; tCK = 10 ns; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once per every two cycles HYS72D64020GU-8-A typ. Parameter/Condition HYS64D64020GU-8-A HYS72D32000GU-8-A typ. Symbol HYS64D32000GU-8-A Operating, Standby and Refresh Currents (PC1600) 256Mbit Operating Current - One bank Active / Read / Precharge; component datasheet IDD2F Precharge Floating Standby Current: CS ≥ VIH MIN, all banks idle; CKE ≥ VIH MIN; tCK = 10 ns, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: CS ≥ VIH MIN, all banks stable at ≥ VIH MIN or ≤ VIL MAX; VIN = VREF for DQ, DQS and DM. IL MAX CK Active Standby Current: one bank; active / precharge;CS ≥ VIH MIN; CKE ≥ VIH MIN; tRC = tRAS MAX; tCK = 10 ns; DQ, DM, and IDD3N DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current - Burst Read: one bank; Burst = 2; reads; burst; address and control inputs changing once per IDD4R continuous clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2; tCK = 10 ns; IOUT = 0mA Operating Current - Burst Write: one bank; Burst = 2; writes; burst; address and control inputs changing once per I DD4W continuous clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2; tCK = 10 ns Operating Current - Four bank operation; four bank inter- IDD7 leaving with BL=4; Refer to the detailed test conditions in the 1,3 component datasheet 1. IDD currents are measured after the device is properly initialized. Typical values are obtained from characterisation data measured at VDD = 2.5 V and R.T. with an input slew rate = 1V/ns. 2. Enables on-chip refresh and address counters. 3. For two bank modules only : the other bank is in IDD3N mode 4. For two bank modules only : both banks operate in the same current mode INFINEON Technologies 11 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Unit Notes typ. typ. 680 765 1104 1242 mA 1,3 IDD1 Burst = 4; Reads; Refer to the detailed test conditions in the 704 792 1128 1269 mA 1,3 Power-Down Standby Current: all banks idle; IDD2P Precharge power-down mode; CKE ≤ VIL MAX; tCK = 7.5 ns 104 117 208 234 mA 1,4 232 261 464 522 mA 1,4 IDD2Q idle; CKE ≥ VIH MIN; t CK = 7.5 ns,address and other control inputs 216 243 432 486 mA 1,4 Power-Down Standby Current: one bank active; IDD3P Active power-down mode; CKE ≤ V ; t = 7.5 ns 104 117 208 234 mA 1,4 424 477 848 954 mA 1,4 burst; address and control inputs changing once per IDD4R continuous 1088 clock cycle; DQ and DQS outputs changing twice per clock 1224 1512 1701 mA 1,3 1251 1536 1728 mA 1,3 1,4 DRAM Technology: IDD0 Operating Current - One bank Active - Precharge; tRC = tRC MIN; tCK = 7.5 ns; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once per every two cycles HYS72D64020GU-7-A typ. Parameter/Condition HYS64D64020GU-7-A HYS72D32000GU-7-A typ. Symbol HYS64D32000GU-7-A Operating, Standby and Refresh Currents (PC2100) 256Mbit Operating Current - One bank Active / Read / Precharge; component datasheet IDD2F Precharge Floating Standby Current: CS ≥ VIH MIN, all banks idle; CKE ≥ VIH MIN; tCK = 7.5 ns, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: CS ≥ VIH MIN, all banks stable at ≥ VIH MIN or ≤ VIL MAX; VIN = VREF for DQ, DQS and DM. IL MAX CK Active Standby Current: one bank; active / precharge;CS ≥ VIH MIN; CKE ≥ VIH MIN; tRC = tRAS MAX; tCK = 7.5 ns; DQ, DM, and IDD3N DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current - Burst Read: one bank; Burst = 2; reads; cycle; CL = 2; tCK = 7.5 ns; IOUT = 0mA Operating Current - Burst Write: one bank; Burst = 2; writes; burst; address and control inputs changing once per 1112 I DD4W continuous clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2; tCK = 7.5 ns IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 1352 1521 2704 3042 mA IDD6 Self-Refresh Current: CKE ≤ 0.2V 15.2 17.1 30.4 34.2 mA 1,2,4 1576 1773 2000 2250 mA Operating Current - Four bank operation; four bank inter- IDD7 leaving with BL=4; Refer to the detailed test conditions in the 1,3 component datasheet 1. IDD currents are measured after the device is properly initialized. Typical values are obtained from characterisation data measured at VDD = 2.5 V and R.T. with an input slew rate = 1V/ns. 2. Enables on-chip refresh and address counters. 3. For two bank modules only : the other bank is in IDD3N mode 4. For two bank modules only : both banks operate in the same current mode INFINEON Technologies 12 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) Symbol tAC tDQSCK DDR266A -7 Parameter DDR200 -8 Unit Notes + 0.8 ns 1-4 + 0.8 ns 1-4 Min Max Min Max DQ output access time from CK/CK − 0.75 + 0.75 − 0.8 DQS output access time from CK/CK − 0.75 + 0.75 − 0.8 tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4 tHP Clock Half Period tCK CL = 2.5 min (tCL, tCH) min (t CL, tCH) ns 1-4 7 12 8 12 ns 1-4 7.5 12 10 12 Clock cycle time tCK ns 1-4 tDH DQ and DM input hold time CL = 2.0 0.5 0.6 ns 1-4 tDS DQ and DM input setup time 0.5 0.6 ns 1-4 tIPW Control and Addr. input pulse width (each input) 2.2 2.5 ns 1, 10 tDIPW DQ and DM input pulse width (each input) 1.75 2 ns 1-4, 11 tHZ Data-out high-impedence time from CK/CK − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 tLZ Data-out low-impedence time from CK/CK − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 0.75 1.25 0.75 1.25 tCK 1-4 1-4 tDQSS Write command to 1st DQS latching transition tDQSQ DQS-DQ skew (for DQS & associated DQ signals) + 0.5 + 0.6 ns tQHS Data hold skew factor + 0.75 + 1.0 ns 1-4 tQH Data Output hold time from DQS tHP-tQHS tHP-tQHS ns 1-4 DQS input low (high) pulse width (write cycle) 0.35 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 tCK 1-4 tMRD tDQSL,H Mode register set command cycle time 14 16 ns 1-4 tWPRES Write preamble setup time 0 0 ns 1-4, 7 tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 tCK 1-4 fast slew rate 0.9 1.1 ns slow slew rate 1.0 1.1 ns fast slew rate 0.9 1.1 ns tIS tIH Address and control input setup time Address and control input hold time slow slew rate 0.60 1.0 0.40 0.60 1.1 2-4, 10,11 ns tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.60 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 45 120,000 50 120,000 ns 1-4 tRC Active to Active/Auto-refresh command period 65 ns 1-4 INFINEON Technologies 13 70 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) Symbol Parameter DDR266A -7 Min Max DDR200 -8 Min Unit Notes ns 1-4 Max tRFC Auto-refresh to Active/Auto-refresh command period tRCD Active to Read or Write delay 20 20 ns 1-4 tRP Precharge command period 20 20 ns 1-4 tRRD Active bank A to Active bank B command 15 15 ns 1-4 tWR Write recovery time 15 15 ns 1-4 tDAL Auto precharge write recovery + precharge time tCK 1-4,9 75 80 (twr/tck) + (trp/tck) tWTR Internal write to read command delay 1 1 tCK 1-4 tXSNR Exit self-refresh to non-read command 75 80 ns 1-4 tXSRD Exit self-refresh to read command 200 tREFI Average Periodic Refresh Interval tCK 1-4 128Mbit based 15.6 200 15.6 µs 1-4, 8 256 Mbit based 7.8 7.8 µs 1-4, 8 1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10. These parameters guarantee device timing, but they are not necessarily tested on each device 11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac) INFINEON Technologies 14 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules SPD Codes for PC1600 Modules “-8” Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM Config Refresh Rate/Type 13 14 15 16 17 18 SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies 128 256 DDR-SDRAM 12 / 13 10 1/2 x64 / x72 0 SSTL_2.5 8 ns 0.8 ns non-ECC / ECC Self-Refresh, 7.8 µs x8 na / x8 tCCD = 1 CLK 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) Addr. and Command Setup Time Addr. and Command Hold Time Data Input Setup Time Data Input Hold Time Superset Information INFINEON Technologies 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered 10.0 ns 0.8 ns not supported not supported 20 ns 15 ns 20 ns 50 ns 256MByte 1.1 ns 1.1 ns 0.6 ns 0.6 ns – 15 512 MBYte two banks x72 0 1 2 3 4 5 6 7 8 9 10 11 12 Hex 512 MByte two banks x64 SPD Entry Value 256 MByte one bank x72 Description 256MByte one bank x64 Byte# 80 08 07 0D 0A 01 40 00 00 01 48 02 08 02 40 00 04 80 80 00 82 08 00 01 02 48 02 08 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 40 B0 B0 60 60 00 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Minimum Core Cycle Time tRC Min. Auto Refresh Cmd Cycle Time tRFC Maximum Clock Cycle Time tck Max. DQS-DQ Skew tDDSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number 70 ns 80 ns 12 ns 0.6 ns 1.0 ns Revision 0.0 – – A7 512 MBYte two banks x72 41 42 43 44 45 46-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-127 128-255 Hex 512 MByte two banks x64 SPD Entry Value 256 MByte one bank x72 Description 256MByte one bank x64 Byte# 46 50 30 3C A0 00 00 B9 A8 BA C1 INFINEO(N) open for Customer use INFINEON Technologies 16 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules SPD Codes for PC2100 Modules “-7” Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM Config Refresh Rate/Type 13 14 15 16 17 18 SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies 128 256 DDR-SDRAM 12/13 10 1/2 x64 / x72 0 SSTL_2.5 7 ns 0.75 ns non-ECC / ECC Self-Refresh, 7.8 µs x8 na / x8 tCCD = 1 CLK 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Ac. Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) Addr. and Command Setup Time Addr. and Command Hold Time Data Input Setup Time Data Input Hold Time Superset Information INFINEON Technologies 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered 7.5 ns 0.75 ns not supported not supported 20 ns 15 ns 20 ns 45 ns 256MByte 0.9 ns 0.9 ns 0.5 ns 0.5 ns – 17 512 MBYte two banks x72 0 1 2 3 4 5 6 7 8 9 10 11 12 Hex 512 MByte two banks x64 SPD Entry Value 256 MByte one bank x72 Description 256MByte one bank x64 Byte# 80 08 07 0D 0A 01 40 01 48 02 40 02 48 00 02 00 04 70 75 00 02 82 00 08 08 00 01 08 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 40 90 90 50 50 00 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Minimum Core Cycle Time tRC Min. Auto Refresh Cmd Cycle Time tRFC Maximum Clock Cycle Time tck Max. DQS-DQ Skew tDDSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number 65 ns 75 ns 12 ns 0.5 ns 0.75 ns Revision 0.0 – – B2 512 MBYte two banks x72 41 42 43 44 45 46-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-127 128-255 Hex 512 MByte two banks x64 SPD Entry Value 256 MByte one bank x72 Description 256MByte one bank x64 Byte# 41 4B 30 32 75 00 00 C4 B3 C5 C1 INFINEO(N) open for Customer use INFINEON Technologies 18 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Package Outlines - Raw Card B1 (One Bank Modules) DDR-SDRAM DIMM Module Package 133.35 +- 0.15 4.0 max. 4.0 31.75 + - 0.13 Front View 2.3 typ. *) 52 pin 1 92 53 64.77 1.27 +- 0.1 49.53 2.3 typ. 6.62 Backside View 144 145 184 2.5D 10.0 17.78 pin 93 *) 3 3 *) on ECC modules only Detail of Contacts B Detail of Contacts A 2.5 +- 0.20 0.20 +- 0.15 6.35 3.8 typ. 0.9R 1+- 0.05 1.27 1.8 2.175 L-DIM-184-9 INFINEON Technologies 19 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Package Outlines -Raw Card A1 (One Bank Modules) DDR-SDRAM DIMM Module Package 133.35 +- 0.15 4.0 max. 4.0 31.75 + - 0.13 Front View 2.3 typ. *) 52 pin 1 92 53 64.77 1.27 +- 0.1 49.53 2.3 typ. 6.62 Backside View 144 145 184 2.5D 10.0 17.78 pin 93 3 3 *) on ECC modules only Detail of Contacts B Detail of Contacts A 2.5 +- 0.20 0.20 +- 0.15 6.35 3.8 typ. 0.9R 1+- 0.05 1.27 1.8 2.175 L-DIM-184-29 INFINEON Technologies 20 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules Package Outlines - Raw Card B1 (Two Bank Modules) DDR-SDRAM DIMM Module Package two bank modules 133.35 -+ 0.15 4.0 max. 4.0 31.75 + - 0.13 Front View 2.3 typ. *) 52 pin 1 92 53 64.77 1.27 +- 0.1 49.53 2.3 typ. 6.62 Backside View 144 145 184 2.5D 10.0 17.78 pin 93 *) 3 3 *) on ECC modules only Detail of Contacts B 6.35 2.5 +- 0.20 0.20 +- 0.15 Detail of Contacts A 3.8 typ. 0.9R 1+- 0.05 1.27 1.8 2.175 L-DIM-184-9d INFINEON Technologies 21 12.01 HYS64/72D32000/64020GU Unbuffered DDR-I SDRAM-Modules INFINEON Technologies 23 12.01