CY24142 MediaClock™ Multimedia Clock Generator Features Benefits • Integrated phase-locked loop (PLL) • Integrated high-performance PLL eliminates the need for • Low-jitter, high-accuracy outputs — external loop filter components • 3.3V operation • Meets critical timing requirements in complex system designs • Enables application compatibility Logic Block Diagram XIN Q OSC. Φ VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P CLK1 13.5 MHz CLK2 54 MHz PLL CLK3 18.432 MHz CLK4 18.432 MHz OE1 OE2 VDDL VDD AVDD AVSS VSS VSSL Pin Configuration CY24142 16-pin TSSOP XIN VDD 1 16 XOUT 2 15 AVDD 3 14 OE1 4 13 CLK4 CLK3 VSS AVSS 5 12 NC VSSL 6 11 VDDL NC 7 10 CLK1 8 9 OE2 CLK2 Frequency Table Part Number Outputs Input Frequency Output Frequency Range CY24142-01 4 18.432 13.5 MHz, 54 MHz, 2 x 18.432 MHz Output Enable Options[1] OE2 OE1 CLK1 CLK2 CLK3 CLK4 Unit 0 0 13.5 OFF OFF OFF MHz 0 1 13.5 54 18.432 OFF MHz 1 0 13.5 OFF OFF 18.432 MHz 1 1 13.5 54 18.432 18.432 MHz Note: 1. Output driven LOW when “OFF.” Cypress Semiconductor Corporation Document #: 38-07532 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2005 CY24142 Pin Description Pin Name Pin Number Pin Description XIN 1 Crystal Input. VDD 2 Voltage Supply. AVDD 3 Analog Voltage Supply. OE1 4 Output Enable 1, 0 = CLK 2 and CLK3 off, 1 = CLK 2 and CLK3 on; weak internal pull-down. AVSS 5 Analog Ground. VSSL 6 VDDL Ground. NC 7 No Connect; leave floating. CLK1 8 13.5-MHz Clock Output. CLK2 9 54-MHz Clock Output; controlled by OE1. OE2 10 Output Enable 2, 0 = CLK4 off, 1 = CLK4 on; weak internal pull-down. VDDL 11 Voltage Supply. NC 12 No Connect; leave floating. VSS 13 Ground. CLK3 14 18.432-MHz Buffered Reference Output, controlled by OE1. CLK4 15 18.432-MHz Buffered Reference Output, controlled by OE2. XOUT 16 Crystal Output. Layout Recommendations The XIN and XOUT traces and pads as well as the crystal should be placed away from any clock traces or noise sources. Noise coupling into the XIN and XOUT traces may cause start-up problems. A pad for a resistor to ground should be laid out on the XOUT trace to be stuffed if necessary, in case start-up issues occur. Document #: 38-07532 Rev. *B Page 2 of 7 CY24142 Absolute Maximum Conditions Storage Temperature (Non-Condensing).... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C (Above which the useful life may be impaired. For user guidelines, not tested. Data Retention @ Tj=125°C..................................> 10 years Supply Voltage (VDD, AVDD, VDDL) ...................–0.5 to +7.0V Package Power Dissipation...................................... 350 mW DC Input Voltage...................................... –0.5V to VDD + 0.5 ESD (Human Body Model) MIL-STD-883.................... 2000V Recommended Crystal Specifications Parameter Description Comments Min. FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR Ratio used because typical R1 values are much to fundamental mode ESR less than the maximum spec DL Crystal drive level Parallel resonance, fundamental mode, AT cut Typ. Max. Unit 18.432 MHz 14 pF 25 Ω 0.5 2 mW Min. Typ. Max. 3.15 3.45 Fundamental mode 3 No external series resistor assumed Recommended Operating Conditions Parameter Description VDD, AVDD, VDDL Supply Voltage TA Ambient Temperature CLOAD Max. Load Capacitance TPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Unit 3.6 V 0 85 °C 15 pF 0.05 500 ms Max. Unit DC Electrical Specifications Parameter Description [2] Output High Current IOL[2] Output Low Current IOH Conditions Min. Typ. VOH = VDD – 0.5, VDD/VDDL = 3.45V 12 24 mA VOL = 0.5, VDD/VDDL = 3.45V 12 24 mA IIH Input High Current VIH = VDD IIL Input Low Current VIL = 0V 5 50 µA 10 µA VDD VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD 0.3 IVDD Supply Current AVDD/VDD Current 25 mA IVDDL Supply Current VDDL Current 20 mA RDOWN Pull-down resistor on Inputs VDD = 3.15 to 3.6V, measured VIN = 3.45V 100 150 kΩ CXTAL[2] Crystal Load Capacitance Total effective load of internal load caps 12.9 0.7 VDD pF Cycle-Cycle Jitter Specifications (VDD = 3.15V – 3.6V) Parameter Description 1σ Typ. Max. Unit Cycle-Cycle Jitter–18.432 MHz 20 120 200 ps Clock Jitter–peak-peak Cycle-Cycle Jitter–54 MHz 40 150 250 ps Clock Jitter–peak-peak Cycle-Cycle Jitter–13.5 MHz 20 120 200 ps t9 Clock Jitter–peak-peak t9 t9 Conditions Note: 2. Guaranteed by characterization, not 100% tested. Document #: 38-07532 Rev. *B Page 3 of 7 CY24142 Test and Measurement Set-up VDDs Outputs 0.1 µF CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t4 t3 V DD 80% of V DD 20% of V DD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 VDD/VDDL/AVDD 3.15V t5 Output stable within PPM Spec. Figure 3. PLL Lock Time Document #: 38-07532 Rev. *B Page 4 of 7 CY24142 tcycle,i tcycle,i+1 t6 = tcycle,i - tcycle,i+1 Figure 4. 54MOUT, LCLK Cycle-to-Cycle Jitter 1000 cycles ... 1000 cycles ... t1000cycle,i t1000cycle,i+1 t7 = t1000cycle,i - t1000cycle,i+1 Figure 5. 54MOUT, LCLK 1000 Cycle Jitter Ordering Information Ordering Code Package Type Operating Range Operating Voltage Standard CY24142ZC-01 16-pin TSSOP Commercial 3.45V CY24142ZC-01T 16-pin TSSOP – Tape and Reel Commercial 3.45V CY24142ZXC-01 16-pin TSSOP Commercial 3.45V CY24142ZXC-01T 16-pin TSSOP – Tape and Reel Commercial 3.45V Lead-free Document #: 38-07532 Rev. *B Page 5 of 7 CY24142 Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 1 MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05gms 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07532 Rev. *B Page 6 of 7 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24142 Document History Page Document Title: CY24142 MediaClock™ Multimedia Clock Generator Document Number: 38-07532 REV. ECN No. Issue Date Orig. of Change Description of Change ** 127352 09/08/03 RGL New Data Sheet *A 130343 10/13/03 RGL Changed the part number from CY24142-1 to CY24142-01. *B 310574 See ECN RGL Added Lead-free Document #: 38-07532 Rev. *B Page 7 of 7