025/0251 PRELIMINARY CY26118 19.6608-MHz Clock Generator Features Benefits • Integrated phase-locked loop (PLL) Highest-performance PLL tailored for multimedia applications • Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • 3.3V operation Part Number CY26118 Outputs 1 Input Frequency Range 15.0000 MHz Output Frequencies 19.6608 MHz Logic Block Diagram Pin Configuration 15.0000 XIN OSC XOUT Q OUTPUT DIVIDER Φ VCO CY26118 8-pin SOIC 19.6608 MHz P PLL AVDD VDD Cypress Semiconductor Corporation Document #: 38-07274 Rev. *A AVSS • XIN 1 8 XOUT AVDD N/C 2 7 3 6 AVSS 4 5 VSS 19.6608 MHz VDD VSS 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2001 CY26118 PRELIMINARY Pin Summary Name Pin Number Description XIN 1 15.000 MHz Reference Crystal Input AVDD 2 Analog Voltage Supply N/C 3 No Connect AVSS 4 Analog Ground VDD 5 Output Voltage Supply 19.6608 MHz 6 19.6608-MHz clock output VSS 7 Output Ground 8 Reference Crystal Output XOUT [1] Absolute Maximum Conditions Parameter Description Supply Voltage VDD Temperature[2] TS Storage TJ Junction Temperature Min. Max. Unit –0.5 7.0 V –65 125 °C 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V 2000 V Electro-Static Discharge Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature Min. Typ. Max. 3.0 3.3 3.6 V 70 °C 0 Unit CLOAD Max Load Capacitance 15 pF Pmax Max Output Power Dissipation, 8-pin package 150 ° C/W fREF Reference Frequency tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 15.000 MHz 0.05 500 ms DC Electrical Characteristics Min. Typ. IOH Parameter Output High Current Name VOH = VDD – 0.5, VDD = 3.3V Description 12 24 IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 CIN Input Capacitance IIZ Input Leakage Current IDD Supply Current Max. mA mA 7 pF 20 mA 5 Sum of Core and Output Current Unit mA Notes: 1. 2. Float XOUT if XIN is externally driven. Rated for 10 years. Document #: 38-07274 Rev. *A Page 2 of 5 CY26118 PRELIMINARY AC Electrical Characteristics (VDD = 3.3V) Parameter[3] DC Min. Typ. Max. Unit Output Duty Cycle Name Duty Cycle is defined in Figure 1 50% of VDD Description 45 50 55 % t3 Rising Edge Slew Rate Output Clock Rise Time 20% - 80% of VDD 0.8 1.8 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time 80% to 20% of VDD 0.8 1.8 V/ns t9 Clock Jitter Peak-to-Peak period jitter t10 PLL Lock Time 200 ps 3 ms Note: 3. Not 100% tested. t1 t3 t4 t2 80% 50% 20% 19.6608 MHz 19.6608 MHz Figure 2. Rise and Fall Time Definitions Figure 1. Duty Cycle Definition; DC = t2/t1 Test Circuit AVDD CLK out 0.1 µF CLOAD OUTPUTS VDD 0.1 µF GND Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26118SC S8 8-Pin SOIC Commercial 3.3V Document #: 38-07274 Rev. *A Page 3 of 5 PRELIMINARY CY26118 Pin Diagrams 8-Lead (150-Mil) SOIC S8 Document #: 38-07274 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY26118 Document Title: CY26118 19.6608-MHz Clock Generator Document Number: 38-07274 REV. ECN NO. Issue Date Orig. of Change ** 110764 02/06/02 CKN New Data Sheet *A 121883 12/14/02 RBI Power up requirements added to Operating Conditions Information Document #: 38-07274 Rev. *A Description of Change Page 5 of 5