CY62126DV30 MoBL® 1-Mbit (64K x 16) Static RAM Features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). • Very high speed — 55 ns • Temperature Ranges — Industrial: –40°C to 85°C — Automotive: –40°C to 125°C • Wide voltage range — 2.2V - 3.6V • Pin compatible with CY62126BV • Ultra-low active power — Typical active current: 0.85 mA @ f = 1 MHz — Typical active current: 5 mA @ f = fMax (55 ns speed) • Ultra-low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • Available in Pb-free and non Pb-free 48-ball VFBGA and 44-pin TSOP Type II packages Functional Description[1] The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. Logic Block Diagram 64K x 16 RAM Array SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0–I/O7 I/O8–I/O15 BHE WE CE OE BLE A14 A15 A12 A13 A11 COLUMN DECODER Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05230 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 18, 2006 [+] Feedback CY62126DV30 MoBL® Product Portfolio Power Dissipation Operating, ICC (mA) VCC Range (V) f = 1 MHz f = fMax Standby, ISB2 (µA) Range Min. Typ. Max. Speed (ns) Typ.[2] Max. Typ.[2] Max. Typ.[2] Max. CY62126DV30L Automotive 2.2 3.0 3.6 55 0.85 1.5 5 10 1.5 15 CY62126DV30LL Industrial 55 0.85 1.5 5 10 1.5 4 Product Pin Configurations[3, 4] 48-ball VFBGA Top View TSOP II (Forward) Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 DNU NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 3. NC pins are not connected to the die. 4. E3 (DNU) can be left as NC or VSS to ensure proper operation. (Expansion Pins on FBGA Package: E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M). Document #: 38-05230 Rev. *H Page 2 of 12 [+] Feedback CY62126DV30 MoBL® DC Input Voltage[6] ................................ −0.3V to VCC + 0.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ..............................................................−0.3 to 3.9V DC Voltage Applied to Outputs in High-Z State[6] ....................................−0.3V to VCC + 0.3V Range Ambient Temperature (TA) VCC[7] Industrial −40°C to +85°C 2.2V to 3.6V Automotive −40°C to +125°C 2.2V to 3.6V DC Electrical Characteristics (Over the Operating Range) CY62126DV30-55 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Test Conditions Min. Typ.[5] Max. Output HIGH Voltage 2.2V < VCC < 2.7V IOH = −0.1 mA 2.0 2.7V < VCC < 3.6V IOH = −1.0 mA 2.4 Output LOW Voltage 2.2V < VCC < 2.7V IOL = 0.1 mA 0.4 2.7V < VCC < 3.6V IOL = 2.1 mA 0.4 Input HIGH Voltage 2.2V < VCC < 2.7V 1.8 VCC + 0.3 2.7V < VCC < 3.6V 2.2 VCC + 0.3 Input LOW Voltage 2.2V < VCC < 2.7V −0.3 0.6 2.7V < VCC < 3.6V −0.3 0.8 Ind’l −1 +1 Auto −4 +4 Ind’l −1 +1 Auto −4 +4 Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current f = fMax = 1/tRC Automatic CE Power-down Current— CMOS Inputs CE > VCC − 0.2V, VIN > VCC − 0.2V, VIN < 0.2V, f = fMax (Address and Data Only), f = 0 (OE, WE, BHE and BLE) Automatic CE Power-down Current— CMOS Inputs CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC = 3.6V f = 1 MHz VCC = 3.6V, IOUT = 0 mA, CMOS level L L LL V 5 10 0.85 1.5 Ind’l 1.5 5 Auto 1.5 15 1.5 4 Ind’l 1.5 5 Auto 1.5 15 1.5 4 LL Unit V V V µA µA mA µA µA Notes: 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 6. VIL(min.) = −2.0V for pulse durations less than 20 ns., VIH(max.) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device operation requires linear ramp of VCC from 0V to VCC(min) & VCC must be stable at VCC(min) for 500 µs. Document #: 38-05230 Rev. *H Page 3 of 12 [+] Feedback CY62126DV30 MoBL® Capacitance[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 8 pF 8 pF TSOP VFBGA Unit 55 76 °C/W 12 11 °C/W TA = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance[8] Parameter ΘJA Description Test Conditions Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch, 2-layer printed circuit board Thermal Resistance (Junction to Case) ΘJC AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC Typ 50 pF 90% 10% 90% 10% GND Rise TIme: 1 V/ns R2 Fall Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.5V 3.0V Unit R1 16600 1103 Ohms R2 15400 1554 Ohms RTH 8000 645 Ohms VTH 1.2 1.75 Volts Data Retention Characteristics Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current Conditions Min. Typ[2] Max. 1.5 VCC=1.5V, CE > VCC − 0.2V, VIN > VCC − 0.2V or VIN < 0.2V tCDR[8] Chip Deselect to Data Retention Time tR[9] Operation Recovery Time Unit V L Ind’l 4 L Auto 10 LL Ind’l 3 µA 0 ns 100 µs Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5 V tCDR VCC(min) tR CE Notes: 8. Tested initially and after any design or proces changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) >100 µs. Document #: 38-05230 Rev. *H Page 4 of 12 [+] Feedback CY62126DV30 MoBL® Switching Characteristics (Over the Operating Range)[10] CY62126DV30-55 Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 ns tDOE OE LOW to Data Valid 25 ns tLZOE OE LOW to Low Z[11] tHZOE OE HIGH to High Z[11, 12] tLZCE 55 ns 55 10 ns 5 [11] CE LOW to Low Z ns 20 10 Z[11, 12] ns ns ns tHZCE CE HIGH to High 20 tPU CE LOW to Power-up tPD CE HIGH to Power-down 55 ns tDBE BLE/BHE LOW to Data Valid 25 ns 0 Z[11] tLZBE BLE/BHE LOW to Low tHZBE BLE/BHE HIGH to High-Z[11, 12] ns ns 5 ns 20 ns Write Cycle[13] tWC Write Cycle Time 55 ns tSCE CE LOW to Write End 40 ns tAW Address Set-up to Write End 40 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 40 ns tBW BLE/BHE LOW to Write End 40 ns tSD Data Set-up to Write End 25 ns tHD Data Hold from Write End 0 ns Z[11, 12] tHZWE WE LOW to High tLZWE WE HIGH to Low Z[11] 20 10 ns ns Notes: 10. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05230 Rev. *H Page 5 of 12 [+] Feedback CY62126DV30 MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[14, 15] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tPD tHZCE tACE OE ttLZOE LZOE BHE/BLE tHZOE tDOE tHZBE tDBE tLZBE HIGH IMPEDANCE DATA OUT HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT ICC 50% 50% ISB Notes: 14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE, BHE, BLE transition LOW. Document #: 38-05230 Rev. *H Page 6 of 12 [+] Feedback CY62126DV30 MoBL® Switching Waveforms(continued) Write Cycle No. 1 (WE Controlled[12, 13, 16, 17, 18] tWC ADDRESS tSCE CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O NOTE 19 tHD DATAIN VALID tHZOE Write Cycle No. 2 (CE Controlled)[12, 13, 16, 17, 18] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O DATAIN NOTE 19 tHD VALID tHZOE Notes: 17. Data I/O is high-impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05230 Rev. *H Page 7 of 12 [+] Feedback CY62126DV30 MoBL® Switching Waveforms(continued) Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATAI/O NOTE 19 tHD DATAIN VALID tLZWE tHZWE Write Cycle No. 4 (BHE/BLE-controlled, OE LOW)[17, 18] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 19 Document #: 38-05230 Rev. *H tHD DATAIN VALID Page 8 of 12 [+] Feedback CY62126DV30 MoBL® Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (ISB) L X X H H High Z Output Disabled Active (ICC) L H L L L Data Out (I/O0–I/O15) Read Active (ICC) L H L H L High Z (I/O8–I/O15); Data Out (I/O0–I/O7) Read Active (ICC) L H L L H Data Out (I/O8–I/O15); High Z (I/O0–I/O7) Read Active (ICC) L L X L L Data In (I/O0–I/O15) Write Active (ICC) L L X H L High Z (I/O8–I/O15); Data In (I/O0–I/O7) Write Active (ICC) L L X L H Data in (I/O8–I/O15); High Z (I/O0–I/O7) Write Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) Ordering Information Speed (ns) 55 Ordering Code CY62126DV30LL-55BVI Package Diagram 51-85150 CY62126DV30LL-55BVXI CY62126DV30LL-55ZI Package Type 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) Operating Range Industrial 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) (Pb-free) 51-85087 CY62126DV30LL-55ZXI 44-pin TSOP II 44-pin TSOP II (Pb-free) CY62126DV30L-55BVXE 51-85150 48-ball Fine-Pitch Ball Grid Array (6 x 8 x 1 mm) (Pb-free) CY62126DV30L-55ZSXE 51-85087 44-pin TSOP II (Pb-free) Automotive Please contact your local Cypress sales representative for availability of these parts Document #: 38-05230 Rev. *H Page 9 of 12 [+] Feedback CY62126DV30 MoBL® Package Diagrams 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 4 5 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 0.55 MAX. 6.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.25 C B 51-85150-*D C Document #: 38-05230 Rev. *H 1.00 MAX 0.26 MAX. SEATING PLANE Page 10 of 12 [+] Feedback CY62126DV30 MoBL® Package Diagrams(continued) 44-pin TSOP II (51-85087) 51-85087-*A MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05230 Rev. *H Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62126DV30 MoBL® Document History Page Document Title: CY62126DV30 MoBL® 1-Mbit (64K x 16) Static RAM Document Number: 38-05230 REV. Orig. of ECN NO. Issue Date Change Description of Change ** 117689 08/27/02 JUI *A 127313 06/13/03 MPR Changed From Advanced Status to Preliminary. Changed ISB2 to 5 µA (L), 4 µA (LL) Changed ICCDR to 4 µA (L), 3 µA (LL) Changed CIN from 6 pF to 8 pF New Data Sheet *B 128340 07/22/03 JUI Changed from Preliminary to Final Add 70-ns speed, updated ordering information *C 129002 08/29/03 CDY Changed ICC 1 MHz typ from 0.5 mA to 0.85 mA *D 238050 See ECN AJU Fixed typo: Changed tDBE from 70 ns to 35 ns *E 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #8 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-pin TSOP-II package name from Z44 to ZS44 *F 335861 See ECN SYT Added Temperature Ranges in the Features Section on Page # 1 Added Automotive Product Information for CY62126DV30-L for 55 ns Added ISB1 and ISB2 values for Automotive range of CY62126DV30-L for 55 ns Added Automotive Information for ICCDR in the Data Retention Characteristics table Added Pb-free packages in the ordering information Changed 44-pin TSOP-II package name from ZS44 to Z44 *G 357256 See ECN PCI Added Pin Configuration and Package Diagram for 56-Lead QFN Package Updated Thermal Characteristics and Ordering Information Table Added Automotive Specs for IIX and IOZ in the DC Electrical Characteristics table on Page# 4 *H 486789 See ECN VKN Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 45 ns and 70ns Speed bin from Product offering Removed 56-pin QFN package Updated Ordering Information Table Document #: 38-05230 Rev. *H Page 12 of 12 [+] Feedback