CY62167EV18 MoBL® 16 Mbit (1M x 16) Static RAM Features by 99 percent when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: the device is deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE HIGH); both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH); and a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). ■ Very high speed: 55 ns ■ Wide voltage range: 1.65V to 2.25V ■ Ultra low standby power ❐ Typical standby current: 1.5 μA ❐ Maximum standby current: 12 μA ■ Ultra low active power ❐ Typical active current: 2.2 mA at f = 1 MHz ■ Easy memory expansion with CE1, CE2, and OE features ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Offered in Pb-free 48-ball VFBGA packages Functional Description The CY62167EV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 9 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 1M × 16 RAM ARRAY IO0–IO7 IO8–IO15 COLUMN DECODER BHE CE2 CE1 A11 A12 A13 A14 A15 A16 A17 A18 A19 Power Down Circuit BHE • 198 Champion Court CE2 OE CE1 BLE BLE Cypress Semiconductor Corporation Document #: 38-05447 Rev. *G WE • San Jose, CA 95134-1709 • 408-943-2600 Revised March 13, 2009 [+] Feedback CY62167EV18 MoBL® Pin Configuration Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View [1, 2, 3] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A IO 8 BHE A3 A4 CE1 IO 0 B IO 9 IO 10 A5 A6 IO 1 IO 2 C VSS IO11 A17 A7 IO3 Vcc D VCC IO 12 NC A16 IO 4 Vss E IO 14 IO 13 A14 A15 IO 5 IO 6 F IO 15 A19 A12 A13 WE IO 7 G A18 A8 A9 A10 A11 NC H Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62167EV18LL Min Typ[4] Max 1.65 1.8 2.25 55 Standby ISB2 (μA) f = fmax Typ[4] Max Typ[4] Max Typ[4] Max 2.2 4.0 25 30 1.5 12 CY62167EV30LL[5] Notes 1. The information related to 6 x 7 x 1 mm VFBGA package is preliminary. 2. NC pins are not connected on the die. 3. Ball H6 for the VFBGA package can be used to upgrade to a 32M density. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 5. This part can be operated in the VCC range of 1.65V–2.25V at 55ns speed. It can also be operated in the VCC range of 2.2V–3.6V at 45ns speed. Document #: 38-05447 Rev. *G Page 2 of 13 [+] Feedback CY62167EV18 MoBL® DC Input Voltage[6, 7] ....... –0.2V to 2.45V (VCC(max) + 0.2V) Maximum Ratings Output Current into Outputs (LOW) ............................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Storage Temperature ................................ –65°C to + 150°C Latch up Current...................................................... >200 mA Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Operating Range Supply Voltage to Ground Potential .......................... –0.2V to 2.45V (VCC(max) + 0.2V) Device DC Voltage Applied to Outputs in High Z State[6, 7]........... –0.2V to 2.45V (VCC(max) + 0.2V) CY62167EV18LL Range Ambient Temperature VCC[8] Industrial –40°C to +85°C 1.65V to 2.25V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –0.1 mA VOL Output LOW Voltage IOL = 0.1 mA VIH Input HIGH Voltage VCC = 1.65V to 2.25V VIL Input LOW Voltage VCC = 1.65V to 2.25V IIX Input Leakage Current IOZ ICC 55 ns Min Typ[4] Unit Max 1.4 V 0.2 V 1.4 VCC + 0.2V V –0.2 0.4 V GND < VI < VCC –1 +1 μA Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 μA VCC Operating Supply Current f = fmax = 1/tRC 25 30 mA 2.2 4.0 mA ISB1 Automatic CE Power Down Current – CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V VIN > VCC – 0.2V, VIN < 0.2V) f = fmax(Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = VCC(max) 1.5 12 μA ISB2[9] Automatic CE Power Down Current – CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max) 1.5 12 μA VCC = VCC(max) IOUT = 0 mA CMOS levels f = 1 MHz Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Notes 6. VIL(min) = –2.0V for pulse durations less than 20 ns. 7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 8. Full Device AC operation is based on a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization. 9. Only chip enables (CE1 and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05447 Rev. *G Page 3 of 13 [+] Feedback CY62167EV18 MoBL® Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) VFBGA VFBGA (6 x 7 x 1mm) (6 x 8 x 1mm) Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board Unit 27.74 55 °C/W 9.84 16 °C/W Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT VCC 30 pF GND R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 1.8V Unit R1 13500 Ω R2 10800 Ω RTH 6000 Ω VTH 0.80 V Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR[9] Data Retention Current tCDR[10] Chip Deselect to Data Retention Time tR[11] Operation Recovery Time Conditions Min Typ[4] Max 1.0 V 10 VCC = 1.0V, CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Unit μA 0 ns tRC ns Figure 3. Data Retention Waveform VCC VCC(min) tCDR DATA RETENTION MODE VDR > 1.0 V VCC(min) tR CE1 or BHE.BLE [12] or CE2 Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. 12. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05447 Rev. *G Page 4 of 13 [+] Feedback CY62167EV18 MoBL® Switching Characteristics Over the Operating Range[13, 14] Parameter Description 55 ns Min Max Unit Read Cycle tRC Read Cycle Time 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 55 ns tDOE OE LOW to Data Valid 25 ns 55 OE LOW to Low-Z[15] tHZOE OE HIGH to High-Z[15, 16] tLZCE CE1 LOW and CE2 HIGH to Low-Z[15] tLZOE ns 10 ns 5 ns 18 10 High-Z[15, 16] ns ns ns tHZCE CE1 HIGH and CE2 LOW to tPU CE1 LOW and CE2 HIGH to Power Up tPD CE1 HIGH and CE2 LOW to Power Down 55 ns tDBE BLE/BHE LOW to Data Valid 55 ns tLZBE tHZBE BLE/BHE LOW to Low-Z[15] BLE/BHE HIGH to High-Z[15, 16] 18 0 ns ns 10 ns 18 ns [17] Write Cycle tWC Write Cycle Time 55 ns tSCE CE1 LOW and CE2 HIGH to Write End 40 ns tAW Address Setup to Write End 40 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 40 ns tBW BLE/BHE LOW to Write End 40 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE [15, 16] WE LOW to High-Z WE HIGH to Low-Z[15] 20 10 ns ns Notes 13. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4. 14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state. 17. The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05447 Rev. *G Page 5 of 13 [+] Feedback CY62167EV18 MoBL® Switching Waveforms Figure 4 shows address transition controlled read cycle waveforms.[18, 19] Figure 4. Read Cycle No. 1 tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5 shows OE controlled read cycle waveforms.[19, 20] Figure 5. Read Cycle No. 2 ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 18. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05447 Rev. *G Page 6 of 13 [+] Feedback CY62167EV18 MoBL® Switching Waveforms (continued) Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22] Figure 6. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA I/O NOTE 23 VALID DATA tHZOE Notes 21. Data IO is high impedance if OE = VIH. 22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 23. During this period the IOs are in output state. Do not apply input signals. Document #: 38-05447 Rev. *G Page 7 of 13 [+] Feedback CY62167EV18 MoBL® Switching Waveforms (continued) Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22] Figure 7. Write Cycle No. 2 tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE DATA I/O tHD tSD NOTE 23 VALID DATA tHZOE Figure 8 shows WE controlled, OE LOW write cycle waveforms.[22] Figure 8. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 23 VALID DATA tHZWE Document #: 38-05447 Rev. *G tHD tLZWE Page 8 of 13 [+] Feedback CY62167EV18 MoBL® Switching Waveforms (continued) Figure 9 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22] Figure 9. Write Cycle No. 4 tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD NOTE 23 DATA IO tHD VALID DATA Truth Table CE1 CE2 WE OE Mode Power H X X X BHE BLE X X High Z Inputs/Outputs Deselect / Power Down Standby (ISB) X L X X X X High Z Deselect / Power Down Standby (ISB) X X X X H H High Z Deselect / Power Down Standby (ISB) L H H L L L Data Out (I/O0–I/O15) Read Active (ICC) L H H L H L Data Out (I/O0–I/O7); High Z (I/O8–I/O15) Read Active (ICC) L H H L L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In (I/O0–I/O7); High Z (I/O8–I/O15) Write Active (ICC) L H L X L H High Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) Document #: 38-05447 Rev. *G Page 9 of 13 [+] Feedback CY62167EV18 MoBL® Ordering Information Speed (ns) 55 Package Diagram Ordering Code Package Type CY62167EV18LL-55BAXI 001-13297 48-ball VFBGA (6 × 7 × 1 mm) (Pb-free) CY62167EV18LL-55BVI 51-85150 CY62167EV18LL-55BVXI CY62167EV30LL-45BVI [5] Operating Range Industrial 48-ball VFBGA (6 × 8 × 1 mm) 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free) 51-85150 48-ball VFBGA (6 × 8 × 1 mm) Package Diagram Figure 10. 48-Ball VFBGA (6 x 7 x 1 mm), 001-13297 NOTES: 1. ALL DIMENSION ARE IN MM [MAX/MIN] 2. JEDEC REFERENCE : MO-216 3. PACKAGE WEIGHT : 0.03g Document #: 38-05447 Rev. *G 001-13297-*A Page 10 of 13 [+] Feedback CY62167EV18 MoBL® Package Diagram Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 0.55 MAX. 6.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.25 C B Document #: 38-05447 Rev. *G 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85150-*D Page 11 of 13 [+] Feedback CY62167EV18 MoBL® Document History Page Document Title: CY62167EV18 MoBL® 16 Mbit (1M x 16) Static RAM Document Number: 38-05447 REV. ECN NO. Orig. of Change Submission date ** 202600 AJU 01/23/2004 *A 463674 NXR See ECN Description of Change New Data Sheet Converted from Advance Information to Preliminary Changed VCC(max) from 2.20V to 2.25V Removed ‘L’ bin and 35 ns speed bin from product offering Changed ball E3 from DNU to NC Removed redundant foot note on DNU Changed the ISB2(typ) value from 1.3 μA to 1.5 μA Changed the ICC(max) value from 40 mA to 25 mA Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns Changed the ICCDR Value from 8 μA to 5 μA Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns Changed tLZOE from 3 ns to 5 ns Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns Changed tSCE, tAW, and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information Updated the Ordering Information table *B 469182 NSI See ECN Minor Change: Moved to external web *C 619122 NXR See ECN Replaced 45 ns speed bin with 55 ns speed bin *D 1130323 VKN See ECN Converted from preliminary to final Added footnote# 8 related ISB2 and ICCDR Changed ISB1 and ISB2 spec from 10 μA to 12 μA Changed ICCDR spec from 8 μA to 10 μA Added footnote# 13 related AC timing parameters Changed tWC spec from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW spec from 35 ns to 40 ns Changed tHZWE spec from 18 ns to 20 ns *E 1388287 VKN See ECN Added 48-Ball VFBGA (6 x 7 x 1mm) package Added footnote# 1 related to FBGA package Updated Ordering Information table *F 1664843 VKN/AESA See ECN Added CY62167EV30LL-45BVI part in the Ordering Information table Added footnote# 5 related to CY62167EV30LL-45BVI part *G 2675375 VKN/PYRS 03/17/2009 Added CY62167EV18LL-55BVI part in the Ordering Information table Document #: 38-05447 Rev. *G Page 12 of 13 [+] Feedback CY62167EV18 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05447 Rev. *G Revised March 13, 2009 Page 13 of 13 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback