CYPRESS CY62157EV18LL

CY62157EV18 MoBL®
8-Mbit (512K x 16) Static RAM
Features
deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are
HIGH). The input and output pins (IO0 through IO15) are
placed in a high impedance state when:
• Very high speed: 55 ns
• Wide voltage range: 1.65V–2.25V
• Deselected (CE1 HIGH or CE2 LOW)
• Pin Compatible with CY62157DV18 and CY62157DV20
• Outputs are disabled (OE HIGH)
• Ultra low standby power
— Typical Standby current: 2 µA
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
— Maximum Standby current: 8 µA
• Write operation is active (CE1 LOW, CE2 HIGH and WE
• Ultra low active power
LOW).
— Typical active current: 1.8 mA @ f = 1 MHz
Write to the device by taking Chip Enables (CE1 LOW and CE2
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power down when deselected
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7), is
written into the location specified on the address pins (A0
through A18). If Byte High Enable (BHE) is LOW, then data
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
from IO pins (IO8 through IO15) is written into the location
specified on the address pins (A0 through A18).
Functional Description [1]
The CY62157EV18 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
Read from the device by taking Chip Enables (CE1 LOW and
CE2 HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW,
then data from memory appears on IO8 to IO15. See the “Truth
Table” on page 9 for a complete description of read and write
modes.
Product Portfolio
Power Dissipation
Speed
(ns)
VCC Range (V)
Product
Operating ICC, (mA)
f = 1MHz
CY62157EV18
Min
Typ [2]
Max
1.65
1.8
2.25
55
f = fmax
Standby, ISB2 (µA)
Typ [2]
Max
Typ [2]
Max
Typ [2]
Max
1.8
3
18
25
2
8
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” located at http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Cypress Semiconductor Corporation
Document #: 38-05490 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 30, 2007
[+] Feedback
CY62157EV18 MoBL®
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
512K x 16
RAM Array
IO0–IO7
IO8–IO15
COLUMN DECODER
A17
A18
A16
A15
A14
A11
A12
A13
BHE
WE
CE2
OE
BLE
CE1
POWER DOWN
CIRCUIT
BHE
CE2
BLE
CE1
Pin Configuration [3]
48-ball VFBGA
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
IO8
BHE
A3
A4
CE1
IO0
B
IO9
IO10
A5
A6
IO1
IO2
C
VSS
IO11
A17
A7
IO3
VCC
D
VCC
IO12
NC
A16
IO4
VSS
E
IO14
IO13
A14
A15
IO5
IO6
F
IO15
NC
A12
A13
WE
IO7
G
A18
A8
A9
A10
A11
NC
H
Note
3. NC pins are not connected on the die.
Document #: 38-05490 Rev. *D
Page 2 of 12
[+] Feedback
CY62157EV18 MoBL®
Maximum Ratings
DC Input Voltage [4, 5] ......... –0.2V to 2.45V (VCCmax + 0.2V)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Output Current into Outputs (LOW) ............................ 20 mA
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Latch-up Current ................................................... > 200 mA
Supply Voltage to Ground
Potential ...............................–0.2V to 2.45V (VCCmax + 0.2V)
Operating Range
Static Discharge Voltage ......................................... > 2001V
(in accordance with MIL-STD-883, Method 3015)
Device
DC Voltage Applied to Outputs
in High-Z State [4, 5] ..............–0.2V to 2.45V (VCCmax + 0.2V)
Range
Ambient
Temperature
VCC [6]
CY62157EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –0.1 mA
VCC = 1.65V
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 1.65V
VIH
Input HIGH Voltage
VCC = 1.65V to 2.25V
VIL
Input LOW Voltage
VCC = 1.65V to 2.25V
IIX
Input Leakage
Current
IOZ
ICC
55 ns
Min
Typ [2]
Unit
Max
1.4
V
0.2
V
1.4
VCC + 0.2V
V
–0.2
0.4
V
GND < VI < VCC
–1
+1
µA
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
µA
VCC Operating Supply
Current
f = fmax = 1/tRC
18
25
mA
1.8
3
mA
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
ISB1
Automatic CEPower Down CE1 > VCC−0.2V or CE2 < 0.2V
Current–CMOS Inputs
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, WE, BHE and BLE), VCC = VCC(max).
2
8
µA
ISB2 [7]
Automatic CE Power Down CE1 > VCC – 0.2V or CE2 < 0.2V,
Current–CMOS Inputs
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max).
2
8
µA
Capacitance [8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.5V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05490 Rev. *D
Page 3 of 12
[+] Feedback
CY62157EV18 MoBL®
Thermal Resistance [8]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
BGA
Unit
72
°C/W
8.86
°C/W
AC Test Loads and Waveforms
VCC
OUTPUT
R1
3V
10%
GND
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
Value
Unit
R1
13500
Ω
R2
10800
Ω
RTH
6000
Ω
VTH
0.80
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR [8]
Chip Deselect to Data Retention Time
tR [9]
Operation Recovery Time
Min
Typ [2]
Max
1.0
V
1
VCC= VDR, CE1 > VCC – 0.2V,
CE2 < 0.2V,VIN > VCC – 0.2V or VIN < 0.2V
Unit
3
µA
0
ns
tRC
ns
Data Retention Waveform [10]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.0V
VCC(min)
tR
CE1 or
BHE.BLE
or
CE2
Notes
9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 38-05490 Rev. *D
Page 4 of 12
[+] Feedback
CY62157EV18 MoBL®
Switching Characteristics (Over the Operating Range) [11, 12]
Parameter
55 ns
Description
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
55
ns
tDOE
OE LOW to Data Valid
25
ns
tLZOE
OE LOW to Low-Z
55
55
10
[13]
OE HIGH to High-Z
tHZOE
ns
ns
5
[13, 14]
ns
ns
18
ns
CE1 LOW and CE2 HIGH to Low-Z
[13]
tHZCE
CE1 HIGH and CE2 LOW to High-Z
[13, 14]
tPU
CE1 LOW and CE2 HIGH to Power Up
tPD
CE1 HIGH and CE2 LOW to Power Down
55
ns
BLE/BHE LOW to Data Valid
55
ns
tLZCE
tDBE
tLZBE
[15]
BLE/BHE LOW to Low-Z
tHZBE
Write Cycle
[13]
BLE/BHE HIGH to High-Z
10
ns
18
0
ns
10
[13, 14]
ns
ns
18
ns
[16]
tWC
Write Cycle Time
45
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE/BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
tLZWE
WE LOW to High-Z
[13, 14]
WE HIGH to Low-Z
[13]
18
10
ns
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further
clarification.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state.
15. If both byte enables are toggled together, this value is 10 ns.
16. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
Document #: 38-05490 Rev. *D
Page 5 of 12
[+] Feedback
CY62157EV18 MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [17, 18]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle 2 (OE Controlled) [18, 19]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes:
17. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05490 Rev. *D
Page 6 of 12
[+] Feedback
CY62157EV18 MoBL®
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled) [16, 20, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
NOTE 22
VALID DATA
tHZOE
Write Cycle 2 (CE1 or CE2 Controlled) [16, 20, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
NOTE 22
tHD
VALID DATA
tHZOE
Notes:
20. Data IO is high impedance if OE = VIH.
21. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
22. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05490 Rev. *D
Page 7 of 12
[+] Feedback
CY62157EV18 MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW) [21]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA IO
NOTE 22
tHD
VALID DATA
tLZWE
tHZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW) [21]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA IO
NOTE 22
Document #: 38-05490 Rev. *D
tHD
VALID DATA
Page 8 of 12
[+] Feedback
CY62157EV18 MoBL®
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
H
H
L
H
L
Inputs/Outputs
Mode
Power
High-Z
Deselect/Power Down
Standby (ISB)
X
High-Z
Deselect/Power Down
Standby (ISB)
H
H
High-Z
Deselect/Power Down
Standby (ISB)
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
H
L
H
L
Data Out (IO0–IO7);
High-Z (IO8–IO15)
Read
Active (ICC)
H
H
L
L
H
High-Z (IO0–IO7);
Data Out (IO8–IO15)
Read
Active (ICC)
L
H
H
H
L
H
High-Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High-Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High-Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (IO0–IO7);
High-Z (IO8–IO15)
Write
Active (ICC)
L
H
L
X
L
H
High-Z (IO0–IO7);
Data In (IO8–IO15)
Write
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
55
CY62157EV18LL-55BVXI
Package
Diagram
Package Type
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts
Document #: 38-05490 Rev. *D
Page 9 of 12
[+] Feedback
CY62157EV18 MoBL®
Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.10 C
0.21±0.05
0.25 C
B
0.15(4X)
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05490 Rev. *D
Page 10 of 12
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY62157EV18 MoBL®
Document History
Document Title: CY62157EV18 MoBL® 8-Mbit (512K x 16) Static RAM
Document Number:38-05490
REV. ECN NO. Issue Date
Orig. of
Change
Description of Change
**
202862
See ECN
AJU
New Data Sheet
*A
291272
See ECN
SYT
Converted from Advance Information to Preliminary
Changed VCC Max from 2.20 to 2.25 V
Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs
Changed ICCDR from 4 to 4.5 µA
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bins
Changed tDOE from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
respectively
Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45
ns Speed Bins respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
respectively
Changed tSCE, tAW, and tBW from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns
Speed Bins respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
respectively
Added Pb-Free Package Information
*B
444306
See ECN
NXR
Converted from Preliminary to Final
Removed 35 ns speed bin
Removed “L” bin
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU
Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2.4V to
2.45V
Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA to 25
mA for test condition f = fax = 1/tRC
Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz
Changed the ISB1 and ISB2 Max value from 4.5 µA to 8 µA and Typ value from 0.9 µA
to 2 µA respectively
Updated Thermal Resistance table
Changed Test Load Capacitance from 50 pF to 30 pF
Added Typ value for ICCDR
Changed the ICCDR Max value from 4.5 µA to 3 µA
Corrected tR in Data Retention Characteristics from 100 µs to tRC ns
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tLZBE from 6 to 5
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Added footnote #13
Updated the ordering Information and replaced the Package Name column with
Package Diagram
*C
571786
See ECN
VKN
Replaced 45ns speed bin with 55ns
Document #: 38-05490 Rev. *D
Page 11 of 12
[+] Feedback
CY62157EV18 MoBL®
Document Title: CY62157EV18 MoBL® 8-Mbit (512K x 16) Static RAM
Document Number:38-05490
REV. ECN NO. Issue Date
*D
908120
See ECN
Document #: 38-05490 Rev. *D
Orig. of
Change
VKN
Description of Change
Added footnote #7 related to ISB2
Added footnote #12 related AC timing parameters
Page 12 of 12
[+] Feedback