CY62148E MoBL® 4-Mbit (512K x 8) Static RAM Functional Description [1] Features • Very high speed: 45 ns The CY62148E is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when: • Voltage range: 4.5V–5.5V • Pin compatible with CY62148B • Ultra low standby power — Typical standby current: 1 µA — Maximum standby current: 7 µA (Industrial) • Ultra low active power — Typical active current: 2.0 mA @ f = 1 MHz • Easy memory expansion with CE, and OE features • Deselected (CE HIGH) • Automatic power down when deselected • Outputs are disabled (OE HIGH) • CMOS for optimum speed and power • Available in Pb-free 32-pin TSOP II and 32-pin SOIC packages • Write operation is active (CE LOW and WE LOW) [2] To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. Product Portfolio Power Dissipation Product Range Speed (ns) VCC Range (V) Operating ICC (mA) f = 1MHz CY62148ELL TSOP II CY62148ELL SOIC Min Typ [3] Max Ind’l 4.5 5.0 5.5 Ind’l/Auto-A 4.5 5.0 5.5 f = fmax Standby ISB2 (µA) Typ [3] Max Typ [3] Max Typ [3] Max 45 2 2.5 15 20 1 7 55 2 2.5 15 20 1 7 Notes 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. 2. SOIC package is available only in 55 ns speed bin. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Cypress Semiconductor Corporation Document #: 38-05442 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 28, 2007 [+] Feedback CY62148E MoBL® Logic Block Diagram IO2 SENSE AMPS ARRAY IO3 IO4 IO5 IO6 IO7 POWER DOWN A18 A17 COLUMN DECODER A15 OE 512K x 8 A16 WE IO1 A13 A14 CE IO0 INPUT BUFFER ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Pin Configuration [2, 4] 32-pin SOIC/TSOP II Pinout Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE IO7 IO6 IO5 IO4 IO3 Note 4. NC pins are not connected on the die. Document #: 38-05442 Rev. *F Page 2 of 10 [+] Feedback CY62148E MoBL® DC Input Voltage [5, 6] ............ –0.5V to 6.0V (VCCmax + 0.5V) Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied............................................ –55°C to + 125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current ......................................................>200mA Operating Range Supply Voltage to Ground Potential .................................–0.5V to 6.0V (VCCmax + 0.5V) DC Voltage Applied to Outputs in High-Z State [5, 6] ................–0.5V to 6.0V (VCCmax + 0.5V) Device CY62148E Range Ambient Temperature VCC [7] Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V Electrical Characteristics (Over the Operating Range) Parameter Description Test Conditions IOH = –1 mA 55 ns [2] 45 ns Min VOH Output HIGH Voltage VOL VIH Output LOW Voltage IOL = 2.1 mA Input HIGH Voltage VCC = 4.5V to 5.5V 2.2 VIL Input LOW voltage –0.5 Typ [3] Max 2.4 Min Typ [3] 2.4 VCC + 0.5 2.2 0.4 V VCC + 0.5 V 0.8 For SOIC package Unit V 0.4 VCC = 4.5V to 5.5V For TSOPII package Max V –0.5 0.6 [8] IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC Operating Supply Current mA ISB2 [9] f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels Automatic CE Power CE > VCC – 0.2V down Current — VIN > VCC – 0.2V or VIN < 0.2V, CMOS Inputs f = 0, VCC = VCC(max) 15 20 15 20 2 2.5 2 2.5 1 7 1 7 µA Capacitance (For All Packages) [10] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Notes 5. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA. 6. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 8. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6V. This is applicable to SOIC package only. Refer to AN13470 for details. 9. Only chip enable (CE) must be HIGH at CMOS level to meet the ISB2 spec. Other inputs can be left floating. 10. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05442 Rev. *F Page 3 of 10 [+] Feedback CY62148E MoBL® Thermal Resistance [10] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions SOIC Package TSOP II Package Unit 75 77 °C/W 10 13 °C/W Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES 3.0V R2 30 pF INCLUDING JIG AND SCOPE 90% 10% GND Rise Time = 1 V/ns Equivalent to: 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT RTH OUTPUT V Parameters 5.0V Unit R1 1800 Ω R2 990 Ω RTH 639 Ω VTH 1.77 V Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [10] Chip Deselect to Data Retention Time tR [11] Operation Recovery Time Min Typ [3] Max 2 Ind’l/Auto-A VCC= VDR, CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Unit V 1 7 µA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 2.0V tCDR VCC(min) tR CE Note 11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document #: 38-05442 Rev. *F Page 4 of 10 [+] Feedback CY62148E MoBL® Switching Characteristics (Over the Operating Range) [12] Parameter Description 55 ns [2] 45 ns Min Max Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 55 ns tDOE OE LOW to Data Valid 22 25 ns tLZOE OE LOW to LOW Z [13] tHZOE OE HIGH to High Z [13, 14] tLZCE CE LOW to Low Z [13] tHZCE CE HIGH to High Z [13, 14] tPU CE LOW to Power up tPD Write Cycle 45 55 45 10 55 10 5 10 ns 20 10 18 0 ns ns 20 0 45 ns ns 5 18 CE HIGH to Power down ns ns ns 55 ns [15] tWC Write Cycle Time 45 55 ns tSCE CE LOW to Write End 35 40 ns tAW Address Setup to Write End 35 40 ns tHA Address Hold from Write End 0 0 ns tSA Address Setup to Write Start 0 0 ns tPWE WE Pulse Width 35 40 ns tSD Data Setup to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High-Z [13, 14] tLZWE WE HIGH to Low-Z [13] 18 10 20 10 ns ns Notes 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05442 Rev. *F Page 5 of 10 [+] Feedback CY62148E MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [16, 17] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [17, 18] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA IO NOTE 21 tHD DATA VALID tHZOE Notes: 16. Device is continuously selected. OE, CE = VIL. 17. WE is HIGH for read cycles. 18. Address valid before or similar to CE transition LOW. 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 21. During this period, the IOs are in output state and input signals must not be applied. Document #: 38-05442 Rev. *F Page 6 of 10 [+] Feedback CY62148E MoBL® Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [19, 20] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Write Cycle No. 3 (WE Controlled, OE LOW) [20] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 21 DATA IO tHD DATA VALID tLZWE tHZWE Truth Table CE WE OE H X X High Z Deselect/Power down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05442 Rev. *F IO’s Mode Power Page 7 of 10 [+] Feedback CY62148E MoBL® Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 45 CY62148ELL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free) Industrial 55 CY62148ELL-55SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Industrial 55 CY62148ELL-55SXA 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Automotive-A Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 1. 32-pin TSOP II, 51-85095 51-85095-** Document #: 38-05442 Rev. *F Page 8 of 10 [+] Feedback CY62148E MoBL® Package Diagrams (continued) Figure 2. 32-pin (450 MIL) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] SEATING PLANE 51-85081-*B MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05442 Rev. *F Page 9 of 10 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62148E MoBL® Document History Page Document Title: CY62148E MoBL®, 4-Mbit (512K x 8) Static RAM Document Number: 38-05442 REV. ECN NO. Issue Date Orig. of Change ** 201580 01/08/04 AJU New Data Sheet *A 249276 See ECN SYT Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Added RTSOP II and Removed FBGA Package Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs Changed ICCDR from 2.0 µA to 2.5 µA Changed typo in Data Retention Characteristics(tR) from 100 µs to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Corrected typo in Package Name Changed Ordering Information to include Pb-Free Packages *B 414820 See ECN ZSD Changed from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35ns Speed Bin Removed “L” version of CY62148E Changed ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Max) value from 2 mA to 2.5 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f=fmax Removed ISB1 spec from the Electrical characteristics table Changed ISB2 Typ values from 0.7 µA to 1 µA and Max values from 2.5 µA to 7 µA Modified footnote #4 to include current limit Removed redundant footnote on DNU pins Changed the AC testload capacitance from 100 pF to 30 pF on page #4 Changed test load parameters R1, R2, RTH and VTH from 1838 Ω, 994 Ω, 645 Ω and 1.75V to 1800 Ω, 990 Ω, 639 Ω and 1.77V Changed ICCDR from 2.5 µA to 7 µA Added ICCDR typical value Changed tLZOE from 3 ns to 5 ns Changed tLZCE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns Changed tSD from 22 ns to 25 ns Updated the ordering information table and replaced Package Name column with Package Diagram *C 464503 See ECN NXR Included Automotive Range in product offering Updated the Ordering Information *D 485639 See ECN VKN Corrected the operating range to 4.5V - 5.5V on page# 3 *E 833080 See ECN VKN Added footnote #8 Added VILspec for SOIC package *F 890962 See ECN VKN Added Automotive-A part and its related information Removed Automotive-E part and its related information Added footnote #2 related to SOIC package Added footnote #9 related to ISB2 Added AC values for 55 ns Industrial-SOIC range Updated Ordering Information table Document #: 38-05442 Rev. *F Description of Change Page 10 of 10 [+] Feedback