19-2935; Rev 0; 7/03 10Gbps EAM Driver with Integrated Bias Network Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ On-Chip Bias Network 23ps Edge Speed Programmable Modulation Voltage Up to 3VP-P Programmable EAM Biasing Voltage Up to 1.25V Selectable Data-Retiming Latch Up to 10.7Gbps Operation Integrated Modulation and Biasing Functions 50Ω On-Chip Input and Output Terminations Pulse-Width Adjustment Enable and Polarity Controls ESD Protection Ordering Information PART TEMP RANGE PIN-PACKAGE MAX3941ETG -40°C to +85°C 24-Thin QFN (4mm x 4mm) Applications SONET OC-192 and SDH STM-64 Transmission Systems DWDM Systems Long/Short-Reach Optical Transmitters 10Gbps Ethernet Typical Application Circuit -5.2V PLRT MODEN 0.01µF 50Ω DATA+ RTEN GND DATA+ EAM 0.01µF MAX3952 DATA- 10Gbps SERIALIZER 50Ω DATA- 50Ω CLK+ 50Ω CLK- MAX3941 0.01µF CLK+ OUT 50Ω 0.01µF CLK- PWC+ PWC2kΩ REPRESENTS A CONTROLLED-5.2V IMPEDANCE TRANSMISSION LINE. MODSET BIASSET + VMODSET - + VBIASSET - VEE -5.2V 330pF 0.1µF -5.2V ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3941 General Description The MAX3941 is designed to drive an electro-absorption modulator (EAM) at data rates up to 10.7Gbps. It incorporates the functions of a biasing circuit and a modulation circuit, with integrated control op amps externally programmed by DC voltages. The integrated bias circuit provides a programmable biasing current up to 50mA. This bias current reflects a bias voltage of up to 1.25V on an external 50Ω load. The bias and modulation circuits are internally connected on chip, eliminating the need for an external bias inductor. A high-bandwidth, fully differential signal path is internally implemented to minimize jitter accumulation. When a clock signal is available, the integrated data-retiming function can be selected to reject input-signal jitter. The MAX3941 receives differential CML signals (ground referenced) with on-chip line terminations of 50Ω. The output has a 50Ω resistor for back termination and is able to deliver a modulation current of 40mA P-P to 120mAP-P, with an edge speed of 23ps (20% to 80% typ). This modulation current reflects an EAM modulation voltage of 1.0VP-P to 3.0VP-P. The MAX3941 also includes an adjustable pulse-width control circuit to precompensate for asymmetrical EAM characteristics. It is available in a compact 4mm x 4mm, 24-pin thin QFN package and operates over the -40°C to +85°C temperature range. MAX3941 10Gbps EAM Driver with Integrated Bias Network ABSOLUTE MAXIMUM RATINGS Supply Voltage VEE ..............................................-6.0V to +0.5V Voltage at MODEN, RTEN, PLRT, MODSET, BIASSET ...........(VEE - 0.5V) to +0.5V Voltage at DATA+, DATA-, CLK+, and CLK-……-1.65V to +0.5V Voltage at OUT .............................................……….-4V to +0.5V Voltage at PWC+, PWC- ...................(VEE - 0.5V) to (VEE + 1.7V) Current Into or Out of OUT.............................……………...80mA Continuous Power Dissipation (TA = +85°C) 24-Lead Thin QFN (derate 20.8mW/°C above +85°C) .............................1354mW Storage Temperature Range .....................……-55°C to +150°C Operating Temperature Range ....................……-40°C to +85°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, and TA = +25°C, unless otherwise noted.) PARAMETER Power-Supply Voltage Supply Current Power-Supply Noise Rejection SYMBOL CONDITIONS VEE IEE PSNR MIN TYP -5.5 Excluding IBIAS and IMOD (Note 1) MAX UNITS -4.9 V Retime disabled 124 174 Retime enabled 140 201 f ≤ 2MHz (Note 2) mA 15 dB 10.7 Gbps SIGNAL INPUT (Note 3) Input Data Rates Single-Ended Input Resistance NRZ RIN Single-Ended Input Voltage VIS Differential Input Voltage VID Differential Input Return Loss RLIN Input to GND 42.5 50 58.5 DC-coupled, Figure 1a -1 0 AC-coupled, Figure 1b -0.4 +0.4 DC-coupled (Note 4) 0.2 2.0 AC-coupled (Note 4) 0.2 1.6 ≤15GHz 15 Ω V VP-P dB EAM BIAS Maximum Bias Current VBIASSET = VEE + 2V Minimum Bias Current VBIASSET = VEE BIASSET Voltage Range VBIASSET Equivalent Bias Resistance RBSEQV Bias-Current-Setting Accuracy VEE (Note 6) mA 1.2 VEE + 2 VBIASSET = VEE + 0.11V 2.1 4.3 VBIASSET = VEE + 0.36V 8.8 11.3 VBIASSET = VEE + 2.0V 52 58.4 VBIASSET < VEE + 0.36V -1100 +1100 VBIASSET ≥ VEE + 0.36V -480 +480 50Ω driver load, VBIASSET = VEE + 0.55V, Figure 2 mA V Ω 36.4 BIASSET Input Resistance BIASSET Bandwidth 56 0.3 (Note 5) TA = +25°C Bias-Current Temperature Stability 50 mA ppm/°C 20 kΩ 5 MHz EAM MODULATION Maximum Modulation Current 112 Minimum Modulation Current VMODSET = VEE MODSET Voltage Range VMODSET Equivalent Modulation Resistance RMODEQV 2 120 37 VEE (Note 7) mAP-P 40 VEE + 1 11.1 _______________________________________________________________________________________ mAP-P V Ω 10Gbps EAM Driver with Integrated Bias Network (VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Modulation depth 10%, 50Ω driver load, Figure 2 Modulation Set Bandwidth MODSET Input Resistance Modulation-Current Temperature Stability (Note 6) Modulation-Current-Setting Error Output Resistance ROUT TYP -10 OUT to GND 42.5 MHz 20 kΩ 50 BIASSET = VEE, MODEN = VEE, MODSET = VEE, DATA+ = high, DATA- = low Total Off Current Output Return Loss RLOUT IBIAS = 30mA, IMOD = 50mA tSU, tHD Figure 3 (Note 6) Output Edge Speed Setup/Hold Time (Notes 6, 8) Pulse-Width Control Input Range (Single Ended) For PWC+ and PWC- Pulse-Width Control Input Range (Differential) (PWC+) - (PWC-) δ 0 ppm/°C +10 % 58.5 Ω 1.2 mA 10 20% to 80% (Notes 6, 8) Pulse-Width Adjustment Range Output Overshoot ≤15GHz 23 dB 32 25 ±30 UNITS 5 -957 50Ω driver load, TA = +25°C MAX ps ps ±50 ps VEE + 0.5 VEE + 1.5 V -0.5 +0.5 V (Notes 6, 8) 10 % Driver Random Jitter RJDR (Note 6) 0.3 0.7 psRMS Driver Deterministic Jitter DJDR PWC- = GND (Notes 6, 9) 6.8 11 psP-P CONTROL INPUTS Input High Voltage VIH (Note 10) Input Low Voltage VIL (Note 10) Input Current (Note 10) VEE + 2.0 -80 V VEE + 0.8 V +200 µA Note 1: Supply current remains elevated once the retiming function is enabled. Power must be cycled to reduce supply current after the retiming function is disabled. Note 2: Power-supply noise rejection is specified as PSNR = 20log(Vnoise (on Vcc) / ∆VOUT). VOUT is the voltage across a 50Ω load. Vnoise (on Vcc) = 100mVP-P. Note 3: For DATA+, DATA-, CLK+, and CLK-. Note 4: CLK input characterized at 10.7Gbps. Note 5: RBSEQV = (VBIASSET - VEE) / IBIAS with MODEN = VEE, DATA+ = high, and DATA- = low. Note 6: Guaranteed by design and characterization using the circuit shown in Figure 4. Note 7: RMODEQV = (VMODSET - VEE) / (IMOD - 37mA) with BIASSET = VEE. Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern. Note 9: Deterministic jitter is defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ). Measured with a 10.7Gbps 27 - 1 PRBS pattern with eighty 0s and eighty 1s inserted in the data pattern. Note 10: For MODEN and PLRT. _______________________________________________________________________________________ 3 MAX3941 ELECTRICAL CHARACTERISTICS (continued) 10Gbps EAM Driver with Integrated Bias Network MAX3941 Test Circuits and Timing Diagrams 0V 100mV 1.0V -0.5V -1.0V (a) DC-COUPLED SINGLE-ENDED CML INPUT 0.4V 800mV 0V -0.4V 100mV (b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT Figure 1. Definition of Single-Ended Input Voltage Range 0V 0V VOUT VOUT VBIASSET (a) MODULATING BIASSET (c) RESULT OF MODULATING BIASSET AND MODSET 180° OUT OF PHASE 0V VOUT mW VMODSET (b) MODULATING MODSET POUT (d) RESULTING OPTICAL OUTPUT NOTE: ALL AMPLITUDES ARE RELATIVE. Figure 2. Modulating BIASSET and MODSET Pins 4 _______________________________________________________________________________________ 10Gbps EAM Driver with Integrated Bias Network CLK+ CLK- tSU VIS = 0.1VP-P TO 1VP-P DC-COUPLED 0.1VP-P TO 0.8VP-P AC-COUPLED tHD DATA- VIS DATA+ (DATA+) (DATA-) VID = 0.2VP-P TO 2VP-P DC-COUPLED 0.2VP-P TO 1.6VP-P AC-COUPLED IOUT IMOD = 40mAP-P TO 120mAP-P IBIAS = 0mA TO 50mA NOTE: IOUT RELATES TO RETIMED DATA. Figure 3. Setup and Hold Timing Definition GND RTEN PWC+ PWC50Ω GND GND1 GND2 ROUT 50Ω 50Ω IOUT OUT 50Ω 50Ω 50Ω 50Ω CLKD Q 50Ω 1 DATA- VEE -5.2V 0.1µF 0 DATA+ 50Ω 300pF 50Ω P W C CLK+ PATTERN GENERATOR 50Ω OSCILLOSCOPE 50Ω 50Ω ZL M U X IMOD IBIAS VEE VEE MODSET BIASSET VMODSET VBIASSET VEE VEE Figure 4. AC-Characterization Circuit _______________________________________________________________________________________ 5 MAX3941 Test Circuits and Timing Diagrams (continued) 10Gbps EAM Driver with Integrated Bias Network MAX3941 Test Circuits and Timing Diagrams (continued) VOLTAGE GND VBIAS VMOD VOUT USABLE RANGE VEE + 1.9V BELOW USABLE RANGE Figure 5. Bias and Modulation Relationship to EAM Voltage Typical Operating Characteristics (Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, TA = +25°C, unless otherwise noted.) MAX3941 toc02 MAX3941 toc01 NOTE: BIAS AND MODULATION 1 SET AT OPTIMUM LEVELS FOR EAM. 2 3 15ps/div 20ps/div 20ps/div PULSE WIDTH vs. RPWC RPWC- (Ω) 2000 1750 1500 1250 1000 750 500 250 160 150 IEE (mA) RETIMING ENABLED 140 130 120 RETIMING DISABLED 110 MEASURED AT 1.25Gbps WITH A 1010 PATTERN 840 830 0 820 810 800 790 780 770 760 100 750 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 6 850 PULSE-WIDTH POSITIVE PULSE (ps) MAX3941 toc04 170 MAX3941 toc05 SUPPLY CURRENT vs. TEMPERATURE (50Ω LOAD, EXCLUDES IBIAS, IMOD) 0 250 500 750 1000 1250 1500 1750 2000 RPWC+ (Ω) _______________________________________________________________________________________ MAX3941 toc03 OC-192 OPTICAL EYE DIAGRAM (OC-192 FILTER, 231 - 1 PRBS) 10Gbps ELECTRICAL EYE DIAGRAM (VMOD = 3VP-P, 231 - 1 PRBS) 10Gbps ELECTRICAL EYE DIAGRAM (VMOD = 1VP-P, 231 - 1 PRBS) 10Gbps EAM Driver with Integrated Bias Network PULSE-WIDTH DISTORTION vs. TEMPERATURE VMOD vs. VMODSET (ZL = 50Ω) 4.0 MAX3941 toc07 4.5 VMODSET IS RELATIVE TO VEE. 3.0 2.5 3.5 VMOD (VP-P) 3.0 2.5 2.0 1.5 2.0 1.5 1.0 1.0 0.5 0.5 0 0 -50 -30 -10 10 30 50 70 90 0 0.25 0.50 0.75 TEMPERATURE (°C) VMODSET (V) VBIAS vs. VBIASSET (ZL = 50Ω) POWER-SUPPLY NOISE REJECTION vs. FREQUENCY 30 MAX3941 toc08 0 VBIASSET IS RELATIVE TO VEE -0.2 1.00 MAX3941 toc09 PULSE-WIDTH DISTORTION (ps) 3.5 MAX3941 toc06 5.0 25 20 -0.6 PSNR (dB) VBIAS (V) -0.4 -0.8 -1.0 15 10 -1.2 5 -1.4 -1.6 0.5 1.0 1.5 2.0 0 2.5 1 100 10 FREQUENCY (Hz) DIFFERENTIAL S11 vs. FREQUENCY (DEVICE POWERED) S22 vs. FREQUENCY (DEVICE POWERED) 0 MAX3941 toc10 0 -5 10k 1k VBIASSET (V) MAX3941 toc11 0 -4 -8 -10 -15 |S22| (dB) S11 (dB) -12 -20 -16 -20 -24 -25 -28 -30 -32 -35 -36 -40 -40 0 3 6 9 FREQUENCY (GHz) 12 15 0 3 6 9 12 15 FREQUENCY (GHz) _______________________________________________________________________________________ 7 MAX3941 Typical Operating Characteristics (continued) (Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, TA = +25°C, unless otherwise noted.) 10Gbps EAM Driver with Integrated Bias Network MAX3941 Pin Description PIN NAME FUNCTION 1 DATA+ Noninverting Data Input with 50Ω On-Chip Termination 2 DATA- Inverting Data Input with 50Ω On-Chip Termination 3, 4, 14 GND Ground. All pins must be connected to board ground. 5 CLK+ Noninverting Clock Input for Data Retiming with 50Ω On-Chip Termination 6 CLK- Inverting Clock Input for Data Retiming with 50Ω On-Chip Termination 7, 11, 12, 13, 18, 19, 24 VEE 8 PWC+ Positive Input for Modulation Pulse-Width Adjustment (See the Design Procedure Section) 9 PWC- Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width adjustment feature (see the Design Procedure section). 10 MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output. 15 GND1 16 OUT 17 GND2 Ground. Ground connection. 20 PLRT Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the differential signal polarity. Contains an internal 100kΩ pullup to GND. 21 BIASSET Bias Current Set. Apply a voltage to set the bias current of the driver output. 22 MODEN TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to VEE. 23 RTEN Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch. EP Exposed Pad Negative Supply Voltage. All pins must be connected to board VEE. Ground. Ground connection. Driver Output. Provides both modulation and bias output. DC-couple to EAM. Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance (see the Exposed Pad Package section). Detailed Description The MAX3941 EAM driver consists of two main parts: a high-speed modulation driver and an EAM-biasing block. The clock and data inputs to the driver are compatible with PECL and CML logic levels. The modulation and bias currents are output through the OUT pin. The modulation output stage is composed of a highspeed differential pair and a programmable current source with a maximum modulation current of 120mA. The rise and fall times are typically 23ps. The modulation current is designed to produce an EAM voltage up to 3.0VP-P when driving a 50Ω module. The 3.0VP-P results from 120mAP-P through the parallel combination of the 50Ω EAM load and the internal 50Ω back termination. 8 Polarity Switch The MAX3941 includes a polarity switch. When the PLRT pin is high or left floating, the output maintains the polarity of the input data. When the PLRT pin is low, the output is inverted relative to the input data. Clock/Data Input Logic Levels The MAX3941 is directly compatible with ground-reference CML. Either DC- or AC-coupling can be used for CML referenced to ground. For all other logic types, AC-coupling should be used. Optional Data Input Latch To reject pattern-dependent jitter in the input data, a synchronous differential clock signal should be connected to the CLK+ and CLK- inputs, and the RTEN control input should be connected to VEE. _______________________________________________________________________________________ 10Gbps EAM Driver with Integrated Bias Network (ZL) in parallel with the internal 50Ω termination resistor (ROUT): Pulse-Width Control To program the desired bias current, force a voltage at the BIASSET pin (see the Typical Application Circuit). The resulting IBIAS current can be calculated by the following equation: The pulse-width control circuit can be used to compensate for pulse-width distortion introduced by the EAM. The differential voltage between PWC+ and PWCadjusts the pulse-width compensation. The adjustment range is typically ±50ps. Optional single-ended operation is possible by forcing a voltage on the PWC+ pin while leaving the PWC- pin unconnected. When PWCis connected to ground, the pulse-width control circuit is automatically disabled. Modulation Output Enable The MAX3941 incorporates a modulation currentenable input. When MODEN is low or floating, the modulation/bias output (OUT) is enabled. When MODEN is high, the output is switched to the logic 0 state. The typical enable time is 2ns and the typical disable time is 2ns. Design Procedure Programming the Modulation Voltage The EAM modulation voltage results from IMOD passing through the EAM impedance (ZL) in parallel with the internal 50Ω termination resistor (ROUT): VMOD ≈ IMOD × ZL × ROUT ZL + ROUT To program the desired modulation current, force a voltage at the MODSET pin (see the Typical Application Circuit). The resulting IMOD current can be calculated by the following equation: IMOD ≈ VMODSET + 37mA 11.1Ω An internal, independent current source drives a constant 37mA to the modulation circuitry, and any voltage above VEE on the MODSET pin adds to this. The input impedance of the MODSET pin is typically 20kΩ. Note that the minimum output voltage is VEE + 1.9V (Figure 5). Programming the Bias Voltage As in the case of modulation, the EAM bias voltage results from IBIAS passing through the EAM impedance VBIAS ≈ IBIAS × ZL × ROUT ZL + ROUT VBIASSET 36.4Ω IBIAS ≈ The input impedance of the BIASSET pin is typically 20kΩ. Note that the minimum output voltage is VEE + 1.9V (Figure 5). Programming the Pulse-Width Control Three methods of control are possible when pulse predistortion is desired to minimize distortion at the receiver. The pulse width can be set with a 2kΩ potentiometer with the center tapped to VEE (or equivalent fixed resistors), by applying a voltage to the PWC+ pin, or by applying a differential voltage across the PWC+ and PWC- pins. See Table 1 for the desired effect of the pulse-width setting. Pulse width is defined as (positive pulse width)/((positive pulse width + negative pulse width)/2). Input Termination Requirement The MAX3941 data and clock inputs are CML compatible. However, it is not necessary to drive the IC with a standard CML signal. As long as the specified input voltage swings are met, the MAX3941 operates properly. Applications Information Layout Considerations To minimize loss and crosstalk, keep the connections between the MAX3941 output and the EAM module as short as possible. Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Circuit boards should be made using low-loss dielectrics. Use controlled-impedance lines for the clock and data inputs as well as for the data output. Be sure to filter the power supply with capacitors placed close to the IC. Table 1. Pulse-Width Control RPWC+ = RPWC- VPWC+ (PWC- OPEN) (V) VEE + 1 VPWC+ VPWC(V) 0 >100 RPWC+ > RPWC- > VEE + 1 >0 <100 RPWC+ < RPWC- < VEE + 1 <0 PULSEWIDTH (%) 100 RPWC+, RPWC- FOR RPWC+ + RPWC- = 2kΩ _______________________________________________________________________________________ 9 MAX3941 The input data is retimed on the rising edge of CLK+. If RTEN is connected to ground, the retiming function is disabled and the input data is directly connected to the output stage. Leave CLK+ and CLK- open when retiming is disabled. MAX3941 10Gbps EAM Driver with Integrated Bias Network RTEN MODEN PLRT GND GND1 GND2 50Ω 50Ω 50Ω ROUT 50Ω 50Ω 50Ω OUT CLK+ VEE CLK- D Q ZL 0 POLARITY MUX PWC DATA+ 1 IMOD DATA50Ω IBIAS 50Ω MAX3941 VEE PWC+ PWC- 2kΩ VEE MODSET BIASSET + + VMODSET - VBIASSET - VEE VEE VEE Figure 6. Functional Diagram Interface Schematics Laser Safety and IEC 825 Figures 7 and 8 show simplified input and output circuits of the MAX3941 EAM driver. Using the MAX3941 EAM driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each customer must determine the level of fault tolerance required by their application, recognizing that Maxim products are not designed or authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application where the failure of a Maxim product could create a situation where personal injury or death may occur. Exposed-Pad Package The exposed pad on the 24-pin QFN provides a very low thermal-resistance path for heat removal from the IC. The pad is also electrically ground on the MAX3941 and must be soldered to the circuit board for proper thermal and electrical performance. Refer to Maxim Application Note HFAN-08.1: Thermal Considerations for QFN and Other Exposed-Pad Packages for additional Information. 10 ______________________________________________________________________________________ 10Gbps EAM Driver with Integrated Bias Network GND1 50Ω GND2 MAX3941 50Ω MAX3941 50Ω 50Ω DATA+/CLK+ GND 50Ω GND OUT DATA-/CLKVEE VEE Figure 8. Simplified Output Circuit Figure 7. Simplified Input Circuit Pin Configuration VEE RTEN MODEN BIASSET PLRT VEE 24 23 22 21 20 19 TOP VIEW Package Information For the latest package outline information, go to www.maximic.com/packages. PART PACKAGE TYPE PACKAGE CODE MAX3941ETG 24-Thin QFN 4mm x 4mm x 0.8mm T2444-1 DATA+ 1 18 VEE DATA- 2 17 GND2 GND 3 16 OUT 15 GND1 TRANSISTOR COUNT: 1918 PROCESS: SiGe Bipolar MAX3941 12 VEE 11 VEE VEE 13 10 6 MODSET CLK- 9 GND PWC- 14 8 5 PWC+ CLK+ 7 4 VEE. GND Chip Information THIN QFN (4mm x 4mm) EXPOSED PAD CONNECTED TO GROUND Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3941 GND