MAXIM MAX3935E/D

19-4803; Rev 1; 12/02
10.7Gbps EAM Driver
The MAX3935 is designed to drive an electro-absorption modulator (EAM) at data rates up to 10.7Gbps. It
provides programmable output levels through externally adjustable bias and modulation currents. This EAM
driver is fabricated with Maxim’s in-house second-generation SiGe process.
The MAX3935 accepts differential ECL or ground-referenced CML clock and data-input signals. Inputs are
terminated with on-chip 50Ω resistors. An input-data
retiming latch can be used to reject input-patterndependent jitter if a clock signal is available.
The driver can modulate EAM devices at amplitudes up
to 3.0VP-P when the device impedance is 50Ω. Typical
(20% to 80%) edge speeds are 34ps. The output has
an on-chip 75Ω resistor for back termination. The
MAX3935 allows for an EAM bias voltage up to 1.2V.
The MAX3935 also includes an adjustable pulse-width
control circuit to precompensate for asymmetrical EAM
characteristics.
Applications
SONET OC-192 and SDH STM-64
Transmission Systems
Features
♦ Single -5.2V Power Supply
♦ Low 110mA Supply Current
♦ 34ps Typical Rise/Fall Time
♦
♦
♦
♦
♦
♦
Up to 10.7Gbps (NRZ) Operation
On-Chip Termination Resistors
Programmable Modulation Voltage Up to 3.0VP-P
Programmable EAM Bias Voltage Up to 1.2V
Adjustable Pulse-Width Control
Selectable Data Retiming Latch
♦ Modulation Enable Control
♦ ESD Protection
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3935EGJ
-40°C to +85°C
32 QFN-EP*
MAX3935E/D
-40°C to +85°C
Dice**
*EP = exposed pad.
**Dice are designed to operate over this range, but are tested and
guaranteed at TA = +25°C only. Contact factory for availability.
DWDM
For the latest package outline information, go to
www.maxim-ic.com/packages.
Metro and Long-Haul Transmitters
Pin Configuration appears at end of data sheet
Add/Drop Multiplexers
Typical Application Circuit
VBIASREF
-5.2V
-5.2V
BIASSET
BIASMON
DATA+
50Ω
DATA+
DATA-
50Ω
DATA-
EAM
GND
50Ω
MODN1
50Ω
MOD
MAX3935
MAX3952
VTT
VOUT
MODN2
10Gbps SERIALIZER
CLK+
50Ω
CLK+
CLK-
50Ω
CLK-
BIAS
PWC+
L
100pF
PWC- MODEN RTEN MODMON MODSET VEE
RPWC
2kΩ
-5.2V
100Ω -5.2V
-5.2V
-5.2V
VMODREF
-5.2V
REPRESENTS A CONTROLLED–IMPEDANCE TRANSMISSION LINE
-5.2V
†Covered by U.S. patent number 5,883,910.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3935†
General Description
MAX3935†
10.7Gbps EAM Driver
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VEE ...............................................-6.0V to +0.5V
VTT...........................................................(VEE - 0.5V) to +0.5V
DATA+, DATA- and CLK+, CLK- .......(VTT - 1.2V) to the lower of
(VTT + 1.2V) or +0.5V
MODEN, RTEN, PWC+, and PWC- .............(VEE - 0.5V) to +0.5V
MODSET and BIASSET Voltage .......(VEE - 0.5V) to (VEE + 1.5V)
MOD and BIAS Voltage .............................(VEE + 1.0V) to +0.5V
MODN1 and MODN2 Voltage ...............................-0.5V to +0.5V
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Current into DATA+, DATA-, CLK+, CLK(VTT = 0V)....................................................-24mA to +30.5mA
Current into DATA+, DATA-, CLK+, CLK(VTT = -1.3V) ..................................................-24mA to +24mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VEE = -4.9V to -5.5V ±6%, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 16.7mA, IMOD = 83.3mA, TA = +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Power-Supply Voltage
VEE
Power-Supply Current
IEE
Single-Ended Input Resistance
Bias Current-Setting Range
IBIAS
Bias Current-Setting Error
Bias Sensing Resistor
CONDITIONS
MIN
TYP
MAX
UNITS
-5.5
-5.2
-4.9
V
106
140
mA
50
60
Ω
40
mA
+10
%
8.3
Ω
Excluding bias and modulation current
Input to VTT
40
IBIAS defined in Figure 3
1
Bias current = 40mA, TA = +25°C
RBIAS
-10
6.7
Bias Current Temperature
Stability
IBIAS = 40mA (Note 2)
Bias Off-Current
BIASSET ≤ (VEE + 0.4V)
-480
IBIAS = 1mA
MODEN and RTEN Input High
VIH
MODEN and RTEN Input Low
VIL
Power-Supply Rejection Ratio
PSRR
7.5
+480
-200
0.05
VEE +
2.0
mA
V
VEE +
0.8
f ≤ 10MHz, 100mVP-P (Note 8)
ppm/°C
50
V
dB
SIGNAL INPUT FOR VTT = 0
Single-Ended Input
(DC-Coupled)
VIS
Single-Ended Input
(AC-Coupled)
VIS
2
At high
At low
0
-1.00
-0.15
At high
0.075
0.400
At low
-0.400
-0.075
_______________________________________________________________________________________
V
V
10.7Gbps EAM Driver
(VEE = -4.9V to -5.5V ±6%, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 16.7mA, IMOD = 83.3mA, TA = +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Differential Input Swing
(DC-Coupled)
VID
Differential Input Swing
(AC-Coupled)
VID
CONDITIONS
MIN
TYP
MAX
UNITS
0.3
2.0
VP-P
0.3
1.6
VP-P
SIGNAL INPUT FOR VTT = -1.3V
Input Common Mode
VICM
Single-Ended Input
VIS
Differential Input Swing
VID
-1.3
V
At high
-1.225
-0.800
At low
-1.800
-1.375
0.3
2.0
V
VP-P
AC ELECTRICAL CHARACTERISTICS
(VEE = -4.9V to -5.5V ±6%, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 16.7mA, IMOD = 83.3mA, TA = +25°C,
unless otherwise noted.) (Notes 1, 4, 5)
PARAMETER
SYMBOL
Input Data Rates
CONDITIONS
MIN
NRZ (Note 2)
Input Return Loss
RLIN
f ≤ 15GHz (Notes 2, 6)
Modulation Current-Setting
Range
IMOD
IMOD defined in Figure 3 (Note 7)
20
TA = +25°C (Note 9)
-10
Modulation Current-Setting Error
Modulation Sensing Resistor
RMOD
2.7
Modulation Current Temperature
Stability
IMOD = 100mA (Note 2)
Modulation Off-Current
MODSET ≤ (VEE + 0.4V)
Output Edge Speed
Setup/Hold-Time
tR , t F
ZL = 50Ω, 20% to 80% (Note 3)
Figure 2 (Notes 2, 3)
Pulse-Width Adjustment Range
ZL = 50Ω, at 10Gbps (Notes 2, 3)
Pulse-Width Stability
PWC+ and PWC- open (Notes 2, 3)
Pulse-Width Control Input
Range
For PWC+ and PWC-
15
dB
3.0
100
mA
+10
%
3.3
Ω
+550
75.0
ppm/°C
0.1
mA
86.3
Ω
34
ps
25
ps
±60
-6
VEE
UNITS
Gbps
-200
63.8
tSU, tHD
MAX
10.7
-550
IMOD = 20mA
Output Back Termination
Resistor
TYP
VEE +
1.0
ps
+6
ps
VEE +
2.0
V
_______________________________________________________________________________________
3
MAX3935†
DC ELECTRICAL CHARACTERISTICS (continued)
AC ELECTRICAL CHARACTERISTICS (continued)
(VEE = -4.9V to -5.5V ±6%, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 16.7mA, IMOD = 83.3mA, TA = +25°C,
unless otherwise noted.) (Notes 1, 4, 5)
PARAMETER
SYMBOL
Output Overshoot/Undershoot
δ
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 3)
1
%
Driver Random Jitter
(Note 3)
0.75
psRMS
Driver Deterministic Jitter
(Note 5)
11
psP-P
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Specifications at -40°C are guaranteed by design and characterization.
Guaranteed by design and characterization.
Measured using a 10.7Gbps repeating 0000 0000 1111 1111 pattern.
AC characterization performed using the circuit in Figure 1.
Measured using a 10.7Gbps 213 -1 PRBS with eighty zeros + eighty ones input data pattern.
For both data inputs (DATA+, DATA-) and clock inputs (CLK+, CLK-).
Load impedance is 50Ω in parallel with an internal 75Ω termination.
PSRR = 20 × log10 (VNOISE (ON VCC)/(∆IMOD ✕ 30Ω)). Excludes the effect of the external op amp.
For 40mA ≤ IMOD ≤ 100mA.
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
ELECTRICAL EYE DIAGRAM
(IMOD = 100mA, 213 - 1 +80CID)
14ps/div
4
MAX3935 toc02
ELECTRICAL EYE DIAGRAM
(IMOD = 20mA, 213 - 1 +80CID)
13ps/div
MAX3935 toc03
OPTICAL EYE DIAGRAM
(IMOD = 100mA, 213 - 1 +80CID)
MAX3935 toc01
MAX3935†
10.7Gbps EAM Driver
13ps/div
_______________________________________________________________________________________
10.7Gbps EAM Driver
PULSE-WIDTH DISTORTION
vs. TEMPERATURE
120
110
100
90
80
70
MAX3935 toc05
2.0
60
100mA
PERCENT OF UNITS (%)
SUPPLY CURRENT (mA)
130
20mA
PULSE-WIDTH DISTORTION (ps)
140
TYPICAL DISTRIBUTION OF RISE TIME
2.5
MAX3935 toc04
150
MAX3935 toc06
SUPPLY CURRENT (IEE) vs. TEMPERATURE
(EXCLUDES BIAS AND MODULATION CURRENTS)
1.5
1.0
0.5
50
40
30
20
10
60
0
0
50
-40
-20
0
20
40
60
-40
80
-20
0
20
40
60
80
32
33
34
TEMPERATURE (°C)
TEMPERATURE (°C)
35
36
37
38
RISE TIME (ps)
PULSE WIDTH vs. RPWC
0
30
20
10
790
770
750
730
710
3.0
2.5
2.0
1.5
1.0
0.5
690
34
35
36
37
0
38
400
800
1200
1600
0
2000
0
RPWC+ (Ω)
FALL TIME (ps)
1.4
1.2
0.05
0.10
0.15
0.20
0.25
0.30
VMODREF (V)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
BIAS VOLTAGE (50Ω) LOAD vs. VBIASREF
60
83.3mA
55
50
1.0
PSRR (dB)
33
MAX3935 toc10
32
MAX3935 toc11
0
MAX3935 toc09
MAX3935 toc08
PULSE WIDTH OF POSITIVE PULSE (ps)
MAX3935 toc07
40
MODULATION VOLTAGE vs. VMODREF
3.5
MODULATION VOLTAGE (V)
400
810
50
BIAS VOLTAGE (V)
PERCENT OF UNITS (%)
60
RPWC- (Ω)
1200
800
1600
PULSE WIDTH OF NEGATIVE PULSE (ps)
2000
TYPICAL DISTRIBUTION OF FALL TIME
0.8
0.6
100mA
45
40
20mA
35
0.4
30
0.2
25
20
0
0
0.05
0.10
0.15
VBIASREF (V)
0.20
0.25
0.30
0.01
0.1
1
10
100
1000 10,000
FREQUENCY (kHz)
_______________________________________________________________________________________
5
MAX3935†
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
DIFFERENTIAL S11 vs. FREQUENCY
S22 vs. FREQUENCY WITH POWER OFF
-5
-10
MAX3935 toc13
0
MAX3935 toc12
0
-5
-15
-10
|S22| (dB)
|S11| (dB)
MAX3935†
10.7Gbps EAM Driver
-20
-25
-30
-15
-20
-35
-25
-40
-45
-30
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
FREQUENCY (GHz)
8
10 12 14 16 18 20
FREQUENCY (GHz)
Pin Description
6
PIN
NAME
1, 4
VTT
2
DATA+
FUNCTION
Termination Reference Voltage for Data Inputs
Noninverting Data Input, with 50Ω On-Chip Termination
3
DATA-
5, 8
VTT
Inverting Data Input, with 50Ω On-Chip Termination
6
CLK+
Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
7
CLK-
Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
9
PWC+
Positive Input for Modulation Pulse-Width Adjustment. Connected to VEE through RPWC.
10
PWC-
Negative Input for Modulation Pulse-Width Adjustment. Connected to VEE through RPWC.
11, 18, 22, 30
GND
Ground
12, 13, 17,
23, 28, 29
VEE
Negative Supply Voltage
14
MODMON
Modulation Current Monitor. (VMODMON - VEE) / 3Ω = IMOD.
15
MODSET
Modulation Current Set. Connected to the output of an external op amp (see the Design Procedure
section).
16, 24
N.C.
19, 21
MODN2,
MODN1
20
MOD
Modulation Output, DC-Coupled to EAM
25
BIAS
EAM Bias Output. Connect to the EAM through an inductor.
Termination Voltage for Clock Inputs
No Connection. Leave unconnected.
Complementary Modulation Output with On-Chip Resistive Load. Connect to GND.
_______________________________________________________________________________________
10.7Gbps EAM Driver
PIN
NAME
FUNCTION
26
BIASSET
Bias Current Set. Connected to the output of an external op amp (see the Design Procedure
section).
27
BIASMON
Bias Current Monitor. (VBIASMON - VEE) / 7.5Ω = IBIAS.
31
MODEN
32
RTEN
TTL/CMOS Modulation Enable Input. Low for normal operation, high to put the EAM in the
absorption (logic 0) state. Internal 100kΩ pullup to GND.
TTL/CMOS Data Retiming Input. Low for retimed data, high to bypass retiming latch. Internal
100kΩ pullup to GND.
GND
DATA+
50Ω
DATA-
50Ω
DATA+
MODN1
DATA-
15Ω
BIAS
PATTERN
GENERATOR
OSCILLOSCOPE
MAX3935EGJ
VTT
50Ω
MOD
VOUT
CLK+
50Ω
50Ω
CLK+
MODN2
CLK-
50Ω
CLKRTEN
MODEN
-5.2V
-5.2V
-5.2V
Figure 1. AC Characterization Circuit
Detailed Description
The MAX3935 EAM driver consists of a high-speed
modulation driver and an EAM-biasing block (see
Figure 3). The clock and data inputs to the modulation
driver interface with ECL and CML logic levels. The
modulation and bias outputs sink current to V EE at
-5.2V.
The modulation output stage is composed of a highspeed differential pair and a programmable current
source rise times a maximum modulation current of
100mA. The rise and fall times are typically 34ps. The
modulation current is designed to produce an EAM
voltage up to 3.0VP-P when driving a 50Ω module. The
3.0Vp-p results from 100mA through 50Ω in parallel
with an internal 75Ω resistor (30Ω).
Any loading of the EAM module with capacitance
degrades the optical output performance. Because the
BIAS output is connected to the EAM, minimize the parasitic capacitance associated with this pad by using an
inductor (L) to isolate the BIAS pin from the EAM.
Clock/Data Input Logic Levels
The MAX3935 is directly compatible with 0V reference
CML. Other logic interfaces are possible with AC-coupling capacitors. For 0V CML of AC-coupled logic, set
VTT to 0V. For other DC-coupled differential signals, set
VTT to the common-mode input voltage.
_______________________________________________________________________________________
7
MAX3935†
Pin Description (continued)
MAX3935†
10.7Gbps EAM Driver
CLK+
VIS = 0.15V
TO 1.0V
CLKtSU
tHD
DATADATA+
VIS = 0.15V
TO 1.0V
(MODMON). The voltage at BIASMON is equal to (IBIAS
✕ RBIAS) + VEE, and the voltage at MODMON is equal
to (IMOD ✕ RMOD) + VEE. IBIAS and IMOD are shown in
Figure 3. The internal resistors RBIAS and RMOD are
7.5Ω and 3Ω, respectively (±10%). Connect BIASMON
and MODMON to the inverting input of an op amp to
program the bias and modulation current (see Design
Procedure).
Design Procedure
Programming the Modulation Voltage
VID = 0.3V
TO 2.0V
The EAM modulation voltage results from IMOD passing
through the EAM impedance in parallel with the internal
75Ω termination resistor.
(DATA+) - (DATA-)
VMOD ≈ IMOD ×
0.6V
TO 3.0V
VOUT
Figure 2. Required Input Signal, Setup/Hold-Time Definition
and Output Polarity
Optional Input Data Retiming
To eliminate pattern-dependent jitter in the input data,
connect a synchronous differential clock signal to the
CLK+ and CLK- inputs, and the RTEN control input
should be tied low. The input data is retimed on the rising edge of CLK+. If RTEN is tied high or left floating,
the retiming function is disabled and the input data is
directly connected to the output stage. Leave CLK+
and CLK- open when retiming is disabled.
Pulse-Width Control
The pulse-width control circuit can be used to minimize
pulse-width distortion. The differential voltage between
PWC+ and PWC- adjusts the pulse-width compensation. When PWC+ and PWC- are left open, the pulsewidth control circuit is automatically disabled.
Modulation Output Enable
The MAX3935 incorporates a modulation current
enable input. When MODEN is low, the modulation output (MOD) is enabled. When MODEN is high or floating,
the output is disabled. In the disabled condition, the
modulation output sinks current to keep the EAM module in the high-absorption state. The typical EAM
enable time is 2ns, and the typical disable time is 5ns.
Current Monitors
The MAX3935 features a bias-current monitor output
(BIASMON) and a modulation-current monitor output
8
ZEAM × 75Ω
ZEAM + 75Ω
To program the desired modulation current, connect
the inverting input of an op amp (see the Typical
Application Circuit) to MODMON and connect the output to MODSET. Connect the positive op amp voltage
supply to ground and the negative supply to VEE. The
modulation current is set by connecting a reference
voltage VMODREF to the noninverting input of the op
amp. See the Modulation Voltage vs. V MODREF
graph in the Typical Operating Characteristics to select
the value of VMODREF that corresponds to the required
modulation current.
IMOD =
VMODREF
3Ω
Programming the Bias Voltage
The EAM bias voltage results from I BIAS passing
through the EAM impedance in parallel with the internal
75Ω termination resistor.
VBIAS ≈ IBIAS ×
ZEAM × 75Ω
ZEAM + 75Ω
To program the desired EAM bias current, connect the
inverting input of an op amp (see the Typical Application
Circuit) to BIASMON and connect the output to BIASSET.
Connect the positive op amp voltage supply to ground
and the negative supply to VEE . The EAM bias current is
set by connecting a reference voltage VBIASREF to the
noninverting input of the op amp. See the Bias Voltage
vs. V BIASREF graph in the Typical Operating
Characteristics to select the value of VBIAS that corresponds to the required EAM bias voltage.
_______________________________________________________________________________________
10.7Gbps EAM Driver
MAX3935†
RTEN
MODEN
VTT
75Ω
50Ω
50Ω
EAM
75Ω
50Ω
CLK+
100Ω
MODN1
50Ω
MOD2
MOD
50Ω
MOD1
50Ω
MODN2
CLK100Ω
0
Q
BIAS
D
DATA+
PWC
MUX
50Ω
L
1
50Ω
IMOD
DATA-
50Ω
IBIAS
50Ω
VTT
1mA
1mA
RMOD
RBIAS
5kΩ
RPWC
PWC+
PWC-
MODSET
5kΩ
BIASSET
VEE MODMON
VEE
BIASMON
2kΩ
VEE
Figure 3. MAX3935EGJ Functional Diagram
IBIAS =
VBIASREF
7.5Ω
To keep the bias and modulation currents in compliance, the following constraint on the total current must
be made for 50Ω EAM modules:
|VEE| - (IBIAS + IMOD) ✕ 30Ω ≥ 1.55V
External Op Amp Selection
External op amps are required for regulating the bias
and modulation currents. The ability to operate from a
single supply with input common-mode range extending to the negative supply rail is critical in the op amp
selection. Low bias current and high PSRR also are
important. Bias current to the inverting input passes
through a 5kΩ resistor. This could add an error to the
voltage produced by the modulation and bias currentsense resistors. The op amp gain bandwidth must be
high enough to regulate at the power-supply ripple frequency on VEE.
Pulse-Width Control Setup
Two methods of control are possible when pulse predistortion is desired to minimize distortion at the receiver.
The pulse width can be set with a 2kΩ potentiometer (or
equivalent fixed resistors); or applying a voltage, with
VEE + 1V common mode, to the PWC pins can set it. See
Table 1 for the desired effect of the pulse-width setting.
Table 1. Pulse-Width Control
PULSE
WIDTH
RP, RN for
RP + RN = 2kΩ
VPWC+, VPWC- for
VCM = VEE + 1V
100%
1kΩ or Open
VPWC+ = VPWC- = VEE + 1V
>100%
RP > RN
VPWC+ > VPWC-
<100%
RP < RN
VPWC+ < VPWC-
_______________________________________________________________________________________
9
MAX3935†
10.7Gbps EAM Driver
Applications Information
Input and Output Schematics
Layout Considerations
To minimize loss and crosstalk, keep the connections
between the MAX3935 output and the EAM module as
short as possible. Use good high-frequency layout
techniques and multilayer boards with uninterrupted
ground plane to minimize EMI and crosstalk. Make circuit boards using low-loss dielectrics. Use controlledimpedance lines for the clock and data inputs as well
as the modulation output.
Wire Bonding Die
For high-current density and reliable operation, the
MAX3935 uses gold metalization. Make connections to
the die with gold wire only, using ball-bonding techniques. Wedge-bonding processes are not recommended due to possible fracturing of sublayers
caused by stress during bonding. Die thickness is
8 mils (203µm). Die size is 64 mils by 120 mils
(1.626mm by 3.048mm).
The inductance at the high-speed connections for
MOD1, MOD2 and MODN1, MODN2 must be minimized. The minimum length of the bond wires is constrained by the type of wire bonder used as well as the
dimensions of the die. Wire length measured in the x-y
plane from the edge of the die should approach 15 mils
if possible. The bond wire must not come closer to the
edge of die than 2X the bond wire diameter. MOD1 and
MOD2 should each have a wire bond to reduce the total
inductance for the MOD output.
VTT
50Ω
GND
50Ω
DATA+
DATA-
VEE
Figure 4. Equivalent Input Circuit
GND
MODN1 MOD1 MOD2 MODN2
GND
100Ω
100Ω
150Ω
150Ω
150Ω
150Ω
IMOD
VEE
* NOTE: ESD PROTECTION IS INCLUDED ON MOD1, MOD2, MODN1, AND MODN2.
Figure 5. Equivalent Output Circuit
10
______________________________________________________________________________________
10.7Gbps EAM Driver
RTEN
MODEN
GND
VEE
VEE
BIASMON
BIASSET
BIAS
32
31
30
29
28
27
26
25
TOP VIEW
VTT
1
24
N.C.
DATA+
2
23
VEE
DATA-
3
22
GND
VTT
4
21
MODN1
VTT
5
20
MOD
CLK+
6
19
MODN2
CLK-
7
18
GND
VTT
8
17
VEE
9
10
11
12
13
14
15
16
PWC+
PWC-
GND
VEE
VEE
MODMON
MODSET
N.C.
MAX3935
Chip Topography
The origin for pad coordinates is the center of the die.
All pad locations are referenced from the origin and
indicate the center of the pad where the bond wire
should be connected. For more information on bonding
coordinates refer to Maxim Application Note HFAN08.0.1: Understanding Bonding Coordinates and
Physical Die Size on Maxim’s website.
Chip Information
TRANSISTOR COUNT: 1535
SUBSTRATE: INSULATOR, CONNECT TO GND
PROCESS: SiGe BIPOLAR
DIE THICKNESS: 8 mils
THE EXPOSED PAD MUST BE SOLDERED TO
SUPPLY GROUND ON THE CIRCUIT BOARD.
Chip Topography
RTEN
N.C.
N.C.
GND
VEE
VCC
MODEN
GND
VEE
VEE
GND
BIASSET
BIASMON
VEE
BIAS
VEE
VTT
DATA+
GND
DATA-
MODN1
VTT
MOD1
VTT
MOD2
CLK+
MODN2
CLK-
GND
VTT
VEE
PWC+
N.C.
N.C.
N.C.
PWC-
GND
N.C.
VEE
VEE
VEE
GND
GND
VEE
GND
MODSET
MODMON
N.C.
______________________________________________________________________________________
11
MAX3935†
Pin Configuration
10.7Gbps EAM Driver
MAX3935†
Pad Coordinates
PAD
COORDINATE
X
PAD
NAME
GND
Y
COORDINATE
X
Y
1393.5
392
1
VTT
-1393.5
-531
25
2
CLK-
-1393.5
-392
26
MODN1
1393.5
266
3
CLK+
-1393.5
-266
27
MOD1
1393.5
140
4
VTT
-1393.5
-140
28
MOD2
1393.5
-140
5
VTT
-1393.5
140
29
MODN2
1393.5
-266
6
DATA-
-1393.5
266
30
GND
1393.5
-392
7
DATA+
-1393.5
392
31
VEE
1393.5
-531
530
32
GND
1333.5
-681
8
VTT
-1393.5
9
N.C.
-914.5
681
33
N.C.
1207.5
-681
10
N.C.
-788.5
681
34
MODSET
1081.5
-681
11
RTEN
-637.5
681
35
MODMON
955.5
-681
12
MODEN
-511.5
681
36
VEE
829.5
-681
13
GND
-133.5
681
37
VEE
703.5
-681
681
38
GND
474.5
-681
14
12
NAME
VEE
-7.5
15
VEE
118.5
681
39
GND
348.5
-681
16
GND
348.5
681
40
VEE
118.5
-681
17
GND
474.5
681
41
VEE
-7.5
-681
18
VEE
703.5
681
42
GND
-133.5
-681
19
VEE
829.5
681
43
N.C.
-259.5
-681
20
BIASMON
955.5
681
44
N.C.
-385.5
-681
21
BIASSET
1081.5
681
45
PWC-
-511.5
-681
22
BIAS
1207.5
681
46
PWC+
-637.5
-681
23
GND
1333.5
681
47
N.C.
-788.5
-681
24
VEE
1393.5
530
48
N.C.
-914.5
-681
______________________________________________________________________________________
10.7Gbps EAM Driver
32L QFN.EPS
PACKAGE OUTLINE, 16,20,28,32L QFN,
5x5x0.90 MM
1
21-0091
I
2
______________________________________________________________________________________
13
MAX3935†
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.
32L QFN.EPS
MAX3935†
10.7Gbps EAM Driver
PACKAGE OUTLINE, 16,20,28,32L QFN,
5x5x0.90 MM
1
21-0091
I
2
Maxim makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Maxim assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation consequential
or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “typicals” must be validated for
each customer application by customer’s technical experts. Maxim products are not designed, intended or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
Maxim product could create a situation where personal injury or death may occur.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.