19-2934; Rev 0; 7/03 10Gbps Modulator Driver Features ♦ 23ps Edge Speed ♦ Single-Ended Modulation Voltage Up to 3VP-P ♦ Differential Modulation Voltage Up to 6VP-P ♦ Selectable Data-Retiming Latch ♦ Up to 10.7Gbps Operation ♦ 50Ω On-Chip Input and Output Terminations ♦ Pulse-Width Adjustment ♦ Enable and Polarity Controls ♦ ESD Protection Applications Mach Zehnder Modulators Packaged Direct-Modulated Lasers SONET OC-192 and SDH STM-64 Transmission Systems DWDM Systems Long/Short-Reach Optical Transmitters Ordering Information PART TEMP RANGE PIN-PACKAGE MAX3942ETG -40°C to +85°C 24 Thin QFN (4mm ✕ 4mm) 10Gbps Ethernet Pin Configuration appears at end of data sheet. Typical Application Circuit 50Ω -5.2V L2 PLRT 0.01µF 50Ω DATA+ MODEN RTEN 0.01µF GND 50Ω OUT- DATA+ 0.01µF MAX3952 50Ω DATA- MACH ZEHNDER MODULATOR DATA50Ω 10Gbps SERIALIZER MAX3942 0.01µF CLK+ 50Ω CLK+ 50Ω CLK- L1 0.01µF 0.01µF CLK- 50Ω OUT+ PWC+ PWC2kΩ -5.2V MODSET VEE + VMODSET - -5.2V -5.2V 1000pF 0.1µF L1 AND L2 ARE HIGH-FREQUENCY FERRITE BEADS REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3942 General Description The MAX3942 is designed to drive high-speed optical modulators at data rates up to 10.7Gbps. It functions as a modulation circuit, with an integrated control op amp externally programmed by a DC voltage. A high-bandwidth, fully differential signal path is internally implemented to minimize jitter accumulation. When a clock signal is available, the integrated data-retiming function can be selected to reject input-signal jitter. The MAX3942 receives differential CML signals (groundreferenced) with on-chip line terminations of 50Ω. Each of the differential outputs has an on-chip 50Ω resistor for back termination. The driver is able to deliver a modulation current of 40mA P-P to 120mA P-P, with an edge speed of 23ps (typical 20% to 80%). This modulation current reflects a modulation voltage of 1.0VP-P to 3.0VP-P single ended or 2.0VP-P to 6.0VP-P differential. The MAX3942 also includes an adjustable pulse-width control circuit to precompensate for asymmetrical modulator characteristics. It is available in a compact 4mm ✕ 4mm, 24-pin thin QFN package and operates over the -40°C to +85°C temperature range. MAX3942 10Gbps Modulator Driver ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +85°C) 24-Pin Thin QFN (derate 20.8mW/° above +85°C) ....1354mW Current into or out of OUT+, OUT-.................……………...80mA Storage Temperature Range .....................……-55°C to +150°C Operating Temperature Range ....................……-40°C to +85°C Lead Temperature (soldering, 10s)............………………+300°C Supply Voltage VEE ..............................................-6.0V to +0.5V Voltage at MODEN, RTEN, PLRT, MODSET............................(VEE - 0.5V) to +0.5V Voltage at DATA+, DATA-, CLK+, and CLK-……-1.65V to +0.5V Voltage at OUT+, OUT- ................................……….-4V to +0.5V Voltage at PWC+, PWC- ...................(VEE - 0.5V) to (VEE + 1.7V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IMOD = 100mA, and TA = +25°C, unless otherwise noted.) PARAMETER Power-Supply Voltage Supply Current Power-Supply Noise Rejection SYMBOL CONDITIONS VEE IEE PSNR MIN TYP -5.5 Excluding IMOD (Note 1) MAX UNITS -4.9 V Retime disabled 125 175 Retime enabled 140 200 f ≤ 2MHz (Note 2); see Figure 3 15 mA dB SIGNAL INPUT (Note 3) Input Data Rates NRZ Single-Ended Input Resistance RIN Single-Ended Input Voltage VIS Differential Input Voltage VID Differential Input Return Loss RLIN Input to GND 10.7 42.5 50 Gbps 58.5 DC-coupled, Figure 1a -1 0 AC-coupled, Figure 1b -0.4 +0.4 DC-coupled (Note 4) 0.2 2.0 AC-coupled (Note 4) 0.2 1.6 ≤ 15GHz 15 Ω V VP-P dB MODULATION (Note 5) Maximum Modulation Current 112 Minimum Modulation Current VMODSET = VEE MODSET Voltage Range VMODSET Equivalent Modulation Resistance RMODEQV Modulation Set Bandwidth 120 37 VEE (Note 7) Modulation depth 10%, 50Ω driver load MODSET Input Resistance mAP-P 40 mAP-P VEE + 1 V 11.1 Ω 5 MHz 20 kΩ Modulation-Current Temperature Stability (Note 6) -980 0 ppm/°C Modulation-Current-Setting Error 50Ω driver load, TA = +25°C -10 +10 % OUT+ and OUT- to GND 42.5 58.5 Ω Output Resistance 2 ROUT 50 _______________________________________________________________________________________ 10Gbps Modulator Driver (VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IMOD = 100mA, and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MODEN = VEE, MODSET = VEE, DATA+ = high, DATA- = low Off Current Differential Output Return Loss RLOUT Output Edge Speed Setup/Hold Time IMOD = 50mA Pulse-Width Adjustment Range Figure 2 (Note 6) (Notes 6, 8) Pulse-Width Control Input Range (Single Ended) For PWC+ and PWC- Pulse-Width Control Input Range (Differential) (PWC+) - (PWC-) δ 23 RJDR (Note 6) Driver Deterministic Jitter DJDR PWC- = GND (Notes 6, 9) 1.6 mA dB 32 25 ±30 ps ps ±50 ps VEE + 0.5 VEE + 1.5 V -0.5 +0.5 V 0.3 0.8 psRMS 8 13 psP-P (Notes 6, 8) Driver Random Jitter UNITS 10 20% to 80% (Notes 6, 8) tSU, tHD Output Overshoot ≤ 10GHz MAX 5 % CONTROL INPUTS Input High Voltage VIH (Note 10) Input Low Voltage VIL (Note 10) Input Current (Note 10) VEE + 2.0 -80 V VEE + 0.8 V +200 µA Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply current after the retiming function has been disabled. Note 2: Power-supply noise rejection is specified as PSNR = 20Log(Vnoise (on Vcc) / ∆VOUT). VOUT is the voltage across a 50Ω load. Vnoise (on Vcc) = 100mVP-P. Note 3: For DATA+, DATA-, CLK+, and CLK-. Note 4: CLK input characterized at 10.7Gbps. Note 5: Minimum voltage on OUT+ and OUT- is VEE + 1.9V. Note 6: Guaranteed by design and characterization using the circuit shown in Figure 3. Note 7: RMODEQV = (VMODSET - VEE) / (IMOD - 37mA). Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern. Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter). Measured with a 10.7Gbps 27 - 1 PRBS pattern with 80 zeros and 80 ones inserted in the data pattern. Note 10: For MODEN and PLRT. _______________________________________________________________________________________ 3 MAX3942 ELECTRICAL CHARACTERISTICS (continued) 10Gbps Modulator Driver MAX3942 Test Circuits and Timing Diagrams 0V 100mV 1.0V -0.5V -1.0V (a) DC-COUPLED SINGLE-ENDED CML INPUT 0.4V 800mV 0V -0.4V 100mV (b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT Figure 1. Definition of Single-Ended Input Voltage Range CLK+ VIS = 0.1VP-P TO 1VP-P DC-COUPLED 0.1VP-P TO 0.8VP-P AC-COUPLED CLKtSU tHD DATA- DATA+ (DATA+) - (DATA-) VID = 0.2VP-P TO 2VP-P DC-COUPLED 0.2VP-P TO 1.6VP-P AC-COUPLED IOUT+ IMOD = 40mAP-P TO 120mAP-P IOUTNOTE: IOUT+ AND IOUT- RELATE TO RETIMED DATA. SEE FIGURE 3 FOR POLARITY. Figure 2. Setup and Hold Timing Definition 4 _______________________________________________________________________________________ 10Gbps Modulator Driver PLRT 50Ω RTEN MODEN PWC+ PWC- CLK+ IOUT- 50Ω OSCILLOSCOPE CLK- PATTERN GENERATOR MAX3942 50Ω DATA+ 50Ω DATA- OUT- 50Ω OUT+ 50Ω 50Ω IOUT+ ZL VEE MODSET -5.2V GND VMODSET 0.1µF 1000pF VEE Figure 3. AC Characterization Circuit _______________________________________________________________________________________ 5 MAX3942 Test Circuits and Timing Diagrams (continued) Typical Operating Characteristics (Typical values are at VEE = -5.2V, IMOD = 100mA, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE (50Ω LOAD, EXCLUDES IMOD) 10.7Gbps ELECTRICAL EYE DIAGRAM (VMOD = 6VP-P DIFFERENTIAL, 231 - 1 PRBS) MAX3942 toc01 MAX3942 toc03 170 MAX3942 toc02 10.7Gbps ELECTRICAL EYE DIAGRAM (VMOD = 2VP-P DIFFERENTIAL, 231 - 1 PRBS) 160 150 IEE (mA) RETIMING ENABLED 140 130 120 RETIMING DISABLED 110 100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 16ps/div 16ps/div TEMPERATURE (°C) 820 810 800 790 780 770 1.8 7 1.6 VMODSET IS RELATIVE TO VEE 6 1.4 1.2 1.0 0.8 0.6 0 POWER-SUPPLY NOISE REJECTION vs. FREQUENCY -30 -10 10 30 50 70 90 0 DIFFERENTIAL S22 vs. FREQUENCY (DEVICE POWERED) 0 MAX3942 toc08 -5 -3 -6 |S22| (dB) IS11I (dB) 1.00 -9 -15 -20 -25 -12 -15 -18 -21 -30 -24 5 0 1 10 100 FREQUENCY (Hz) 6 0.75 DIFFERENTIAL S11 vs. FREQUENCY (DEVICE POWERED) 20 10 0.50 VMODSET (V) -10 15 0.25 TEMPERATURE (°C) 0 MAX3942 toc07 25 2 0 -50 250 500 750 1000 1250 1500 1750 2000 RPWC+ (Ω) 30 3 1 0 750 4 0.4 0.2 760 5 MAX3942 toc09 830 2.0 DIFFERENTIAL VMOD (VP-P) MEASURED AT 1.25Gbps WITH A 1010 PATTERN 840 DIFFERENTIAL VMOD vs. VMODSET (ZL = 50Ω ON OUT+ AND OUT-) MAX3942 toc05 MAX3942 toc04 PULSE-WIDTH POSITIVE PULSE (ps) 850 PULSE-WIDTH DISTORTION vs. TEMPERATURE 0 PULSE-WIDTH DISTORTION (ps) RPWC- (Ω) 2000 1750 1500 1250 1000 750 500 250 MAX3942 toc06 PULSE WIDTH vs. RPWC PSNR (dB) MAX3942 10Gbps Modulator Driver 1k 10k -35 -27 -40 -30 0 3 6 9 FREQUENCY (GHz) 12 15 0 3 6 9 FREQUENCY (GHz) _______________________________________________________________________________________ 12 15 10Gbps Modulator Driver PIN NAME FUNCTION 1 DATA+ Noninverting Data Input, with 50Ω On-Chip Termination 2 DATA- Inverting Data Input, with 50Ω On-Chip Termination 3, 4, 14, 17 GND Ground. All pins must be connected to board ground. 5 CLK+ Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination 6 CLK- Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination 7, 11, 12, 13, 18, 19, 21, 24 VEE 8 PWC+ Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section). 9 PWC- Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width adjustment feature (see the Design Procedure section). 10 MODSET Negative Supply Voltage. All pins must be connected to board VEE. Modulation Current Set. Apply a voltage to set the modulation current of the driver output. 15 OUT- Inverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current when PLRT is high and when differential data is high. 16 OUT+ Noninverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current when PLRT is high and when differential data is low. 20 PLRT Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the differential signal polarity. Contains an internal 100kΩ pullup to GND. 22 MODEN 23 RTEN EP Exposed Pad TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to VEE. Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch. Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance. See the Layout Considerations section. Detailed Description The MAX3942 modulator driver accepts differential clock and data inputs that are compatible with PECL and CML logic levels. The modulation output stage is composed of a highspeed differential pair and a programmable current source with a maximum modulation current of 120mA. The rise and fall times are typically 23ps. The modulation current is designed to produce a modulation voltage up to 3.0VP-P single endedly, or 6.0VP-P differentially when driving a 50Ω module. The 3.0VP-P results from 120mAP-P through the parallel combination of the 50Ω modulator load and the internal 50Ω back termination. Polarity Switch The MAX3942 includes a polarity switch. When the PLRT pin is high or left floating, the outputs maintain the polarity of the input data. When the PLRT pin is low, the outputs are inverted relative to the input data. Clock/Data Input Logic Levels The MAX3942 is directly compatible with ground-reference CML. Either DC- or AC-coupling may be used for CML referenced to ground. For all other logic types, AC-coupling should be used. Optional Data Input Latch To reject pattern-dependent jitter in the input data, a synchronous differential clock signal should be connected to the CLK+ and CLK- inputs, and the RTEN control input should be connected to VEE. _______________________________________________________________________________________ 7 MAX3942 Pin Description MAX3942 10Gbps Modulator Driver The input data is retimed on the rising edge of CLK+. If RTEN is connected to ground, the retiming function is disabled and the input data is directly connected to the output stage. Leave CLK+ and CLK- open when retiming is disabled. An internal, independent current source drives a constant 37mA to the modulation circuitry and any voltage above VEE on the MODSET pin adds to this. The input impedance of the MODSET pin is typically 20kΩ. Note that the minimum output voltage is VEE + 1.9V. Pulse-Width Control Programming the Pulse-Width Control The pulse-width control circuit can be used to compensate for pulse-width distortion introduced by the modulator. The differential voltage between PWC+ and PWCadjusts the pulse-width compensation. The adjustment range is typically ±50ps. Optional single-ended operation is possible by forcing a voltage on the PWC+ pin while leaving the PWC- pin unconnected. When PWCis connected to ground, the pulse-width control circuit is automatically disabled. Three methods of control are possible when pulse predistortion is desired to minimize distortion at the receiver. The pulse width may be set with a 2kΩ potentiometer with the center tapped to VEE (or equivalent fixed resistors), or by applying a voltage to the PWC+ pin, or by applying a differential voltage across the PWC+ and PWC- pins. See Table 1 for the desired effect of the pulse-width setting. Pulse width is defined as (positive pulse width)/((positive pulse width + negative pulse width)/2). Modulation Output Enable Input Termination Requirement The MAX3942 incorporates a modulation currentenable input. When MODEN is low or floating, the modulation outputs OUT+ and OUT- are enabled. When MODEN is high, the drive current is switched to OUT+. The typical enable time is 2ns and the typical disable time is 2ns. The MAX3942 data and clock inputs are CML compatible. However, it is not necessary to drive the IC with a standard CML signal. As long as the specified input voltage swings are met, the MAX3942 operates properly. Design Procedure Programming the Modulation Voltage The modulation voltage results from I MOD passing through the load impedance (ZL) in parallel with the internal 50Ω termination resistor (ROUT): VMOD ≈ IMOD × ZL × ROUT ZL + ROUT To program the desired modulation current, force a voltage at the MODSET pin (see the Typical Application Circuit). The resulting IMOD current can be calculated by the following equation: IMOD ≈ 8 VMODSET + 37mA 11.1Ω Applications Information Layout Considerations To minimize loss and crosstalk, keep the connections between the MAX3942 output and the modulator as short as possible. Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Circuit boards should be made using low-loss dielectrics. Use controlled-impedance lines for the clock and data inputs, as well as for the data output. Table 1. Pulse-Width Control PULSE WIDTH (%) RPWC+, RPWC- FOR RPWC+ + RPWC- = 2kΩ VPWC+ (PWC- OPEN) (V) VPWC+ VPWC(V) 100 RPWC+ = RPWC- VEE + 1 0 >100 RPWC+ > RPWC- > VEE + 1 >0 <100 RPWC+ < RPWC- < VEE + 1 <0 _______________________________________________________________________________________ 10Gbps Modulator Driver MODEN PLRT 50Ω 50Ω 50Ω 50Ω 50Ω MAX3942 RTEN 50Ω OUTOUT+ CLK+ VEE CLKD Q 0 MUX DATA+ DATA- POLARITY PWC 1 50Ω IMOD 50Ω MAX3942 PWC+ VEE MODSET PWC2kΩ + VMODSET - VEE VEE Figure 4. Functional Diagram GND Interface Schematics Figures 5 and 6 show simplified input and output circuits of the MAX3942 modulator driver. To minimize inductance, keep the connections from OUT, GND, and VEE as short as possible. This is crucial for optimal performance. Laser Safety and IEC 825 Using the MAX3942 EAM driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each customer must determine the level of fault tolerance required by their application, recognizing that Maxim products are not designed or authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application where the failure of a Maxim product could create a situation where personal injury or death may occur. 50Ω 50Ω MAX3942 DATA+/CLK+ DATA-/CLK- VEE Figure 5. Simplified Input Circuit _______________________________________________________________________________________ 9 10Gbps Modulator Driver MAX3942 Exposed-Pad Package GND GND MAX3942 50Ω GND 50Ω GND OUT- The exposed pad on the 24-pin QFN provides a very low thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3942 and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Maxim Application Note HFAN-08.1: Thermal Considerations for QFN and Other Exposed-Pad Packages for additional information. OUT+ Chip Information VEE VEE TRANSISTOR COUNT: 1918 PROCESS: SiGe Bipolar Figure 6. Simplified Output Circuit VEE RTEN MODEN VEE PLRT VEE 24 23 22 21 20 19 Pin Configuration TOP VIEW Package Information DATA+ 1 18 VEE DATA- 2 17 GND GND 3 16 OUT+ 15 OUT- MAX3942 PACKAGE TYPE PACKAGE CODE MAX3942ETG 24 Thin QFN (4mm ✕ 4mm ✕ 0.8mm) T2444-1 12 PART VEE 11 VEE VEE 13 10 6 MODSET CLK- 9 GND PWC- 14 8 5 PWC+ CLK+ 7 4 VEE. GND For the latest package outline information, go to www.maxim-ic.com/packages. 24 THIN QFN (4mm x 4mm) EXPOSED PAD CONNECTED TO GROUND Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.