19-2730; Rev 0; 1/03 10Gbps EAM Driver with Integrated Bias Network Features ♦ On-Chip Bias Network ♦ 23ps Edge Speed ♦ Programmable Modulation Voltage Up to 3VP-P ♦ Programmable EAM Biasing Voltage Up to 1.25V ♦ Selectable Data-Retiming Latch ♦ Up to 10.7Gbps Operation ♦ Integrated Modulation and Biasing Functions ♦ 50Ω On-Chip Input and Output Terminations ♦ Pulse-Width Adjustment ♦ Enable and Polarity Controls ♦ ESD Protection Ordering Information PART MAX3940E/D TEMP RANGE PIN-PACKAGE -40°C to +85°C Dice* *Dice are designed to operate over a -40°C to +120°C junction temperature (TJ) range, but are tested and guaranteed at TA = +25°C only. Applications SONET OC-192 and SDH STM-64 Transmission Systems DWDM Systems Long/Short-Reach Optical Transmitters 10Gbps Ethernet Typical Application Circuit -5.2V PLRT 0.01µF 50Ω DATA+ MODEN RTEN GND DATA+ EAM 0.01µF MAX3952 DATA- 10Gbps SERIALIZER 50Ω DATA- 50Ω CLK+ 50Ω CLK- MAX3940 0.01µF CLK+ OUT 50Ω 0.01µF CLK- PWC+ PWC2kΩ -5.2V MODSET BIASSET + VMODSET - + VBIASSET - VEE -5.2V -5.2V 330pF 0.1µF REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3940 General Description The MAX3940 is designed to drive an electro-absorption modulator (EAM) at data rates up to 10.7Gbps. It incorporates the functions of a biasing circuit and a modulation circuit, with integrated control op amps externally programmed by DC voltages. The integrated bias circuit provides a programmable biasing current up to 50mA. This bias current reflects a bias voltage of up to 1.25V on an external 50Ω load. The bias and modulation circuits are internally connected on chip, eliminating the need for an external bias inductor. A high-bandwidth, fully differential signal path is internally implemented to minimize jitter accumulation. When a clock signal is available, the integrated data-retiming function can be selected to reject input-signal jitter. The MAX3940 receives differential CML signals (ground referenced) with on-chip line terminations of 50Ω. The output has a 50Ω resistor for back termination and is able to deliver a modulation current of 40mA P-P to 120mAP-P, with an edge speed of 23ps (typical, 20% to 80%). This modulation current reflects an EAM modulation voltage of 1.0VP-P to 3.0VP-P. The MAX3940 also includes an adjustable pulse-width control circuit to precompensate for asymmetrical EAM characteristics. MAX3940 10Gbps EAM Driver with Integrated Bias Network ABSOLUTE MAXIMUM RATINGS Current into or out of OUT..............................……………...80mA Storage Temperature Range .....................……-55°C to +150°C Operating Junction Temperature Range....……-55°C to +150°C Processing Temperature (die)....................………………+400°C Supply Voltage VEE ..............................................-6.0V to +0.5V Voltage at MODEN, RTEN, PLRT, MODSET, BIASSET ...........(VEE - 0.5V) to +0.5V Voltage at DATA+, DATA-, CLK+, and CLK-……-1.65V to +0.5V Voltage at OUT .............................................……….-4V to +0.5V Voltage at PWC+, PWC- ...................(VEE - 0.5V) to (VEE + 1.7V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, and TA = +25°C, unless otherwise noted.) PARAMETER Power-Supply Voltage Supply Current Power-Supply Noise Rejection SYMBOL CONDITIONS VEE IEE PSNR MIN TYP -5.5 Excluding IBIAS and IMOD (Note 1) MAX UNITS -4.9 V Retime disabled 122 170 Retime enabled 139 195 f ≤ 10MHz (Note 2), see Figure 4 12 mA dB SIGNAL INPUT (Note 3) Input Data Rates Single-Ended Input Resistance NRZ RIN Single-Ended Input Voltage VIS Differential Input Voltage VID Differential Input Return Loss RLIN 10.7 42.5 DC-coupled, Figure 1a -1 0 AC-coupled, Figure 1b -0.4 +0.4 DC-coupled (Note 4) 0.2 2.0 AC-coupled (Note 4) 0.2 1.6 (Note 3) 50 Gbps Input to GND (Note 3) ≤ 10GHz 17 10GHz < f ≤ 15GHz 10 58.5 Ω V VP-P dB EAM BIAS Maximum Bias Current VBIASSET = VEE + 2V Minimum Bias Current VBIASSET = VEE BIASSET Voltage Range VBIASSET Equivalent Bias Resistance RBSEQV Bias-Current-Setting Accuracy VEE (Note 6) mA 1 VEE + 2 VBIASSET = VEE + 0.11V 2.1 3.9 VBIASSET = VEE + 0.36V 8.8 11.2 VBIASSET = VEE + 2.0V 52 58 VBIASSET < VEE + 0.36V -1300 +1300 VBIASSET ≥ VEE + 0.36V -480 +480 50Ω driver load, VBIASSET = VEE + 0.55V, Figure 2 mA V Ω 36.4 BIASSET Input Resistance BIASSET Bandwidth 55 0.3 (Note 5) TA = +25°C Bias-Current Temperature Stability 50 mA ppm/°C 20 kΩ 5 MHz EAM MODULATION Maximum Modulation Current VMODSET = VEE + 1V Minimum Modulation Current VMODSET = VEE MODSET Voltage Range VMODSET Equivalent Modulation Resistance RMODEQV 2 120 127 38 VEE (Note 7) 11.1 _______________________________________________________________________________________ mAP-P 40 mAP-P VEE + 1 V Ω 10Gbps EAM Driver with Integrated Bias Network (VEE = -5.5V to -4.9V, TA = -40°C to +85°C. Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Modulation depth 10%, 50Ω driver load, see Figure 2 Modulation Set Bandwidth MODSET Input Resistance Modulation-Current Temperature Stability (Note 6) Modulation-Current Setting Error Output Resistance OUT to GND 20 kΩ 50 BIASSET = VEE, MODEN = VEE, MODSET = VEE, DATA+ = high, DATA- = low Total Off Current Output Return Loss RLOUT IBIAS = 30mA, IMOD = 50mA tSU, tHD Figure 3 (Note 6) Output Edge Speed ≤ 5GHz Pulse-Width Adjustment Range (Notes 6, 8) Pulse-Width Control Input Range (Single Ended) For PWC+ and PWC- Pulse-Width Control Input Range (Differential) δ Output Overshoot +480 ppm/°C +5 % 58.5 Ω 1 mA 8 20% to 80% (Notes 6, 8) Setup/Hold Time 23 dB 32 25 ±20 UNITS MHz -5 42.5 MAX 5 -480 50Ω driver load, TA = +25°C ROUT TYP ps ps ±50 ps VEE + 0.5 VEE + 1.5 V (PWC+) - (PWC-) -0.5 +0.5 V (Notes 6, 8) -10 +10 % Driver Random Jitter RJDR (Note 6) 0.3 1.1 psRMS Driver Deterministic Jitter DJDR PWC- = GND (Notes 6, 9) 6.8 14 psP-P CONTROL INPUTS Input High Voltage VIH (Note 10) Input Low Voltage VIL (Note 10) Input Current (Note 10) VEE + 2.0 -80 V VEE + 0.8 V +80 µA Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply current after the retiming function has been disabled. Note 2: Power-supply noise rejection is specified as PSNR = 20Log(Vnoise (on Vcc) / ∆VOUT). VOUT is the voltage across a 50Ω load. Vnoise (on Vcc) = 100mVP-P. Note 3: For DATA+, DATA-, CLK+, and CLK-. Note 4: CLK input characterized at 10.7Gbps Note 5: RBSEQV = (VBIASSET - VEE) / IOUT with MODEN = VEE, DATA+ = high, and DATA- = low. Note 6: Guaranteed by design and characterization using the circuit shown in Figure 4. Note 7: RMODEQV = (VMODSET - VEE) / (IOUT - 37mA) with BIASSET = VEE. Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern. Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter). Measured with a 10.7Gbps 27 - 1 PRBS pattern with eighty 0s and eighty 1s inserted in the data pattern. Note 10: For MODEN and PLRT. _______________________________________________________________________________________ 3 MAX3940 ELECTRICAL CHARACTERISTICS (continued) 10Gbps EAM Driver with Integrated Bias Network MAX3940 Test Circuits and Timing Diagrams 0V 100mV 1.0V -0.5V -1.0V (a) DC-COUPLED SINGLE-ENDED CML INPUT 0.4V 800mV 0V -0.4V 100mV (b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT Figure 1. Definition of Single-Ended Input Voltage Range 0V 0V VOUT VOUT VBIASSET (a) MODULATING BIASSET (c) RESULT OF MODULATING BIASSET AND MODSET 180° OUT OF PHASE 0V VOUT mW VMODSET (b) MODULATING MODSET POUT (d) RESULTING OPTICAL OUTPUT NOTE: ALL AMPLITUDES ARE RELATIVE Figure 2. Modulating BIASSET and MODSET pads 4 _______________________________________________________________________________________ 10Gbps EAM Driver with Integrated Bias Network CLK+ CLK- tSU VIS = 0.1VP-P TO 1VP-P DC-COUPLED 0.1VP-P TO 0.8VP-P AC-COUPLED tHD DATA- VIS DATA+ (DATA+) (DATA-) VID = 0.2VP-P TO 2VP-P DC-COUPLED 0.2VP-P TO 1.6VP-P AC-COUPLED IOUT IMOD = 40mAP-P TO 120mAP-P IBIAS = 0mA TO 50mA NOTE: IOUT RELATES TO RETIMED DATA Figure 3. Setup and Hold Timing Definition GND 50Ω ROUT 50Ω 50Ω OUT 50Ω OSCILLOSCOPE 50Ω 50Ω 50Ω 50Ω PATTERN GENERATOR DATA+ ZL 50Ω DATA- IMOD IBIAS MAX3940 VEE VEE VEE MODSET BIASSET -5.2V 0.1µF 300pF VEE VEE Figure 4. AC Characterization Circuit _______________________________________________________________________________________ 5 MAX3940 Test Circuits and Timing Diagrams (continued) 10Gbps EAM Driver with Integrated Bias Network MAX3940 Test Circuits and Timing Diagrams (continued) VOLTAGE GND VBIAS VMOD VOUT USABLE RANGE VEE + 1.67V BELOW USABLE RANGE Figure 5. Bias and Modulation Relationship to EAM Voltage Typical Operating Characteristics (Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, TA = +25°C, unless otherwise noted.) 10.3Gbps OPTICAL EYE DIAGRAM MAX3940 toc02 MAX3940 toc01 10Gbps ELECTRICAL EYE DIAGRAM (VMOD = 3VP-P, 231 - 1 PRBS) MAX3940 toc03 10Gbps ELECTRICAL EYE DIAGRAM (VMOD = 1VP-P, 231 - 1 PRBS) ASIP, INC. 20ps/div 20ps/div 20ps/div PULSE WIDTH vs. RPWC 160 150 IEE (mA) RETIMING ENABLED 140 130 120 RETIMING DISABLED 110 MEASURED AT 1.25Gbps WITH A 1010 PATTERN 840 830 0 820 810 800 790 780 770 760 100 750 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 6 850 PULSE-WIDTH POSITIVE PULSE (ps) MAX3940 toc04 170 RPWC- (Ω) 2000 1750 1500 1250 1000 750 500 250 MAX3940 toc05 SUPPLY CURRENT vs. TEMPERATURE (50Ω LOAD, EXCLUDES IBIAS, IMOD) 0 250 500 750 1000 1250 1500 1750 2000 RPWC+ (Ω) _______________________________________________________________________________________ 10Gbps EAM Driver with Integrated Bias Network VMOD vs. VMODSET (ZL = 50Ω) PULSE-WIDTH DISTORTION vs. TEMPERATURE 4.0 MAX3940 toc07 4.5 VMODSET IS RELATIVE TO VEE 3.0 2.5 3.5 VMOD (VP-P) PULSE-WIDTH DISTORTION (ps) 3.5 MAX3940 toc06 5.0 3.0 2.5 2.0 1.5 2.0 1.5 1.0 1.0 0.5 0.5 0 0 0.25 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0.50 0.75 1.00 VMODSET (V) TEMPERATURE (°C) VBIAS vs. VBIASSET (ZL = 50Ω) POWER-SUPPLY NOISE REJECTION vs. FREQUENCY -0.2 30 MAX3940 toc09 VBIASSET IS RELATIVE TO VEE MAX3940 toc08 0 25 20 -0.6 PSNR (dB) VBIAS (V) -0.4 -0.8 -1.0 15 10 -1.2 5 -1.4 -1.6 0 0 0.5 1.0 1.5 2.0 2.5 0.1 1 VBIASSET (V) DIFFERENTIAL S11 vs. FREQUENCY 1000 10,000 MAX3940 toc11 0 -5 -10 -20 -25 |S22| (dB) S11 (dB) -10 -15 100 S22 vs. FREQUENCY (DEVICE POWERED) MAX3940 toc10 0 -5 10 FREQUENCY (kHz) -30 -35 -40 -15 -20 -25 -45 -50 -55 -60 -30 -35 -40 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (GHz) 0 2 4 6 8 10 FREQUENCY (GHz) _______________________________________________________________________________________ 7 MAX3940 Typical Operating Characteristics (continued) (Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, TA = +25°C, unless otherwise noted.) 10Gbps EAM Driver with Integrated Bias Network MAX3940 Pad Description PAD NAME FUNCTION BP1, BP2, BP4, BP5, BP7–BP12, BP14, BP15, BP17–BP24, BP26, BP27, BP28 GND Ground. All pads must be connected to board ground. BP3 DATA+ Noninverting Data Input, with 50Ω On-Chip Termination BP6 DATA- Inverting Data Input, with 50Ω On-Chip Termination BP13 CLK+ Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination BP16 CLK- Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination BP25 OUT Driver Output. Provides both modulation and bias output. DC-couple to EAM. BP29 MODEN TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to VEE. BP30 RTEN Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch. BP31 BIASSET Bias Current Set. Apply a voltage to set the bias current of the driver output. BP32 MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output. BP33–BP41 VEE BP42 PWC+ Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section). BP43 PWC- Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width adjustment feature (see the Design Procedure section). BP44 PLRT Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the differential signal polarity. Contains an internal 100kΩ pullup to GND. Negative Supply Voltage. All pads must be connected to VEE. Detailed Description The MAX3940 EAM driver consists of two main parts: a high-speed modulation driver and an EAM-biasing block. The clock and data inputs to the driver are compatible with PECL and CML logic levels. The modulation and bias current are output through the OUT pad. The modulation output stage is composed of a highspeed differential pair and a programmable current source with a maximum modulation current of 120mA. The rise and fall times are typically 23ps. The modulation current is designed to produce an EAM voltage up to 3.0VP-P when driving a 50Ω module. The 3.0VP-P results from 120mAP-P through the parallel combination of the 50Ω EAM load and the internal 50Ω back termination. 8 Polarity Switch The MAX3940 includes a polarity switch. When the PLRT pad is high or left floating, the output maintains the polarity of the input data. When the PLRT pad is low, the output is inverted relative to the input data. Clock/Data Input Logic Levels The MAX3940 is directly compatible with ground-reference CML. Either DC- or AC-coupling may be used for CML referenced to ground. For all other logic types, AC-coupling should be used. Optional Data Input Latch To reject pattern-dependent jitter in the input data, a synchronous differential clock signal should be connected to the CLK+ and CLK- inputs, and the RTEN control input should be connected to VEE. _______________________________________________________________________________________ 10Gbps EAM Driver with Integrated Bias Network Pulse-Width Control The pulse-width control circuit can be used to compensate for pulse-width distortion introduced by the EAM. The differential voltage between PWC+ and PWCadjusts the pulse-width compensation. The adjustment range is typically ±50ps. Optional single-ended operation is possible by forcing a voltage on the PWC+ pad while leaving the PWC- pad unconnected. When PWCis connected to ground, the pulse-width control circuit is automatically disabled. Modulation Output Enable The MAX3940 incorporates a modulation currentenable input. When MODEN is low or floating, the modulation/bias output (OUT) is enabled. When MODEN is high, the output is switched to the logic 0 state. The typical enable time is 2ns and the typical disable time is 2ns. Design Procedure VBIAS ≈ IBIAS × ZL × ROUT ZL + ROUT To program the desired bias current, force a voltage at the BIASSET pad (see the Typical Application Circuit). The resulting IBIAS current can be calculated by the following equation: VBIASSET 36.4Ω IBIAS ≈ The input impedance of the BIASSET pad is typically 20kΩ. Note that the minimum output voltage is VEE + 1.67V (see Figure 5). Programming the Pulse-Width Control Three methods of control are possible when pulse predistortion is desired to minimize distortion at the receiver. The pulse width may be set with a 2kΩ potentiometer with the center tapped to VEE (or equivalent fixed resistors), or by applying a voltage to the PWC+ pad, or by applying a differential voltage across the PWC+ and PWC- pads. See Table 1 for the desired effect of the pulse-width setting. Pulse width is defined as (positive pulse width)/((positive pulse width + negative pulse width)/2). Programming the Modulation Voltage Input Termination Requirement The EAM modulation voltage results from IMOD passing through the EAM impedance (ZL) in parallel with the internal 50Ω termination resistor (ROUT). The MAX3940 data and clock inputs are CML compatible. However, it is not necessary to drive the IC with a standard CML signal. As long as the specified input voltage swings are met, the MAX3940 will operate properly. VMOD ≈ IMOD × ZL × ROUT ZL + ROUT To program the desired modulation current, force a voltage at the MODSET pad (see the Typical Application Circuit). The resulting IMOD current can be calculated by the following equation: IMOD ≈ VMODSET + 37mA 11.1Ω An internal, independent current source drives a constant 37mA to the modulation circuitry and any voltage above VEE on the MODSET pad adds to this. The input impedance of the MODSET pad is typically 20kΩ. Note that the minimum output voltage is VEE + 1.67V (see Figure 5). Programming the Bias Voltage As in the case of modulation, the EAM bias voltage results from IBIAS passing through the EAM impedance (ZL) in parallel with the internal 50Ω termination resistor (ROUT). Applications Information Layout Considerations To minimize loss and crosstalk, keep the connections between the MAX3940 output and the EAM module as short as possible. Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Circuit boards should be made using low-loss dielectrics. Use controlled-impedance lines for the clock and data inputs as well as for the data output. Wafer capacitors are required to filter the VEE supply. Connect the backside of the die to GND. Table 1. Pulse-Width Control PULSE WIDTH RPWC+, RPWC- FOR RPWC+ + RPWC- = 2kΩ VPWC+ (PWC- OPEN) VPWC+ VPWC- 100% RPWC+ = RPWC- VEE + 1V 0V >100% RPWC+ > RPWC- > VEE + 1V >0V <100% RPWC+ < RPWC- < VEE + 1V <0V _______________________________________________________________________________________ 9 MAX3940 The input data is retimed on the rising edge of CLK+. If RTEN is connected to ground, the retiming function is disabled and the input data is directly connected to the output stage. Leave CLK+ and CLK- open when retiming is disabled. MAX3940 10Gbps EAM Driver with Integrated Bias Network RTEN MODEN PLRT 50Ω 50Ω 50Ω 50Ω 50Ω ROUT 50Ω OUT CLK+ VEE CLK- D Q ZL 0 POLARITY MUX PWC DATA+ 1 IMOD DATA50Ω IBIAS 50Ω MAX3940 VEE PWC+ PWC- 2kΩ VEE MODSET BIASSET + + VMODSET - VBIASSET - VEE VEE VEE Figure 6. Functional Diagram Interface Schematics Laser Safety and IEC 825 Figures 7 and 8 show simplified input and output circuits of the MAX3940 EAM driver. Using the MAX3940 EAM driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each customer must determine the level of fault tolerance required by their application, recognizing that Maxim products are not designed or authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application where the failure of a Maxim product could create a situation where personal injury or death may occur. Wire Bonding Die For high-current density and reliable operation, the MAX3940 uses gold metalization. Make connections to the die with gold wire only, using ball-bonding techniques. Minimize bond-wire lengths and ensure that the span between the ends of the bond wire does not come closer to the edge of the die than two times the bond-wire diameter. The minimum length of the bond wires might be constrained by the type of wire bonder used, as well as the dimensions of the die. To minimize inductance, keep the connections from OUT, GND, and VEE as short as possible. This is crucial for optimal performance. 10 ______________________________________________________________________________________ 10Gbps EAM Driver with Integrated Bias Network MAX3940 GND GND 50Ω 50Ω GND MAX3940 MAX3940 50Ω 50Ω DATA+/CLK+ GND 50Ω GND OUT DATA-/CLK- VEE VEE Figure 7. Simplified Input Circuit Chip Topography/ Pad Configuration The origin for pad coordinates is defined as the bottom left corner of the bottom left pad. All pad locations are referenced from the origin and indicate the center of the pad where the bond wire should be connected. Refer to Maxim application note HFAN-08.0.1: Understanding Bonding Coordinates and Physical Die Size for detailed information. Maxim characterized this circuit with gold wire (1-mil diameter wire) ball bonded to the pads. Die pad size is 4 mils (102µm) square, and die thickness is 8 mils (203µm). Figure 8. Simplified Output Circuit Chip Information TRANSISTOR COUNT: 2084 PROCESS: SiGe BIPOLAR SUBSTRATE: SOI DIE THICKNESS: 8 mils ______________________________________________________________________________________ 11 10Gbps EAM Driver with Integrated Bias Network MAX3940 Chip Topography PLRT PWC- PWC+ VEE VEE VEE VEE VEE VEE VEE VEE VEE MODSET BIASSET RTEN MODEN GND GND GND GND GND DATA+ OUT GND GND DATA- GND GND GND GND GND (0, 0) GND GND GND GND CLK+ GND GND CLK- GND GND GND GND GND 2.3mm (90.6 mils) 12 ______________________________________________________________________________________ 1.6mm (63 mils) 10Gbps EAM Driver with Integrated Bias Network COORDINATES (µm) PAD NUMBER PAD NAME X BP1 GND 51.2 BP2 GND 51.2 BP3 DATA+ BP4 GND BP5 GND 51.2 BP6 DATA- BP7 GND BP8 GND COORDINATES (µm) Y PAD NUMBER PAD NAME X Y 933.2 BP23 GND 2028 108.6 807.2 BP24 GND 2028 234.6 51.2 681.2 BP25 OUT 2028 574.8 51.2 555.2 BP26 GND 2028 700.8 429.2 BP27 GND 2028 856.2 51.2 303.2 BP28 GND 2028 982.2 51.2 177.2 BP29 MODEN 1953.8 1140.4 51.2 51.2 BP30 RTEN 1827.8 1140.4 1140.4 BP9 GND 231.8 -63.6 BP31 BIASSET 1701.8 BP10 GND 357.8 -63.6 BP32 MODSET 1575.8 1140.4 BP11 GND 483.8 -63.6 BP33 VEE 1449.8 1140.4 BP12 GND 609.8 -63.6 BP34 VEE 1323.8 1140.4 BP13 CLK+ 769.4 -63.6 BP35 VEE 1197.8 1140.4 BP14 GND 895.4 -63.6 BP36 VEE 1071.8 1140.4 BP15 GND 1021.4 -63.6 BP37 VEE 945.8 1140.4 BP16 CLK- 1147.4 -63.6 BP38 VEE 819.8 1140.4 BP17 GND 1305.2 -63.6 BP39 VEE 693.8 1140.4 BP18 GND 1431.2 -63.6 BP40 VEE 567.8 1140.4 BP19 GND 1606.2 -63.6 BP41 VEE 441.8 1140.4 BP20 GND 1732.2 -63.6 BP42 PWC+ 315.8 1140.4 BP21 GND 1874 -63.2 BP43 PWC- 189.8 1140.4 BP22 GND 2028 -43.8 BP44 PLRT 63.8 1140.4 Package Information For the latest package outline information, go to www.maxim-ic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3940 Table 2. Bondpad Locations