PHILIPS SAA7838H

SAA7838H
One Chip CD Audio Device with integrated MP3/WMA decoder
CE Only Rev. 1.1 — 15 April 2005
IC Datasheet
Document information
Info
Content
Project
cMusIC
Title
cMusIC IC Datasheet for CE Internal Only
Authors
M.Alarakhia/D.Witters/C.Chalk
Document ID
cmusic_ic_datasheet_SAA7838.fm
Document type
Status
Draft
Keywords
Distribution information
Name
Department
Address
cMusIC IC Project
via
cMUSIC System Project Team
via Cobalt cMusIC TeamRoom &
cMusIC web page
c
c
Summary: The SAA7838 cMusIC, is a single chip solution CD audio decoder with
on-chip MP3 and WMA decoding, digital servo, audio DAC, sample rate converter,
pre-amp, laser driver and integrated ARM7TDMI-S microprocessor. The device
contains all required ROM and RAM, including an internal re-programmable flash
ROM, and is targeted at low cost compressed audio CD applications. The design is
derived from the SAA7806 (“MusIC”) one chip CD audio decoder IC, with additions to
allow low cost system implementation of MP3 and WMA decoding.
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 ................ Formats.......... .............................................................................. 6
3
Pinning information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 ................ Pinning list..... .............................................................................. 7
3.2 ................ Pinning diagram........................................................................... 10
4
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 ................ Analogue Data Acquisition........................................................... 13
6.1.1
LF Acquisition .............................................................................. 13
6.1.2
HF Acquisition.............................................................................. 15
6.2 ................ Analogue Clock Generation......................................................... 18
6.3 ................ General Purpose Analogue Inputs............................................... 19
6.4 ................ Auxiliary Analogue Inputs ............................................................ 19
6.5 ................ Channel Decoder......................................................................... 22
6.5.1
Features........ .............................................................................. 22
6.5.2
Block Diagram ............................................................................. 22
6.5.3
Clock Control .............................................................................. 25
6.5.4
Decoder-ARM Microprocessor Interface ..................................... 27
6.5.4.1
Programming interface ................................................................ 27
6.5.4.2
Interrupt Strategy ......................................................................... 27
6.5.5
EFM bit detection and demodulation ........................................... 28
6.5.5.1
Signal Conditioning...................................................................... 28
6.5.5.2
Bit Detector .............................................................................. 36
6.5.5.3
Limiting the PLL frequency range ................................................ 40
6.5.5.4
Run length 2 push-back detector................................................. 41
6.5.5.5
Available signals for monitoring ................................................... 41
6.5.5.6
Use of jitter measurement............................................................ 42
6.5.5.7
Internal lock flags......................................................................... 42
6.5.5.8
Format of the measurements signal on MEAS1 pin .................... 43
6.5.5.9
Demodulator .............................................................................. 44
6.5.5.10
EFM Demodulation ...................................................................... 44
6.5.5.11
Sync detection & synchronisation................................................ 44
6.5.5.12
Sync protection ............................................................................ 44
6.5.6
CD decoding . .............................................................................. 45
6.5.6.1
General Description of CD-Decoding .......................................... 45
6.5.6.2
Q-channel subcode interface....................................................... 45
6.5.6.3
CD-TEXT interface ...................................................................... 46
6.5.7
Main Data Decoding .................................................................... 47
6.5.7.1
Data processing........................................................................... 47
6.5.7.2
Data Latency + FIFO operation ................................................... 48
6.5.7.3
risky and safe correction modes .................................................. 48
6.5.8
Error corrector statistics............................................................... 49
6.5.8.1
CFLG
.............................................................................. 49
6.5.8.2
BLER counters............................................................................. 50
6.5.9
Audio backend + data output interfaces ...................................... 50
6.5.9.1
Audio processing ......................................................................... 50
6.5.9.2
Interpolate and hold ..................................................................... 51
6.5.9.3
Soft mute and error detection ...................................................... 51
6.5.9.4
Hard mute on EBU....................................................................... 52
6.5.9.5
Silence detection and kill generation ........................................... 52
6.5.9.6
Deemphasis filter ......................................................................... 52
6.5.9.7
Upsample filter (4 times).............................................................. 53
6.5.9.8
Data output interfaces.................................................................. 53
12NC
IC Datasheet
© Philips Electronics N.V. 2002. All rights reserved.
Rev. 1.1 — 15 April 2005
2 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
6.5.9.9
IIS interface ..............................................................................
6.5.9.10
subcode(V4) interface..................................................................
6.5.10
Motor............. ..............................................................................
6.5.10.1
Frequency setpoint ......................................................................
6.5.10.2
Position error ..............................................................................
6.5.10.3
Motor control loop gains (KP, KF and KI) ....................................
6.5.10.4
Operation modes .........................................................................
6.5.10.5
Writing, reading motor integrator value........................................
6.5.10.6
Some notes on application motor servo ......................................
6.5.10.7
Tacho
..............................................................................
6.6 ................ Digital Servo - PDSIC ..................................................................
6.6.1
PDSIC Registers and servo RAM control ....................................
6.6.2
Diode Signal Processing..............................................................
6.6.3
Signal Conditioning......................................................................
6.6.4
Focus Servo System....................................................................
6.6.4.1
Focus Start Up.............................................................................
6.6.4.2
Focus Position Control Loop........................................................
6.6.4.3
Dropout detection ........................................................................
6.6.4.4
Focus loss detection and fast restart ...........................................
6.6.4.5
Focus loop gain switching............................................................
6.6.4.6
Focus automatic gain control loop ...............................................
6.6.5
Radial servo system ....................................................................
6.6.5.1
Radial PID - On-Track Mode .......................................................
6.6.5.2
Level initialization.........................................................................
6.6.5.3
Dropout detection ........................................................................
6.6.5.4
Focus loss detection and fast restart ...........................................
6.6.5.5
Focus loop gain switching............................................................
6.6.5.6
Focus automatic gain control loop ...............................................
6.6.6
Radial servo system ....................................................................
6.6.6.1
Level initialization.........................................................................
6.6.6.2
Sledge control..............................................................................
6.6.6.3
Tracking control ...........................................................................
6.6.6.4
Access
..............................................................................
6.6.6.5
Radial automatic gain control loop...............................................
6.6.7
Off-track counting ........................................................................
6.6.8
Defect detection...........................................................................
6.6.9
Off-track detection .......................................................................
6.6.10
High level features .......................................................................
6.6.10.1
Automatic error handling..............................................................
6.6.10.2
Automatic sequencers and timer interrupts .................................
6.6.11
Driver interface ............................................................................
6.7 ................ Flexible servo options ..................................................................
6.7.1
Modes of operation ......................................................................
6.7.2
Hardware servo only....................................................................
6.7.2.1
Hardware servo with fine offset compensation ............................
6.7.2.2
Fully flexible servo .......................................................................
6.7.2.3
Pre-processing with hardware servo ...........................................
6.7.2.4
Hardware servo with post-processing..........................................
6.7.2.5
Pre-processing with hardware servo plus post-processing .........
6.8 ................ BLOCK DECODER......................................................................
6.8.1
Supported modes of operation ....................................................
6.8.2
Channel decoder to Block decoder Interface(C2I).......................
6.8.3
Block decoder to Segmentation manager interface.....................
6.9 ................ Segmentation Manager ...............................................................
6.9.1
General ......... ..............................................................................
6.9.2
Interrupt Generation.....................................................................
6.9.3
Segmentation buffer ARM subsystem Interface ..........................
6.10 .............. Laser interface .............................................................................
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IC Datasheet
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© Philips Electronics N.V. 2002. All rights reserved.
Rev. 1.1 — 15 April 2005
3 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
7
ARM7 System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.1 ................ ARM7TDMI-S Microprocessor..................................................... 81
7.2 ................ Static memory Interface Unit (SMIU) ........................................... 82
7.3 ................ Program ROM Interface............................................................... 82
7.4 ................ Boot Rom Interface...................................................................... 82
7.5 ................ Embedded KFlash Interface ........................................................ 83
7.6 ................ RAM Interface.............................................................................. 83
7.7 ................ I2C Interface.. .............................................................................. 84
7.8 ................ General Purpose I/O’s ................................................................. 84
7.9 ................ Interrupt Controller....................................................................... 84
7.10 .............. 2 x UART Interfaces .................................................................... 84
7.11 .............. 2 x Timers...... .............................................................................. 85
7.12 .............. Watch Dog Timer......................................................................... 85
7.13 .............. Real Time Clock .......................................................................... 85
7.14 .............. DMA Controller ............................................................................ 86
7.15 .............. Backend audio processing........................................................... 86
7.15.1
Parallel to Serial I2S conversion.................................................. 86
7.15.2
Variable sample rate converter.................................................... 87
7.15.3
EBU Interface .............................................................................. 87
8
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.1 .............. Introduction to soldering surface mount packages ...................... 96
14.2 .............. Reflow soldering .......................................................................... 96
14.3 .............. Wave soldering ............................................................................ 97
14.4 .............. Manual soldering ......................................................................... 97
14.5 .............. Package related soldering information ........................................ 98
15
Datasheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
18
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
19
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1. General description
The SAA7838 (“cMusIC”), is a single chip solution CD audio decoder with on-chip
MP3 and WMA decoding, digital servo, audio DAC, sample rate converter, pre-amp,
laser driver and integrated ARM7TDMI-S microprocessor. The device contains all
required ROM and RAM, including an internal re-programmable flash ROM, and is
targeted at low cost compressed audio CD applications. The design is derived from
the SAA7804 (“MusIC”) one chip CD audio decoder IC, with additions to allow low
cost system implementation of MP3 and WMA decoding.
12NC
IC Datasheet
© Philips Electronics N.V. 2002. All rights reserved.
Rev. 1.1 — 15 April 2005
4 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
2. Features
„ Channel decoder and digital servo based on SAA7804 MusIC design.
„ 32bit embedded ARM7 RISC microprocessor supporting both 32bit and 16bit
(“Thumb”) instruction sets.
„ Maximum ARM operating frequency of 76MHz, equivalent to 68MIPS.
„ Decoding of compressed audio stream (MP3/WMA) on ARM7 core.
„ All memories required for MP3/WMA decoding embedded on chip: combination of
130kB mask programmed internal programme ROM (to reduce wait states on
high speed code, e.g. decompression algorithms), 42kB boot ROM, 64kB of
internal re-programmable flash ROM (for simple re-programming of application
code). 110kB internal SRAM.
„ Programmable clock frequency for ARM microprocessor - allowing users to
trade-off power consumption and processing power depending on requirements.
„ Block decoder hardware to perform C3 error correction.
„ Sample rate converter circuit to convert compressed audio sample rates (in range
8kHz to 48kHz) to an output rate 44.1kHz.
„ Microprocessor access to digital representations of the diode input signals from
the optical pick up. The micro can also generate the servo output signals RA, FO,
SL, allowing the possibility of additional servo algorithms in software.
„ Programmable PDM outputs (effectively sine and cosine) to allow use of stepper
motor for sledge mechanism.
„ Microprocessor access to audio streams, both from the internal CD decoder and
an external stereo auxiliary input (e.g. an analogue source from a tuner, converted
to digital via on-chip ADC’s) to allow audio processing algorithms in the ARM
micro, e.g. bass boost, volume control.
„ Four general purpose analogue inputs (A_IN_1 to A_IN_4) allowing the ARM
micro access to other external analogue signals, e.g. low cost keypad,
temperature sensor, via on-chip ADC’s
„ Two additional analogue audio inputs (AUX_L, AUX_R) to allow the ARM micro
access to external audio signals (e.g. tuner). Allows audio algorithms (e.g. bass
boost) to be performed on external audio signals.
„ Real Time Clock operated from separate 32kHz crystal. Allows low power standby
mode with real time clock still operational.
„ Watchdog timer.
„ IIS, SP-DIF, subcode (V4) and subcode sync outputs.
„ 32 GPIO’s
„ Two standard UART channels
„ Two external interrupt pins
„ IIC interface configurable for master or slave modes, supporting 100kbits/sec and
400kbits/sec standards.
„ Slave IIS mode in which the channel decoder can synchronise the CD playback
speed to an input IIS clock.
„ Integrated digital HF/Mirror detector with measurement of min and max peak
values, amplitude and offset.
„ Integrated CD-Text decoder.
„ Up to 6x decode speed, CLV or CAV modes.
12NC
IC Datasheet
© Philips Electronics N.V. 2002. All rights reserved.
Rev. 1.1 — 15 April 2005
5 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
„ QFP100 package with 0.65mm pin pitch.
„ Separate left and right channel digital silence detect available on KILL pins.
„ Digital silence detection available on loopback data from external source as well
as internal data.
„ “Filterless” pseudo-bitstream audio DAC with minimal external components.
„ Stereo line outputs for audio DAC.
„ Loop back mode allowing the use of integrated DAC with external IIS/EIAJ
sources.
„ Compatible with voltage mode mechanisms.
„ On chip buffering and filtering of the diode signals from the mechanism in order to
optimise the signals for the decoder and servo parts.
„ LF(Servo) signals converted to digital representations by Sigma-Delta ADC’s
shared between pairs of channels to minimise dc offset between channels.
„ HF part summed from signals D1-D4 and converted to digital signals by HF 6 bit
ADC.
„ Selectable DC offset cancellation of quiescent mechanism voltages and dark
currents, digitally controlled. Additional fine DC offset cancellation in digital
domain.
„ Eye pattern monitor system to observe selectable points within the analogue
pre-amp.
„ Current and average jitter values available via registers.
„ On chip laser power control, up to maximum currents of 120 mA.
„ Laser on-off control, including “soft” start control - zero to nominal output power in
1ms.
„ Monitor control and feedback circuit to maintain nominal output power throughout
the life of laser.
„ Configured for Nsub monitor diode.
„ JTAG interface for device access and ARM code development (compatible with
ARM multi-ICE).
„ All digital input pins 5V tolerant.
2.1 Formats
Read of the following CD-Decode formats
„ CD-R
„ CD-RW
„ CD-DA (red book)
„ CD-ROM(Mode 1 and Mode 2)
„ CD-MP3
„ CD-WMA
„ Video CD
„ SACD (CD layer only)
„ Support 80 .. 100 minute CD playback
„ Multi-session discs
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IC Datasheet
© Philips Electronics N.V. 2002. All rights reserved.
Rev. 1.1 — 15 April 2005
6 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
3. Pinning information
3.1 Pinning list
Table 1:
Pinning List
Symbol
Pin
Type
Main Function
SL_SIN
1
O
Sledge actuator/ stepper motor PDM output (sine)
GPIO31_COS
2
B
general purpose I/O / stepper motor PDM output (cosine)
LPOWER
3
P
Laser power supply
LASER
4
P
Laser Drive
MONITOR
5
AI
Laser monitor diode
VSSA1
6
P
Analogue Ground
HF_MON
7
AIO
HF monitor output signal
VDDA1
8
P
Analogue Supply
D1
9
AI
Diode voltage input (central diode signal input)
D2
10
AI
Diode voltage input (central diode signal input)
D3
11
AI
Diode voltage input (central diode signal input)
D4
12
AI
Diode voltage input (central diode signal input)
R1
13
AI
Diode voltage input (satellite diode signal input)
R2
14
AI
Diode voltage input (satellite diode signal input)
AUX_L
15
AI
Auxiliary audio left input
AUX_R
16
AI
Auxiliary audio right input
VDDA2
17
P
Analogue Supply
OPU_REF_OUT
18
AO
OPU reference voltage
VSSA2
19
P
Analogue Ground
OSCOUT
20
AO
Crystal/resonator output
OSCIN
21
AI
Crystal/resonator input
VDDA3
22
P
Analogue supply
DAC_LP
23
AO
Audio DAC left channel differential output (positive)
DAC_LN
24
AO
Audio DAC left channel differential output (negative)
DAC_VREF
25
AIO
Audio DAC decoupling point (10uF//100nF to ground)
DAC_RN
26
AO
Audio DAC right channel differential output (negative)
DAC_RP
27
AO
Audio DAC right channel differential output (positive)
DAC_FGND
28
P
Audio DAC floating ground
VSSA3
29
P
Analogue ground
OSC_32K_IN
30
AO
32kHz crystal input
OSC_32K_OUT
31
AO
32kHz crystal output
VDDD1
32
P
Digital Core Supply 1
A_IN_GPIO0
33
AIB
Analogue input 1/general purpose I/O
A_IN_GPIO1
34
AIB
Analogue input 2/general purpose I/O
A_IN_GPIO2
35
AIB
Analogue input 3/general purpose I/O
A_IN_GPIO3
36
AIB
Analogue input 4/general purpose I/O
VSSD1
37
P
Digital Core ground 1
12NC
IC Datasheet
Comments
© Philips Electronics N.V. 2002. All rights reserved.
Rev. 1.1 — 15 April 2005
7 of 102
SAA7838
Philips Semiconductors
IC Datasheet
Table 1:
One Chip CD Audio Device with Integrated MP3/WMA decoder
Pinning List…continued
Symbol
Pin
Type
Main Function
TX_GPIO4
38
B
UART transmit/general purpose I/O
RX_GPIO5
39
B
UART receive/general purpose I/O
TX2_GPIO6
40
B
UART2 transmit/general purpose I/O
RX2_GPIO7
41
B
UART2 receive/general purpose I/O
SDA
42
B
Micro interface data I/O line (open drain output)
SCL
43
B
Micro interface clock line
LKILL
44
O
Kill output for left channel (configurable as open drain)
RKILL
45
O
Kill output for right channel (configurable as open drain)
VSSP1
46
P
Digital ground 1 for periphery (pads)
DOBM
47
O
Bi-phase mark otuput (no external buffer required)
VDDP1
48
P
Digital supply 1 for periphery (pads)
GPIO8_INT2
49
B
General purpose I/O / external interrupt 2
GPIO9
50
B
General purpose I/O
GPIO10
51
B
General purpose I/O
GPIO11
52
B
General purpose I/O
GPIO12
53
B
General purpose I/O
GPIO13
54
B
General purpose I/O
GPIO14
55
B
General purpose I/O
GPIO15
56
B
General purpose I/O
GPIO16_SDI
57
B
General purpose I/O / serial data input (loopback)
GPIO17_WCLI
58
B
General purpose I/O / serial word clock input (loopback)
GPIO18_SCLI
59
B
General purpose I/O / serial bit clock input (loopback)
VSSD2
60
P
Digital core ground 2
VDDD2
61
P
Digital core supply 2
GPIO19_T1
62
B
General purpose I/O / tacho input 1 (for spindle motor sensor)
GPIO20_T2
63
B
General purpose I/O / tacho input 2(for spindle motor sensor)
GPIO21_T3
64
B
General purpose I/O / tacho input 3(for spindle motor sensor)
GPIO22_PWM1_CA 65
P1
B
General purpose I/O / timer PWM output1 / capture input1
GPIO23_PWM2_CA 66
P2
B
General purpose I/O / timer PWM output2 / capture input2
GPIO24_PWM3_CA 67
P3
B
General purpose I/O / timer PWM output3 / capture input3
GPIO25_PWM4_CA 68
P4
B
General purpose I/O / timer PWM output4 / capture input4
GPIO26_MEAS
69
B
General purpose I/O / channel decoder telemetry output
GPIO27_CFLG
70
B
General purpose I/O / channel decoder correction statistics
GPIO28_CL1
71
B
General purpose I/O / clock output for sampling channel
decoder telemetry outputs
GPIO29
72
B
General purpose I/O
VSSP2
73
P
Digital ground 2 for periphery (pads)
RESET
74
IUH
Power on reset (Active low)
12NC
IC Datasheet
Comments
© Philips Electronics N.V. 2002. All rights reserved.
Rev. 1.1 — 15 April 2005
8 of 102
SAA7838
Philips Semiconductors
IC Datasheet
Table 1:
One Chip CD Audio Device with Integrated MP3/WMA decoder
Pinning List…continued
Symbol
Pin
Type
Main Function
VDDP2
75
P
Digital supply 2 for periphery (pads)
INT1
76
I
External interrupt 1
VSSD3
77
P
Digital core ground 3
VDDD3
78
P
Digital core supply 3
EF
79
O
C2 error flag
DATA
80
O
Serial data output
WCLK
81
O
Word clock output
SCLK
82
O
Serial clock output
SYNC
83
O
EFM frame synchronisation
V4_CL16
84
B
Versatile pin 4/clock output 16.9344MHz
TDI
85
IU
JTAG1/2 test data input
TMS
86
IU
JTAG1/2 test mode select
TCK
87
IDH
JTAG1/2 test clock
TRST
88
IU
JTAG1/2 asyncronous reset (active low)
TDO
89
O
JTAG1/2 test data output
ARM_JTAG_SEL
90
I
Select between ARM JTAG and general JTAG
GPIO30_RTCK
91
B
General purpose I/O / JTAG clock output
DEV_ROM
92
ID
Development ROM select (low = internal ROM)
VSSD4
93
P
Digital core ground 4
VDDD4
94
P
Digital core supply 4
MOTO1
95
O
Motor output 1
MOTO2
96
O
Motor output 2
VSSP3
97
P
Digital ground 3 for periphery (pads)
VDDP3
98
P
Digital supply 3 for periphery (pads)
RA
99
O
Radial actuator
FO
100
O
Focus actuator
Comments
Table 2: Pin type definition…continued
All
digital inputs and bidirectional
pins are 5V tolerant
Type
Definition
AI
analogue input
AO
analogue output
AIO
analogue input/output
IH
digital input with hysteresis
ID
digital input with pull-down
IDH
digital input with pull-down & hysteresis
IU
digital input with pull-up
IUH
digital input with pull-up & hysteresis
O
digital output, slew rate limited
B
digital bi-directional, slew rate limited
P
power connection
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SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
61
60
59
58
57
56
55
54
53
52
51
62
VSSP2
GPIO29
GPIO28_CL1
GPIO27_CFLG
GPIO26_MEAS
GPIO25_PWM4_CAP4
GPIO24_PWM3_CAP3
GPIO23_PWM2_CAP2
GPIO22_PWM1_CAP1
GPIO21_T3
GPIO20_T2
GPIO19_T1
VDDD2
VSSD2
GPIO18_SCLI
GPIO17_WCLI
GPIO16_SDI
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
SAA7838H
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
GPIO9
GPIO8_INT2
VDDP1
DOBM
VSSP1
RKILL
LKILL
SCL
SDA
RX2_GPIO7
TX2_GPIO6
RX_GPIO5
TX_GPIO4
VSSD1
A_IN_GPIO3
A_IN_GPIO2
A_IN_GPIO1
A_IN_GPIO0
VDDD1
OSC_32K_OUT
DAC_RP
DAC_FGND
VSSA3
OSC_32_IN
R1
R2
AUX_L
AUX_R
VDDA2
OPU_REF_OUT
VSSA2
OSCOUT
OSCIN
VDDA3
DAC_LP
DAC_LN
DAC_VREF
DAC_RN
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SOT317-2
SL_SIN
GPIO31_COS
LPOWER
LASER
MONITOR
VSSA1
HF_MON
VDDA1
D1
D2
1
MOTO1
MOTO2
VSSP3
VDDP3
RA
FO
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D3
D4
WCLK
SCLK
SYNC
V4_CL16
TDI
TMS
TCK
TRSTn
TDO
ARM_JTAG_SEL
GPIO30_RTCK
DEV_ROM
VSSD4
VDDD4
2
3
4
5
6
7
8
9
10
11
80
DATA
EF
VDDD3
VSSD3
INT1
VDDP2
RESETn
3.2 Pinning diagram
Fig 1. SAA7838 Pinning Diagram
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SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
HF ADC
4. Block Diagrams
CHANNEL DECODER
LF Analogue ADC’s
General PurposeADC’s
EBU
INTERFACE
CHANNEL
CLOCK
CONTROL
REG
INTERFACE
AHB
Address
Decoder
REG
INTERFACE
AHB
INTERFACE
Flexi Servo
Interface.
ARM7 CPU
REG
INTERFACE
2xTimer
SMIU
2xUart
AHB INT
Audio
Dac Line
Outputs
AHB 2 VPB
Flash (64KB
AHB REGs
Analogue
Laser
Driver
DMA
Controller
Boot Rom
(42KB)
Sledge Stepper
Motor Driver.
General
Purpose
ADC Proc.
AHB INT
AHB INT
Prog
Rom(130KB)
SERVO
Clock
Analogue
PLL
C3 ERCO
I2S OUTPUT
MOTOR
CONTROL
DIGITAL
SERVO
BLOCK
BUFFER
Parallel INPUT and
OUTPUT INTERFACES
Parallel
DATA
INTERFACE
DIGITAL
DECODER
SEG. MAN
BLOCK DECODER
Ram(110KB)
Interrupt Ctrl
Clock Control
WDT
RTC
I2C
GPIO
Audio Proc.
Buffer
EBU
SRC
VPB SUB-SYSTEM
MULTI LAYER AHB SUB-SYSTEM
Fig 2. SAA7838 Top Level Block Diagram
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11 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
5. Limiting values
Table 3:
Absolute maximum ratings
Symbol Parameter
Conditions
Min
Max
Units
VDDD
supply voltage (digital)
-0.5
+2.5
V
VDDP
supply voltage (periphery)
-0.5
+3.6
V
VDDA
supply voltage (analogue)
-0.5
+3.6
V
VIN
input voltage
-0.5
VDDA + 0.5
V
-0.5
5.5
V
-55
+125
oC
-
TBD
mW
analogue inputs
VIFVT
input voltage
digital
tstg
storage temperature
Ptot
total power dissipation
inputs [1]
Playing Disc at 2X
in CD-MP3 Mode
[1]
All digital input and bidirectional pins are 5V tolerant
[2]
Maximum absolute voltage at receiver inputs during transient conditions. Transient voltage time
durations shall be limited to Tsettle,CM (10ms maximum).
Table 4:
Recommended operating conditions
Symbol
Parameter
Conditions Min
Typ
Max
Units
VDDD
supply voltage (digital core)
1.65
1.80
1.95
V
VDDP
supply voltage (pads)
3.0
3.3
3.6
V
VDDA
supply voltage (analogue)
3.0
3.3
3.6
V
tamb
operating ambient temperature
-
25
-
oC
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12 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
6. Functional description
6.1 Analogue Data Acquisition
The input signals from the OPU photodiodes contain information used in the servo
loops and the high frequency data from which the audio samples are reconstructed.
The SAA7838 contains all the necessary circuitry to process the photodiode signals
directly and hence removes the need for a separate external diode signal
pre-amplifier.
6.1.1
LF Acquisition
The LF signal path acquires the photodiode voltage signals and converts them into
4MHz Pulse-Density-Modulated digital data streams. These streams are processed
within the digital servo to control the focus, radial and sledge loops.
The servo processing makes use of the difference calculations D1-D2, D3-D4 and
R1-R2. Ideally these differences should be zero when the quantities D1..R2 due to
the laser illumination are equal. However in a practical system, errors reduce the
accuracy of the signal processing. Two main forms of errors exist - dc offsets and
relative gain mismatch between the differenced channels.
The dc offsets are minimised in SAA7838 by dc offset compensation circuitry which
allows the dc present in the PDM streams to be measured when the laser is
switched-off, and then subtracted in the digital domain from the signals when the
laser is on.
Relative gain mismatch is minimised by using carefully scaled circuitry in the time
continuos parts of the signal path, and by time sharing circuitry in the time discrete
parts. A simplified block diagram of the LF acquisition path is shown in Fig 3.
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IC Datasheet
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Objective Spec
cMusIC (SAA7838)
One Chip CD Audio Device with Integrated MP3/WMA decoder
Rev. 1.1 — 15 April 2005
14 of 102
© Philips Electronics N.V. Year. All rights reserved.
Fig 3. LF Acquisition Block Diagram
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
The output of the OPU is converted to a current across the input resistor. The current
conveyor provides a low input impedance and a high output impedance and sets a
virtual earth at the end of the V to I converter to the same voltage as Vref (1.6V).
The level shifter’s purpose is to act as a summing node for the DC cancellation and to
produce a current that is referenced to an internal bias voltage and so is independent
of Vref.
The output current charges up an integration capacitor. When the voltage hits Vdda/2
the comparator switches and sends a feedback current that is in the opposite polarity
to the input current to try to discharge the capacitor.
The register LFADCGain defines the amount of feedback current and so sets the
gain of the ADC. A PDM (pulse density modulation) waveform is the output of the
ADC. The output of the ADC is passed through a low pass filter (in the digital domain)
and the average value at the output of the filter is in proportion to the voltage between
Vin and Vref.
The same ADC structures are used for the auxiliary analogue inputs, AUX_L and
AUX_R and the general purpose analogue inputs, A_IN_1, A_IN_2, A_IN_3 and
A_IN_4. These inputs are accessible from device pins GPIO0, GPIO1, GPIO2, and
GPIO3 respectively. There are 2 General purpose ADC and therefore the 4 inputs are
internally multiplexed. A_IN_1 and A_IN_3 are multiplexed to access general
purpose ADC1 and A_IN_2 and A_IN_4 are multiplexed to access general purpose
ADC2. The ADC’s used by the auxiliary analogue inputs are muxed with the D1 and
D2 inputs. The registers to control the internal multiplexor for Aux Inputs and general
purpose ADC’s is AuxandGPADCControl
6.1.2
HF Acquisition
The HF data (EFM) signal is obtained by summing the signals from the 3 or 4 central
diodes of the OPU, filtering the signals and converting to a digital representation via a
6 bit HF ADC. Fig 4. shows a simplified block diagram of the HF path.
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IC Datasheet
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15 of 102
20k
D2
20k
D3
20k
D4
20k
A
B
High Pass
Filter
RF AMP 1
RF AMP 2
Philips Semiconductors
D1
0 to 12dB
Register
AGCGain<3:0>
C
IC Datasheet
12NC
Objective Spec
0dB to 24dB
Register AGCGain<7:4>
Register
RFControl2<5>
20k
D
80k
noise_filt_sel
G
20k
Register
RFControl2<1>
E
80k
Register
OffsetComp<5:0>
decoded to
<31:0>
H
Register
RFControl1<3:0>
67.7376MHz
sys_clk
Register
RFControl2<2>
Register
RFControl2<4>
16 of 102
© Philips Electronics N.V. Year. All rights reserved.
rf_mon
amp
Register
RFControl1<6:4>
G
Register
RFControl2<3>
Fig 4. HF Acquisition Block Diagram
rf_adc_out<5:0>
to
Channel Decoder
F
E
D
C
B
A
67.7376MHz from
PLL
cMusIC (SAA7838)
HF_MON
6 bit RF
ADC
noise
filter
20k
One Chip CD Audio Device with Integrated MP3/WMA decoder
Rev. 1.1 — 15 April 2005
Register RFControl2<1>
Register
RFControl2<0>
Single ended to
differential
converter
4X
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
The four diode signals D1, D2, D3 and D4 are summed in the first RF amplifier. The
gain of the first amplifier is controlled by register AGCGain, bits 7:4.
A second gain stage has been added to lessen the gain bandwidth requirements of a
single gain stage opamp and also to act with the Dynamic AGC (Automatic gain
control). The gain of this amplifier is set with register AGCGain, bits 3:0 and can be
changed on the fly from the ARM Micro. The gain range was chosen to accommodate
12dB of gain needed to boost the signal as the laser tracks across a finger print
defect on the disc.
For CD-R, CR-RW and finger prints not only does the AC signal reduce in amplitude
compared to a perfect pressed disk but also the DC pedestal voltage will reduce. The
high pass filter will remove all dc present at the input but offsets would be added by
the second and third gain stages.
A 5 bit plus sign DAC controlled by register OffsetComp, bits 5:0.
”OffsetCompValue<5:0>” adds a current to compensate for this offset. The amount of
current will reduce in dB linear states and will track the AC gain.
To help users of the IC set-up the correct gain and DC offset for each particular
mechanism an eye pattern monitor facility has been included. This consists of a high
frequency buffer amplifier whose input can be selected to monitor various important
nodes within the analogue RF path. The monitor point is controlled by register
RFControl1, bits 6:4 RFMonSel. The output of the buffer drives HF_MON pin (pin 7).
This register also controls the roll-off frequency of the noise filter which sits in front of
the 6bit ADC in the RF path.
Various blocks within the analog RF path can be powered down if required, including
the complete path. These power down bits are controlled by register RFControl2,
bits 5:0.
In addition, the 6 bit RF ADC can be tested stand alone in application mode or a
separate external RF path IC can be connected to SAA7838 by selecting bit1 of this
register, “RFBypassSel”. The input for the RF signal is then through the HF_MON pin.
In this mode the centre diode summing circuit, RF amp1, high pass filter and RF
amp2 are all bypassed.
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IC Datasheet
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17 of 102
0
1
OSC
Register CLKGEN
CTRL<5>
0
osc_comp_out
1
0
HF
ADC
1
clk multiplier
8x
Used for Internal Test
adac_in_8_clk
Register CLKGEN
CNTRL<3>
AUDIO
DAC
Register CLKGEN
CNTRL<0>
0
1
clk multiplier
variable ratio
Used for Internal Test
18 of 102
© Philips Electronics N.V. Year. All rights reserved.
Register CLKGEN
CNTRL<2>
OSC
Fig 5. Analogue Clock Generation
micro_clk(152Mhz)
sys32k_clk
(Real Time
Clock)
cMusIC (SAA7838)
Register CLKGEN
CNTRL<1>
lfadc8m_clk
(Digital Servo)
One Chip CD Audio Device with Integrated MP3/WMA decoder
Rev. 1.1 — 15 April 2005
1/2
Register
AnaClockPLLCo
ntrol<3>
Philips Semiconductors
pad_clk3v3
pad_clk1v8
(Used for
Internal
Test)
Register
AnaClockPL
LControl<0>
Register CLKGEN
CNTRL<4>
pad_clk3v3
Analogue to Digital
Interface
Analogue Front End
Clocking Strategy
PADS
IC Datasheet
12NC
Objective Spec
6.2 Analogue Clock Generation
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
The SAA7838 consists of 2 analogue Phase Lock Loops. The 67Mhz PLL is
dedicated for the channel decoder. The 152MHz PLL is dedicated for the rest of the
functionalily. The clock strategy for SAA7838 aims at addressing areas that are prone
to noise affects that can decrease the quality of audio. The clocks related to audio
DAC, LF ADC are generated directly from the analogue, instead of being derived
from high frequency PLL’s.Figure 7 depicts the clocking strategy for the digital core.
6.3 General Purpose Analogue Inputs
The Four general-purpose ADC inputs(GPIO0 pin 33, GPIO1 pin 34, GPIO2 pin 35,
and GPIO3 pin 36) can be used for giving the ARM microprocessor access to external analogue sources, e.g. for monitoring temperature and to provide simple
resister-ladder keypad functionality. These inputs use an additional pair of
sigma-delta ADC’s identical to those used for the LF diode inputs.
The general purpose analogue inputs have separate interrupt request lines and use
address space in the servo registers for storing the converted digital values. The output of the general-purpose ADCs are low-pass filtered and can have fine offset compensation added before being passed to a decimation filter. The digital values output
of the decimation filter are then captured in the servo registers with 10 bit resolution
per channel.
There are only two ADCs for general purpose application and so each ADC is
multiplexed between two inputs. ADC1 between GPIO0 and GPIO2 and ADC2
between GPIO1 and GPIO3. The signal that selects GPIO2 and GPIO3 inputs is
AuxControlandGPADC.
6.4 Auxiliary Analogue Inputs
Two further analogue inputs, AUX_L and AUX_R, are available with sufficient resolution for inputting external audio sources, e.g. for allowing ARM access to an external
audio source for sound processing algorithms.
This allows audio processing of external audio sources via the AUX pins, whilst
simultaneously using the general purpose inputs for keyboard and temperature
inputs.
Since these two inputs share one pair of the LF sigma-delta ADC’s used in the LF
path (for inputs D1 and D2) a multiplexer is used to control the data source into the
ADC’s. (Therefore, D1 and D2 cannot be used at the same time as AUX_IN_L and
AUX_IN_R.) This path is designed for a tuner input where the THD specification is
~0.3% and the SNR is < 60dB. These performance figures are below that available
when the normal CD-Audio path is used i.e. SNR > 80Db and THD < 0.01%.
The audio data is converted to a pulse density modulated digital stream for both input
channels. This data is then low pass filtered and decimated to produce 10 bit representations of the analogue inputs.
The auxiliary input is different from the general purpose analogue inputs in that the
parallel data is converted to an I2S format stream and then sent to the I2S handler
block which makes the data available to the ARM micro.The I2S handler contains a
12 deep size data FIFO which means the ARM micro does not have to service the
audio data with as high a priority as it would if it were directly registered. Refer to Fig
6.
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IC Datasheet
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Rev. 1.1 — 15 April 2005
19 of 102
Aux L
S2
C
DSIC
ADC
ENB
S1
Aux R
S2
D1 or
Aux L
Decimation
Filters
LPF
D2 or
Aux R
D2 or
Aux R
Multiplexer
D2
D1 or
Aux L
Serial
Out
D2 or
Aux R
D
WCLK
C
ENB
Key
10 bit samples of Aux L & Aux R
expanded to 16 bits by adding six
LSB's
Internal
signal
BCLK
Data
Device Pin
20 of 102
© Philips Electronics N.V. Year. All rights reserved.
Fig 6. Auxiliary Analogue Inputs Block Diagram
cMusIC (SAA7838)
VPB Bus
Block used to route I2S
to Audio DAC or pins
One Chip CD Audio Device with Integrated MP3/WMA decoder
Rev. 1.1 — 15 April 2005
Spare Reg A
lf_auxin_sel
D1 or
Aux L
D
I2S Router
S1
Philips Semiconductors
IC Datasheet
12NC
Objective Spec
Multiplexer
D1
Osc in
Osc out
4.2336 MHz Audio DAC Clock
Clock
Generator
ARM/AHB
Clock
Generator
32KHz Clock
Analogue Clock
Generator
CD Slim
Block
Decoder
Philips Semiconductors
32Khz_out
IC Datasheet
12NC
Objective Spec
32Khz_in
AHB
Regs
67MHz Channel Clock
152MHz subsys Clock
ARM
RAM
ROM
SMIU
AHB/
VPB
Interface
PDSIC
SEG.
MAN
DMA
21 of 102
© Philips Electronics N.V. Year. All rights reserved.
VPB Slaves clock
VPB
RTC
GPIO
WDT
8.4672 MHz I2C Clock
I2S Bit Clock
Fig 7. Clocking Top Level Block Diagram
2x
UART
I2C
I2S
Handler
2x
Timers
Audio
DAC
cMusIC (SAA7838)
8.4672 MHz PDSIC Clock
One Chip CD Audio Device with Integrated MP3/WMA decoder
Rev. 1.1 — 15 April 2005
AHB
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
6.5 Channel Decoder
6.5.1
Features
The channel decoder in the SAA7838 is derived from the design used in the
SAA7817 DVD decoder IC. The design has been optimised for CD decode
functionality (i.e. EFMPlus demodulation has been removed) and has the following
features:
„ 1-channel interface to the on-chip 6-bit 67 MHz AD converter
„ signal conditioning logic with high-pass filter, DC offset cancellation (AOC) and
AGC logic
„ HF Defect detection circuitry with automatic hold of AGC, AOC, HPF, PLL and
slicer on defect detection
„ digital equaliser, noise filter, PLL and slicer
„ RL2PB mechanism
„ EFM demodulator with sync interpolation
„ CD-text and subcode Q-channel extraction blocks with software-interface via
registers
„ decoding, de-interleaving and Reed-Solomon error correction according to CD
CIRC standards
„ on chip de-interleaving SRAM memory
„ audio processing backend with interpolate/hold, mute, kill and silence detect logic;
and de-emphasis and 4X upsample filter.
„ 2 data-output interfaces: IIS and EBU
„ 1 serial subcode output interface (V4)
„ motor control for CLV(locked on EFM) or CAV(locked on tacho) or open loop or
software controlled regulation with 1 or 2 motor pins.
„ On Board tacho measurement with 1 or 3 Hall sensor inputs(T1-T3, which
provides frequency input for motor loop. The sensor inputs are shared with GPIO
pins.
„ 8 bits register map, with AHB slave interface
„ an interrupt output with associated interrupt, status and interrupt enable registers
for full interrupt-driven operation
„ Debug information available via meas1 and cflg pins and parallel debug-bus.
6.5.2
Block Diagram
The incoming diode signals are first added and processed in the analog frontend in
order to create a proper RF(HF) signal. This analog signal is converted to digital by
the ADC. This signal is then resampled from the ADC-clk to the systemclock domain
via the int/dump block. Offset and gain on the RF signal is regulated away via the
AGC/AOC loop (which go via the analog frontend). Remaining offset which is not
removed by the analog frontend can be removed via the digital HPFilter. The
RF-signal is then sliced by the bit detector, clock recovery is done by a full-digital
PLL with noisefilter, equaliser and sample rate convertor. A defect detector
makes it possible to hold AGC, AOC, HPF, slicer and PLL during black/white dots. At
this point in the datapath, RF-samples are converted into a bitstream.The RL2
pushback will avoid that RL3’s in the RF are accidently translated into RL1 or RL2 in
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22 of 102
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
the bitstream. The channel bit stream is demodulated to bytes by the EFM
demodulator. Q-channel subcode and CD-TEXT information is extracted via the
Q-subcode and CD-TEXT decoder, available for readout through the subcpu
interface. The main data stream is error-corrected by the ERCO, while the Memproc
takes care of the CIRC de-interleaving and buffering of data in a FIFO. At the
backend of the channel decoder, corrupted audio-samples can be interpolated and
held, while a burst of errors can trigger the mute block. Detection of digital silence
can be used to kill the internal/external audio DAC. Pre-emphasis on the audio-disc
can be removed via the de-emphasis filter, and the data can be 4x upsampled
before sending to the audio DAC. CD-data is outputted via the IIS and/or the EBU
outputs. Motor-control can be frequency regulated on incoming RF bitrate, with
additional phase regulation on FIFO filling, or can be fully controlled via software. CLV
support is guaranteed in this way, A tacho measurement block is available as well.
Motor can get regulated on the tacho-frequency, in this way CAV support is possible.
Debug information is available via registers, via the dedicated serial lines Meas1 and
Cflg.
On the block diagram, the Arm AHB address of the registers that control specific logic
has been added in RED next to each functional block.
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IC Datasheet
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Rev. 1.1 — 15 April 2005
23 of 102
12NC
IC Datasheet
Rev. 1.1 — 15 April 2005
EFM
Demod
0x3000 (0020, 0240,
0248, 024C)
subcpu
+
general
0x3000 0168
Ana
log
A
D
C
AGC
AOC
Peak
Detectors
Offset
Measure
ment
HPF
0x3000
00A40x3000
00BC
+
error correction info
ERCO
moto1
moto2
0x3000 0210 0x3000 022C
MOTOR-Control
(CIRC dec
+ FIFO)
Memproc
0x3000 0170,
0x3000 0178
-
0x3000 013C
0x3000
00F0-0x3000
0104
Defect
Detector
Peak
Detector
0x3000 0174,
0x3000 01800x3000 0184
hold
0x3000
00D4
- 0x3000
00D8
0x3000 0000 0x3000 000C
clockshop
0x3000 01A00x3000 01A8
Q-subcode
CD-TEXT
0x3000 01B00x3000 01BC
0x3000 0060 0x3000 00A0
0x3000
00A0
0x3000
0000
Int/Dump
0x3000 00D0
slice
level
determine
T1T2 T3
silence
detect
Error
detect
0x3000 01E8
Kill
generation
Upsample
Right KILL
Left KILL
0x3000 01EC
Deemph
0x3000 00400x3000 004C
interrupts
0x3000 01D0,
0x3000 01D4
IIS
EBU
Interface
0x3000 01E0
0x3000 01F0
Hard mute
CFLG
0x3000 0244
MEAS1
0x3000 (01400144)
0x3000 01F0
0x3000 01E0,
0x3000 01E4
0x3000 01E8
0x3000 0260 0x300 026C
Tacho
Soft mute
Slice level
PLL frequency
Jitter value
Multiplex
RMS
jitter
measurement
0x3000 01E0
to
demodulator
0x3000 (0120-0128), 0x3000
(0134-0138),0x3000 0148
zero
trans
detect
RL2
pushback
0x3000 01E0
Digital
PLL
clocked on PLL clock
0x3000
0130
Digital
equaliser
0x3000 01DC
0x3000 01F0
hold
Noise
Filter
0x3000
012C
Interpolate/
hold
SRC
0x3000
0160
IIS
IC Datasheet
from
RL2 PB
diode
signals
Philips Semiconductors
SAA7838
One Chip CD Audio Device with Integrated MP3/WMA decoder
Fig 8. Channel Decoder Top Level Block Diagram
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6.5.3
Clock Control
cl1clock
CL1_DIV
(50%)
int & dump
CL1
/1, /2, /3, /4
hf_clk (66M)
sysclock
xclk (66M)
sysclk
33M
(50%)
/2
CLOCKSYS_DIV
(pulse blanking)
/1 (33M), /2 (16M),
/4 (8M), /8 (4M),
/16 (2M)
sys_always_on
phi1
phi2
phi3
fastclk
ebuclock
CLOCKEBU_DIV
(50%)
ebuclki
/2, /3, /4, /6, /8, /12,
/16, /24, /32, /48
ebuclk
cl16clock
CL16_DIV
(50%)
CL16
/3, /4, /6, /8
bitclock
CLOCKBIT_DIV
(50%)
bclki
/2, /3, /4, /6, /8, /12,
/16, /24, /32, /48
bclk
bclk_in
bdei
Fig 9. Clock Control Block Diagram
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One Chip CD Audio Device with Integrated MP3/WMA decoder
The clock control block defines the clock frequencies for four clock domains.
„ xclk
(Almost) all internal clocks are derived from xclk. This clock is the output of the
clock multiplier in the analog part and has a fixed frequency of 67.7376Mhz =
8.4672 (crystal oscillator) x 8. If a 16 MHz crystal is used, the crystal clock is
divided by 2 inside the analog block.
Crystal selection is done via
AnalPLLControl(Sel16).
„ Sysclk domain
The main part of the internal channel decoder blocks run on the sysclk or
derivatives. Sysclk is derived from xclk divided by 2 (50% dutycycle) and can be
further divided down via register SysclockConfig(SysDiv). This register also
provides the possibility to power down the majority of the clocks (for sleep
mode).The choice of the sysclk frequency in an application is determined by the
expected input bitrate on the RF stream. The relation between this incoming
bitstream frequency and the system clock is expressed in a "fbit/fsysclk" ratio. There
are 2 limiting factors :
- The HF-PLL operation range is between 0.25 and 2 fbit/fsysclk.
- The decoder and error corrector throughput rate is limited to 1.7 fbit/fsysclk.
This brings the constraint to 0.25 < fbit/fsysclk < 1.7
„ Bitclk domain
The IIS backend logic runs on this clk. Bitclk is also output as part of the IIS
interface. In audio slave mode this clocks needs to be programmed exactly at
44100 Hz x 2 x 16/24/32 (depending on IIS-mode), to get a 1X data rate to the
audio DAC. In master mode with gated bitclk, bitclk must be programmed at a
higher rate then the required outgoing bitrate for that disc speed, to avoid FIFO
overflow in the decoder. (For instance @ N=1, the incoming RF-bitrate = 4.3218
Mhz, which corresponds with an output bitrate of 1.4112 Mhz. This means that
bitclk > 1.4112 Mhz is high enough when IIS-16 is chosen, while IIS-32 requires at
least 2.8224 Mhz bitclk.
The bitclk division is selected via register BitClockConfig. Also bitclk-gating can
be enabled via the same register.
„ EBUclk domain
The EBU backend runs on this clk. The EBU (or SPDIF) interface is only enabled
during audio slave mode. The ebuclk needs to be exactly 44100 x 64 = 2.8224
Mhz for 1X operation.
EBU clk division is selected via register EBUClockConfig.
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-There are a few other clocks controlled by the clock control block:
- The hf-clk is fixed at 67.7376Mhz, and is used to clock in the samples from the
ADC, which is clocked by the xclk with the same clock frequency.
- The bclk_in is the incoming IIS-bitclk, which is used when IIS is programmed to
receive bclk rather then transmitting it (programmed via register IISConfig).
- The CL1 clock can be used to monitor the Cflg and Meas1 debug lines. The
frequency can be programmed via register CLClockConfig.
- The CL16 clock can be used to clock an external audio DAC or audio filter IC. The
frequency can be programmed via register CLClockConfig.
6.5.4
Decoder-ARM Microprocessor Interface
The decoder core is internally connected to the ARM core via the AHB interface for
register access to the decoder internal configuration registers.
6.5.4.1
Programming interface
Decoder registers are programmed through the AHB interface. (A full description of
the interface itself will not be described in this document.)
For the application, it should be noted that the interface supports 32 bit registers,
while the decoder only contains 8 bit registers. As a result, the decoder registers will
be treated as 32 bit registers of which the 24 MSB’s are never used.
The register address-map occupied by the decoder goes from relative address
0x3000 0000 to address 0x3000 0374, and can be split up in 2 parts :
0x3000 0000 - 0x3000 024C : the decoder’s own registers : these registers are used
to configure the channel decoder, and the functionality they control is described in
detail in this section.
0x3000 02A0 - 0x3000 0374 : the decoder immigrant registers : these registers are
not used to control the decoder channel decoder, but other parts of the SAA7838 chip
which don’t have their own AHB interface.
6.5.4.2
Interrupt Strategy
The channel decoder contains 2 interrupt registers. InterruptStatus1 contains all
interrupts that operate as set/reset latches (set by hardware, reset by reading from
the register). InterruptStatus2 contains all interrupts that operate as feed throughs
(set by hardware, reset by hardware or by accessing other registers).
Every interrupt-bit can be enabled/disabled separately by writing to the corresponding
enable bit in the InterruptEnable1 and InterruptEnable2 registers. If one or more
interrupt bits in the status registers are set, and at least one of them has its
corresponding enable turned on, the interrupt line of the decoder towards the
microcontroller will go active (low). When an interrupt bit’s corresponding enable is
turned off, the interrupt status bit will still behave exactly the same as described
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One Chip CD Audio Device with Integrated MP3/WMA decoder
above, with as only difference that it will not trigger the interrupt line anymore. In this
mode the interrupt could still be processed if polling on the status register is used
rather then real interrupt handling in the microcontroller.
6.5.5
D1
D2
D3
D4
analog
block
EFM bit detection and demodulation
Signal
conditioning
block
6 bit
ADC
PLL &
bit slicer
To
demod
AGC
AOC
Fig 10. Bit Recovery Block Diagram
A block diagram of the bit recovery is shown in Fig 10.
The HF signal is combined from the 4 diode inputs inside the analog block. It is
preprocessed (LPF, HPF, offset removal and gain adjustment) and then sampled by a
6-bit ADC.
On the sampled HF, bit recovery is done by means of a full digital PLL and slicer.
Before the sampled signal is going into the PLL section, it is preprocessed by a signal
conditioning block. This consists of an integrate-and-dump block, a high-pass filter
and logic available to do gain control and offset control on the RF-signal in the analog
section.
For good playability on defects, a defect detector is present, which can put the PLL,
the slicer, the AGC, the offset cancellation and the high pass filter into hold during
defects.
The detected bits are then sent to the demodulator for sync extraction and EFM
demodulation. For playing on damaged or out-of-spec disks, flywheels are in place to
make the sync extraction more robust.
6.5.5.1
Signal Conditioning
This device has a number of blocks which process the incoming 6-bit HF-signal
„ Integrate and dump block to adapt the frequency of the AD converter to the
system clock
„ Peak detection logic for amplitude measurement
„ Peak detection logic for DC offset measurement
„ Digital high pass filter with configurable cut off frequency
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One Chip CD Audio Device with Integrated MP3/WMA decoder
„ DC - and Gain control logic for onboard variable gain and offset control (in the
analog section)
„ A defect detector
All blocks can be configured under uP control.
Analog
ADC
Int/Dump
HF-data
to bit detection
HPF
Offset
Measurement
Peak
Detectors
AGC
AOC
hold
Peak
Detector
Defect
Detector
hold signals
to bit detection
Fig 11. Signal Conditioning Block Diagram
„ Integrate and dump block
The ADC delivers 1 sample every xclk period (= 1 sample every hfclk period). The
sample rate needs to be adapted from this xclk rate to the lower sysclk rate. For more
info on sysclk speed, see section “Clock Control” on page 25.
The integrate and dump block converts the incoming samples at the hfclk frequency
into a stream of 1 sample per sysclk period. It does an average over a number of
samples to achieve this. If the division factor for the system clock is /2, /4, /8, /16, /32,
an average of 2, 4, 8, 16 or 32 incoming samples is taken and passed further. The
results is a gain in the number of effective bits of the analog-to-digital conversion.
„ High pass filter
A first order IIR high pass filter with a variable 3dB point is implemented. This can be
used to filter out the remaining DC jump on defects (analog HPF will have filtered off
the most). The cut off frequency of the digital high pass filter can be changed on the
fly, by writing to HighPassFiltCont.
It is possible to reset the state of the high pass filter, via bit 6 of register
HighPassFiltCont. The input and the output of the high pass filter are 8 bits wide.
The high-pass filter is implemented in a ’1 minus lowpass’ structure. It is possible to
hold the low-pass filter on defects. For more info, see “Defect Detector” on page 34.
The high pass filter works on the system clock. It’s bandwidth is also proportional to
that sysclk.
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One Chip CD Audio Device with Integrated MP3/WMA decoder
An approximate formula for the cut off frequency, fc, of the high pass filter is
HPSet(5:0)
- ⋅ f sysclk
f c, HPF = ---------------------------11
2π ⋅ 2
„ Peak Detectors
There are 2 kind of peak detectors present in the signal conditioning block.
The first kind works on a immediate attack / slow decay basis, and is used for
measuring peaks, amplitude and offset for readback in software
sending peak information to the defect detector
The second kind works on the principle of detecting max and min peaks within a
window, and is used for the AGC and AOC control logic.
Both sets of peak detectors will look at the RF after it has passed an optional
noisefilter. This noisefilter is a LPF with a programmable high cut off frequency. This
BW is programmed via register PDBandwidth(NoiseFilterBW) for the noisefilter
before the peak detectors of AGC/AOC and measurement read back. The defect
detector peak detector has it’s own noisefilter which is programmed via register
DefectDetPeakBW(NoiseFiltBW).
„ Peak detector with decay filter
The functional schematic of this peak detection is shown in Fig 12.
S1
maxpeak
HF_in
noisefilter
C
S2
minpeak
C
Fig 12. Peak Detection Block with Decay Filter
The minimum and maximum peaks of the incoming signal are measured. Switch S1
takes the largest value at its inputs. Switch S2 takes the minimum value at its inputs.
The time constant of the decay filters has to be long. The same bandwidth is used for
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One Chip CD Audio Device with Integrated MP3/WMA decoder
the decay filter of the minimum and of the maximum peak. The decay filter for the
maximum peak tends to the smallest value possible. The decay filter for the minimum
peak tends to the largest value possible.
The decay BW of the measurement readback decay-filter is controlled via register
PDBandwidth(DecayBW), the one of the defect detector is controlled via register
DefectDetPeakBW(DecayBW).
The following settings of the decay filters are possible: C = 1-2-m, for m=6…21, where
m = DecayBW(3:0)+6.
The corresponding bandwidths of the decay filter are shown in Table 5, when the
frequency of system clock is 10MHz.
m
t
m
t
m
t
m
t
6
6.35 µs
10
102.4 µs
14
1.64 ms
18
26.21 ms
7
12.75 µs
11
204.7 µs
15
3.28 ms
19
52.43 ms
8
25.55 µs
12
409.6 µs
16
6.55 ms
20
104.8 ms
9
51.15 µs
21
209.7 ms
13
819.2 µs
17
13.11 ms
Table 5: Time constants of the decay filters, at fsys = 10 MHz
„ Peak detector based on window
The functional schematic of this peak detection is shown in Fig 13.
noisefilter
maxpeak
HF-in
minpeak
0
window width
Fig 13. Peak Detection Block with Window
The minimum and maximum peaks of the incoming signal are measured during a
programmable window period. The highest and lowest sample within this window are
taken to update maxpeak and minpeak.
The window width of the measurement is controlled via AGCAOCControl
(PDMeasWindow).
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„ AGC and AOC control block
The AGC control block controls the RF amplitude at the input of the ADC by
controlling the gain of an on-chip analog gain amplifier. The AOC control block
controls the RF offset at the input of the ADC by adding/subtracting offset just before
the ADC. Both AGC and AOC loops are built up in the same manner and are pictured
in Fig 14. with their relative position within the signal conditioning block.
G1
HPF (ana)
+
G2
G3
A
D
C
I
N
T
E
G
+1
Koffset
-1
I
N
T
E
G
-1
Kgain
+1
NF
(LPF)
Hi
window
PEAK
DET
Lo
decay
PEAK
DET
decay
PEAK
DET
REGS
DEFECT
DETECT
CLIPPING
DETECT
software
/ defect
4 MSB's
HPF (dig)
NF
(LPF)
software
/ defect
6 MSB's
to bitdetection
I/D
Hi
Lo
Fig 14. AGC and AOC loops
First of all the max and min peaks on the envelope of the RF signal after the ADC are
measured via a noise-filter and the window peak detector (see “Peak Detectors” on
page 30). After that, the amplitude is calculated as maxpeak - minpeak, and the offset
as (maxpeak+minpeak) / 2.
For tuning the loops, it is possible to read back the HFMaxPeak, HFMinPeak,
HFAmplitude and HFOffset, as measured by the decay peak detector, from
registers.
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„ AGC control
The RF-amplitude at the ADC input can be changed with 2 gain amplifiers in the
analog part : G1(fixed) and G2(dynamic). G1 has an gain-range from 0 till 24 dB in 16
steps of 1.6 dB, while G2 has a range from 0 till 12 dB in 16 steps of 0.8 dB. Both
gains can be programmed via register AGCGain. G1 will stay fixed, while G2 can be
regulated in hardware as soon as the AGC is turned on.
The AGC will regulate the gain such that the measured amplitude stays between a
programmed upper threshold(AGCThrHi) and lower threshold(AGCThrLo). If
amplitude is smaller, gain will increase; if amplitude is too large, gain will decrease.
Whenever clipping is detected on 1 or 2 sides, gain will decrease as well. This
gain-changes are not sent to the analog gain-amplifier directly, but are integrated
over time. Only if on average a gain-increase/decrease is requested, this will result in
a real gain-increase/decrease on the amplifier (can also be read back via register
AGCGain). This avoids (together with the noise-filter on the peak detector) that noise
on the RF would result in a nervous gain regulation. To decrease nervous behavior
even further a hysteresis window with a width of 1 gainstep has been added between
the integrator an the actual G2. The bandwidth of the gainloop will determine how fast
it reacts on fingerprints and scratches, and can be programmed via register
AGCIntegBW. It’s also possible to limit the range of G2 by programming a maximum
and minimum boundary (in register AGCGainBound).
„ AOC control
The RF-offset at the ADC input will be removed for the greatest part by the analog
HPF (1st order HPF with 3dB point around 3.6 kHz). The remaining offset (mainly
introduced by the analog frontend itself), can be removed by adding/subtracting a
fixed offset in the analog. This offset subtraction/addition has a range of 32 steps in
each direction, with approximately 1.4 LSBs per step (referenced to the RF-ADC).
This leads to a full correction range of +/- 42 LSB steps (more then the whole ADC
range). This Offset comp value can be programmed via register OffsetComp, and
will be regulated in hardware as soon as the AOC is turned on.
The AOC will regulate the offset compensation value such that the measured offset
stays within a programmed window(OffsetBound). If offset is above this window,
Offset comp value will decrease; if it is below, it will increase. (If there would be an
inversion on the RF signal between analog and digital, this reaction of this loop can
be inverted by programming OffsetBound(OffsetInv)).
This offset-changes are not sent to the analog offset-subtraction directly, but are
integrated over time. Only if on average a offset-increase/decrease is requested, this
will result in a real offset-increase/decrease on the analog addition (can also be read
back via register OffsetComp). This avoids (together with the noise-filter on the peak
detector) that noise on the RF would result in a nervous offset regulation. To
decrease nervous behavior even further a hysteresis window with a width of 1
offset-step has been added between the integrator an the actual OffsetCompValue.
The bandwidth of the offset loop will determine how fast it reacts on fingerprints and
other defects, and can be programmed via register OffsetIntegBW. It’s also possible
to limit the range of the OffsetCompValue by programming a maximum and minimum
boundary (in register OffsetCompBoundHi and OffsetCompBoundLo).
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„ AGC/AOC general + rules of thumb
The AGC and AOC hardware regulation loops can be enabled/disabled separately in
register AGCAOCControl. This register also allows the use of a ’slow’ AGC and/or
AOC loop. In that case the programmed loop-BW is decreased with an extra factor of
128. In this mode the loops will be too slow to react on defects, but can be used for a
slow software-like gain and/or offset regulation to regulate the average gain and
offset over the disc nicely within a specified range.
An important feature is the AGCAOCControl(DisHoldNoLock) bit, which disables
holding of the AGC and AOC loops during defects (triggered by the defect detector,
see ‘Defect detector” on page 22) while the HF-PLL is not in lock. This feature avoids
permanent lockups of the loops caused by a small amplitude triggering the defect
detector, which in return would hold the AGC loop.
As rule of thumbs, following things should be taken into account :
The amplitude thresholds should be programmed not too close to each other, to allow
at least 2 gainsteps (1.6 dB) to go from lower to higher boundary and vice versa. This
to avoid a nervous AGC.
The offset boundary should be programmed not too tight, +/- 8 is a good value. This
to avoid a nervous AOC.
The BW of the loops should never be programmed too high (’fast’) with respect to the
peak detector measurement window, to avoid an unstable loop. If the PDwindow = 2n
sysclk’s wide, the BW of the loops should never be higher then 2 -(n+1).
„ Defect Detector
The purpose of the defect detector is to detect the presence of black or white dots in
the RF-stream, and to freeze some signal conditioning and bit recovery logic during
these defects. This will avoid that the control loops inside this logic would drift away
from their optimal point of operation whilst there is no RF present, such that they can
recover very fast as soon as good RF is present again.
The detection of a defect is based on amplitude. The amplitude is measured via a set
of peak detectors with decay, as described in section “Peak Detectors” on page 30.
The programming of the decay BW and noisefilter BW is done in register
DefectDetPeakBW.
One can program 2 thresholds. A low threshold will trigger a ’defect-detected’ signal
as soon as amplitude goes below this threshold. A high threshold will clear this
’defect-detected’ signal again as soon as amplitude goes above this threshold.
Together these thresholds create an hysteresis on the defect detection, to avoid a
jittery ’defect-detected’ signal (lot’s of ON/OFF’s) when amplitude is on the edge.
Thresholds are programmed in register DefectDetThres.
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The ’defect-detected’ signal can be used to hold the PLL, slicer, AGC, AOC and HPF
during a defect. Which feature(s) will be held can be programmed in register
DefectDetEnables. The same register can be used to force the PLL, slicer and HPF
into hold via software. The AGC and AOC can be held in software by just disabling
the loops in register AGCAOCControl.
Two special features exist on the defect detector :
It’s possible to delay the enabling and disabling of hold features at the beginning and
end of a defect. This can be done by programming a start- and/or stop delay (in
number of sysclk’s) via register DefectDetStartStopDelay. Whenever the defect
detector detects the start of a defect, he will wait for the start delay before triggering a
’defect-detected-processed’ signal. When the defect detector detects the end of a
defect, he will wait for the programmed stop delay before clearing the
defect-detected-processed’ signal again. This also means that defects which are
smaller then the start delay are ignored, and that if the defect contains zones with
good RF amplitude but smaller then the stop delay, they are ignored as well. In reality
all hold features are triggered by the defect-detected-processed’ signal, rather then
the ‘defect-detected’ signal; but after rest of the decoder, both delays are 0, so both
signals are equal.
It’s possible to program a time-window after the end of a defect, during which higher
PLL and/or slicer BW’s can be used (to speed-up the recovery of this loops after the
defect). This window can be programmed via register DefectDetHighBWDelay, the
programming of the BW’s is explained in section “Bit Detector” on page 36.
The detection of the beginning or ending of a defect, with and without start- and stop
delays, can be used to generate an interrupt. See register InterruptEnable1.
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6.5.5.2
from
signal
conditioning
-
+
Bit Detector
SRC
Noise
Filter
slice
level
determine
Digital
equaliser
to
demodulator
RL2
pushback
zero
trans
detect
clocked on PLL clock
Digital
PLL
RMS
jitter
measurement
Multiplex
Jitter value
PLL frequency
Slice level
MEAS1
pad
Fig 15. Block Diagram of the Bit Recovery Block
The bit detector block contains the slice level circuitry, a noise filter to limit HF-EFM
signal noise contribution, an equaliser, a zero-transition detector, a run-length
push-back circuit, a digital PLL and jitter measurement logic.
All processing is done on the bit clock, and bandwidths are proportional to the
channel bit rate.To achieve this, RF data is resampled from the system clock domain
to the bitclk domain by making use of a sample-rate convertor. Blocks can be
configured under microcontroller control and are described in detail in the next
paragraphs.
„ Noise filter
The digital noise filter runs on the channel bitclock frequency fb. It will limit the
bandwidth of the incoming signal to 1/4 of the channel bit clock frequency.
Passband: 0 to 0.22 fb
Stopband: (0.28 fb) to (fb - 0.28 fb)
Rejection: -28 dB
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„ Slice level determination
The slice level determination circuit compensates the incoming signal asymmetry
component. Bandwidth of the slice level determination circuit is programmable via
register SlicerBandwidth. Also the higher BW’s for use after a defect (see ‘Defect
detector”) are programmed in this reg. The bandwidth is proportional to the channel
bit clock frequency. The slice level, or asymmetry, can be read back via register
SlicerAssym.
„ Equaliser
In the bit detection circuit, a programmable equaliser is used: it boosts the high
frequency content of the incoming signal.
A five-tap presentable, asymmetrical equaliser is built in. The equaliser block diagram
is given in Fig 16.
in
D
D
D
D
α.1
D
α.1
+
-
-
+
out
Fig 16. Equaliser Block Diagram
The first and last tap can be programmed via register PLLEqualiser.
„ Usable EFM bit clock range
The channel bit clock frequency should always obey the following constraints:
It should be smaller than two times the system clock frequency fsys
It should be larger than 0.25 × fsys
So:
0.25 < fbit / fsys < 2
Only in this range a reliable bit detection is possible. If input channel bit rate is above
2 × fsys then the PLL will saturate to 2 times the system clock frequency.
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Note that while these are theoretical limits, a real-life application should keep a safety
margin. When the bit clock is relatively low, the internal filter will filter off more noise,
yielding a better performance. If the theoretical upper-limit is approached, playability
(e.g. black dot performance) will drop significantly. The decoder will only be able to
correct the biggest correctable burst error of 16 frames if fbit / fsys < 1.7.
Taken this restriction on the decoder into account, the new range becomes:
0.25 < fbit / fsys < 1.7
„ Digital HF PLL
The digital PLL will recover the channel bit clock. The capture range of the PLL itself
is very limited. To overcome this difficulty, 2 capture aids are present. When using
automatic locking, the PLL will switch states based on the difference between
expected distance and actual distance between syncs.
In total, 3 different PLL operation modes exist:
In-lock (normal operation) : the pll frequency matches the frequency of the channel
bits with an accuracy-error less than 1 %
Inner lock aid (capture aid 1) : the pll frequency matches the frequency of the
channel bits with an accuracy-error between 1 and 10 %
Outer lock aid (capture aid 2) : the pll frequency is more then 10 % far from the
channel bit frequency
First, PLL operation during in-lock is explained. This is the normal on-track situation.
After this, the lock-detection and the 2 capture aids are explained.
„ PLL in-lock characteristics
The PLL behavior during in-lock can best be explained in the frequency domain. PLL
operation is completely linear during in-lock situations. The open-loop response of
the PLL (bode diagram) is given in Fig 17.
loop gain
f0
f1
frequency
fLPF
Fig 17. PLL Bode Diagram
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f1: IntegratorXover-> controlled via Ki
f0: PLLBandwidth -> controlled via Kp
f2: LPBandwidth
-> controlled via Kf
The 3 frequencies are programmable using register PLLBandWidth. The higher
BW’s for use after a defect (see “Defect Detector” on page 34) are programmed in
reg PLLBandWidthHigh.
When the PLL is in lock the recovered PLL clock equals the channel bit clock.
„ Detection of PLL lock
The PLL locking state is determined by the distance between detected syncs. This
means that the sync detection is actually doing the control of the automatic PLL
locking.
The PLL switches from outer lock to inner lock when successive syncs are detected
to be 588 +/- 25 channel bits apart. Internally this is also called a ’winsync (sync falls
in a wider window)’. The number of missed winsyncs is kept in a 3 bit confidence
counter, and the PLL will go out of outer lock when 7 consecutive out-of-window
syncs are found.
The PLL switches from inner lock to in-lock when successive syncs are detected 588
+/- 1 channel bits apart. The number of consecutive missed syncs is kept in a bit
counter, and saturates on either 16 or 61, depending on the value of bit Lock16or61
in register DemodControl. When the saturation level is reached, the PLL is set out of
lock.
The PLL frequency (inner) and phase (in) lock status can be read out in register
PLLLockStatus.
„ PLL outer-lock aid
The outer lock aid has no limitation on capture range, and will bring the PLL within the
range of the inner lock aid. The PLL will first regulate it’s frequency based on
detecting RL3’s as the smallest possible RL’s (fast but rough regulation), and next on
detecting RL11’s as the largest possible RL’s (slow but more accurate).
„ PLL inner-lock aid
The inner lock aid has a capture range of +/- 4 %, and will bring the PLL frequency to
the phase-lock point. It will regulate the PLL frequency such that 588 bits are
detected between 2 EFM-syncs.
„ Influencing PLL behavior
Programmability and observerability is built into the PLL mainly for debugging
purposes, and also to make difficult applications possible. The PLL operation can be
influenced in two ways. First, it is possible to hand-select the state the PLL is in
(in-lock, inner-lock, outer-lock, outer-lock with only RL3 regulation). Second, it is
possible to pre-set the PLL frequency to a certain value.
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„ Over-ruling the PLL’s state
PLL state can be
- In-lock
- Inner lock
- Outer lock
- Outer lock with RL3 regulation only
- Hold
Normally, selection is done automatically using the lock detectors. Selection can be
overruled via register PLLLockAidControl. When LockMode is left to ’0’, user can
still select lockstate, but hardware will overwrite this if hardware selected lockstate
means closer to lock.
LockMode
PLLLockControl
0
00000
Automatic lock behavior
MEANING
1
00001
Force HF PLL into in-lock
1
00110
Force HF PLL into inner lock-aid
1
00100
Force HF PLL into outer lock-aid
1
01000
Force HF PLL into hold mode
1
10100
Force HF PLL into outer lock-aid with RL3 regulation only
x
Others
reserved
Notes: During PLL hold, frequency will not change and the frequency pre-set may be
used.
„ Writing PLL frequency is possible to preset the PLL frequency to a certain value.
This is done by writing the integrator value of the PLL in register PLLIntegrator.
The relationship between the bit frequency, the integrator value, and the sysclk
frequency is given by:
PLLFreq(7:0) + 4
f channelbit = --------------------------------------------- ⋅ f sysclk
128
(EQ 1)
The real-time value of the PLL frequency can be read on the same address.
6.5.5.3
Limiting the PLL frequency range
The range over which the PLL can capture the input frequency can be limited. The
minimum and maximum PLL frequency be set in bits MinIntFreq resp. MaxIntFreq of
register PLLMinMaxBounds.
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6.5.5.4
Run length 2 push-back detector
If this circuit is switched on, all run length 1 and 2 symbols (invalid runlengths) are
pushed back to runlength 3. For RL2’s, the circuit will determine the transition that
was most likely to be in error, and shift transition on that edge. This feature should
always be turned on, but can be deselected via register RL2PushBack.
6.5.5.5
Available signals for monitoring
The operation of the bit detector can be monitored by the microcontroller and using
an external pin. Five signals are made available for measurement.
„ PLL frequency signal
The first signal that can be monitored is the PLL frequency signal. Monitoring via the
microcontroller is done by reading the register PLLIntegrator.
„ Asymmetry signal
The second signal that can be monitored is the 8-bit asymmetry signal. The signal is
in 2-complement form and can be read from register SlicerAssym.
„ Jitter signal
A jitter measurement is done internally. The zero-crossing jitter is available in register
PLLJitter.
The jitter measurement is done in two steps:
First, the distance between the EFM zero transition and the bit clock zero transition is
measured.
Distance (x fbit)
Average distance (bit clocks)
jitter filter input (5 bit decimal integer)
< 2/16
1/16
1
2/16 ... 4/16
3/16
9
4/16 ... 6/16
5/16
25
>6/16
7/16
49
Table 21: Jitter input calculation
Second, the calculated jitter for the zero transition is averaged using a 10-bit
low-pass filter. The top 8 bits of the filter output can be read back from register
PLLJitter. To obtain the jitter in % of the channel bit clock, following formula applies:
jitter (in %) =
jitter(7:0) - 2.83
------------------------------------------ ⋅ 100
1024
This jitter measurement is also available via the Meas1 telemetry signal. On this
signal, the full 10 bit output of the filter is available - see 6.5.5.8‘Format of the
measurements signal on MEAS1 pin”.
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It’s also possible to read out an average jitter value via register PLLAverageJitter.
This value is an average over a period of 8000 bitclks on the normal jitter value. The
formula to transform this into % stays the same :
average jitter (in %) =
6.5.5.6
averagejitter(7:0) - 2.83
---------------------------------------------------------------- ⋅ 100
1024
Use of jitter measurement
The jitter measurement is an absolute-reference jitter measurement. It gives the
average square value of the bit detection jitter. The jitter is measured directly before
the bit detection in this device, and contains contributions due to various
imperfections of the complete signal path: (Note that bit-to-clock jitter is measured.)
„
disc
„
analog preamplifier
„
A/D converter
„
Limited bandwidths in this device
„
Limited PLL performance
„
Influenced by internal noise filter, asymmetry compensation,
equaliser
The jitter measurement is absolute-reference, because it relates directly to the EFM
bit error rate if the disc noise is gaussian.
6.5.5.7
Internal lock flags
The fourth signal that can be monitored are three flags in the PLLLockStatus
register: the internally generated inner lock signal FLock, the internally generated
lock signal InLock and a LongSym(bol) flag when runlength 14 is detected. (Too high
runlength).
In automatic mode, the FLock and InLock flags determine what type of PLL capture
aid is used.
FlockFLag
InLockFlag
Capture mode
0
0
outer lock aid
1
0
inner lock aid
x
1
in-lock
Determining the current PLL capture mode
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6.5.5.8
Format of the measurements signal on MEAS1 pin
On this serial bus, which is output via a pin and should be monitored using CL1
(available via another pin), three measurement signals are multiplexed together.
Figure 18: gives details on the format.
Pause
Start bit
Data bits
Figure 18: Format on measurement pin MEAS1
The data is sent in a serial format. It consists of a pause, followed by a start bit. The
start bit is followed by data bits.
Bit length:4 system clock periods Frame length:64 bits
Data format:
Bit no.
Value
Comment
Note
0
'1'
Start bit
1
1 … 10
jitter(9) ... jitter(0)
First sample of jitter word
2
11
'0'
12
'1'
Intermediate start bit
13 … 22
pllfreq(9) ... pllfreq(0)
PLL frequency word
23
'0'
24
'1'
Intermediate start bit
25 … 32
asym(7) ... asym(0)
slicer level
33, 34, 35
'0'
"000"
36
'1'
Intermediate start bit
37 … 46
jitter(9) ... jitter(0)
Second sample of jitter word
47 … 63
'0'
Pause
2
Data format on measurement pin MEAS1
Notes:
The start bit is always preceded by 17 pause bits. The intermediate start bits at bit
locations 12, 24 and 36 guarantee that no other '1'-value is preceded by 17 '0'-bits.
This allows a simple start bit detection circuit.
The jitter word is sampled twice in every frame.
The jitter in % is calculated with following formula:
jitter (in %) =
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IC Datasheet
jitter(9:0) - 12.81
-------------------------------------------- ⋅ 100
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6.5.5.9
Demodulator
The demodulator block performs the following functions
„EFM demodulation using an logic array.
„sync detection & synchronisation
„sync protection.
6.5.5.10
EFM Demodulation
Each EFM word of 14 channel bits (which are separated from each other by 3
merging bits) is demodulated into one data byte making using of the standard logic
array demodulation as described in the CD red book.
6.5.5.11
Sync detection & synchronisation
The EFM sync pattern is a unique pattern which is not used anywhere else in the
EFM datastream. It consists of 24 bits : RL11 - RL11- RL 2 . An internal sync pulse is
generated when two successive RL11’s are detected. A subsync pulse is given when
the beginning of a new subcode frame is seen. This is done by analyzing the subcode
information : when 2 successive subcodes are subcode-sync-code S0 and S1,
subsync will be activated.
6.5.5.12
Sync protection
The subsync pulse is protected by an interpolation counter, this counter uses the fact
that a subcode frame is always 98 subcode symbols long.
The sync signal itself is also interpolated. If after 33 databytes (= 1 efm-frame), no
new sync is detected, it is assumed that the bit detector has failed to correctly
produce it, and the sync signal is given anyway, this is generally called an
"interpolated sync." If furthermore a new sync is detected in the data shortly after a
previous sync signal ( interpolated or real ) no new sync signal will be given, because
this means the frame has " slipped ". After enough data byte periods, the sync signals
are allowed to pass again.
Although the chance is little, it’s always possible to detect ’false’ syncs, so corrupted
efmbits that form by accident the combination RL11-RL11. If 2 (or 3) of such false
syncs would be detected at the correct distance from each other, this would cause a
false resync of the demodulator. Such resync could lead to a large number of
samples being corrupted at the output of the CIRC decoder. Chance on false sync
detection is the highest during defects (black and white dots).
To prevent such false demodulator resyncs, 2 features have been build in, which are
both programmable via register DemodControl :
„RobustCntResync : This feature should always be turned on : when
it’s on, the demodulator will look for 3 consecutive syncs with correct
in-between distance before resyncing; in stead of 2. This will
improve the robustness against false syncs already a lot.
„SyncGating : when ’1’, the sync-detection is turned OFF during a
defect, to avoid the detection of false syncs; when ’0’, sync detec-
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tion is left ON all the time; Note that the defect detector needs to be
setup properly before this feature can be used. That’s why this feature is turned off by default after reset.
6.5.6
6.5.6.1
CD decoding
General Description of CD-Decoding
The decoder block performs all processing related to error correction and CIRC
de-interleaving and makes use of an internal SRAM FIFO which provides the
necessary data-capacity for doing this. It also extracts the Q-channel subcode and
the CD-TEXT information from the data stream and delivers it to the application via a
register interface.
6.5.6.2
Q-channel subcode interface
The channel decoder contains an internal buffer which stores the Q-channel bytes of
a CD-subcode-frame. This subcode can be retrieved by the microcontroller, by
accessing
the
registers
SubcodeQStatus,
SubcodeQData
and
SubcodeQReadend.
To start retrieving the subcode, the microcontroller must read the register
SubcodeQStatus first. This register contains various status bits that indicate the
status of the Q-subcode that may be read. When, after reading the register
SubcodeQStatus, the QReady bit is found high, the Q-subcode interface will be
blocked (indicated by Qbusy going high) so that no new subcode will overwrite the
current one. QCRCOK indicates if the current subcode frame was indicated ok or not
by a hardware CRC check.
After reading SubcodeQStatus with QReady = '1' , the microcontroller may retrieve
as many subcode bytes as required (max. 10) by issuing subsequent reads to
register SubcodeQData.
The content of the Q-channel subcode in the main data area is described in Table 6.
For description of the content during the lead-in area, see CD red book.
Address/Byte
1
Name
Comments
CONTROL/
MODE
2
TNO
3
POINT
4
REL MIN
Mod100
5
REL SEC
Mod 60
6
REL FRAME
Mod 75
7
ZERO
0 or incremented modulo 10
8
ABS MIN
Mod100
9
ABS SEC
Mod 60
10
ABS FRAME
Mod 75
Relative time
Absolute time
Table 6: subcode Q-channel frame content
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After finishing subcode read the microcontroller must release the interface to allow
the decoder to capture new subcode information. This is done by issuing a read to
register SubcodeQReadend.
The availability of a new subcode frame will also trigger an interrupt if bit
InterruptEnable2(SubcodeReadyEnable) is set.
6.5.6.3
CD-TEXT interface
The channel decoder contains an internal buffer which stores CD-TEXT information
(format 4, available in the lead-in area). The buffer can hold 1 CD-TEXT pack for
readback, while it receives at the same time the next pack.
The operation of the CD-TEXT readback interface is controlled via register
CDTEXTControl. Bit FreezeEn determines whether or not the internal buffer is
frozen during readback (such that the next pack can not overwrite the current one
before the micro has finished reading). Bit CRCFailEn determines whether or not
packs with a failing CRC check are made available for readback.
This subcode can be retrieved by the microcontroller, by accessing the registers
CDTEXTStatus, CDTEXTData and CDTEXTReadEnd.
To start retrieving the CD-TEXT pack, the microcontroller must read the register
CDTEXTStatus first. This register contains various status bits that indicate the status
of the CD-TEXT pack that may be read. When, after reading the register
CDTEXTStatus, the TextReady bit is found high, the CDTEXT interface will be
blocked (indicated by Textbusy going high) so that no new subcode will overwrite the
current one; at least if CDTEXTControl(FreezeEn) is turned on. TextCRCOK
indicates if the current CDText pack was indicated ok or not by a hardware CRC
check.
After reading CDTEXTStatus with TextReady = '1' , the microcontroller may retrieve
as many CDText bytes as required (max. 16) by issuing subsequent reads to register
CDTEXTData.
After finishing CD-TEXT read the microcontroller must release the interface to allow
the decoder to capture new CDTEXT information. This is done by issuing a read to
register CDTEXTReadEnd.
Remark : If CDTEXTControl(FreezeEn) is disabled, the interface is not held during
readback, which means it can happen that the current CD-TEXT pack is overwritten
by the next one before all bytes of the current pack are read out. Such an event will
be indicated by setting CDTEXTReadEnd(BufferOverflow) high, so that it can be
noticed by software at the end of the pack-read.
The availability of a new CDTEXT pack will also trigger an interrupt if bit
InterruptEnable1(CDTEXTReadyEnable) is set.
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6.5.7
6.5.7.1
Main Data Decoding
Data processing
The CD main data is deinterleaved and error-corrected according the CD red book
CIRC decoding standards and uses an internal SRAM as buffer and FIFO. The C1
correction will correct up to 2 errors / EFM-frame, and will flag all uncorrectable
frames as an erasure. The C2 error correction will correct up till 2 errors or 4
erasures, and will also flag all uncorrectable frames as an erasure.
The decoding operation is controlled by the DecoMode register. There are basically 2
decode operation modes.
In Flush mode, the de-interleaver tables are emptied, and all internal pointers are
reset. No data is written into the buffer, no corrections are done, and no data is
output.
In Play mode, de-interleaver tables are filled, C1 / C2 corrections are done, and data
is output (when available).
During FLUSH mode, no data is output from the device. During PLAY mode, data is
output via the IIS interface as soon as it is available in the internal FIFO.
Figure 19 shows the operation of the FIFO and corrections during CD playback.
FIFO filling
'd'
deinter
leave
C1
correct
FIFO
'D'
deinterleave
C2
correct
Delta
deinter
leave
To
IIS
backend
data
from
demod
Fig 19. Data Processing during CD mode
De-interleaving of the data is done as required by the Red Book specification.
De-interleaving is performed by the SRAM FIFO address calculation functions in the
memory processor. Two corrections are done - C1 followed by C2.
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6.5.7.2
Data Latency + FIFO operation
The system data latency is a function of the minimum amount of data required in the
FIFO to perform the de-interleaving operation. The latency is quoted in the number of
C1 frames (24 bytes of user data). The latency of the CIRC decoder is 118 frames.
The FIFOFilling is defined as this ’data latency’ + the number of extra frames stored
in the FIFO. The filling of the FIFO must be maintained within certain limits. 118
frames is the minimum as required for the deinterleaving, 128 is the physical
maximum limit, determined by the used SRAM size. This results in a usable FIFO
size of 11 frames. The FIFOfilling can be read back via register FIFOFill.
The Fifofilling must have a correct value. This can be achieved in 2 ways :
„ Master (Flow Control) mode : this mode is selected when using a gated bitclock
(bclk) at the IIS interface, see “IIS interface” on page 54 for more information. As
soon as a frame is available in the FIFO, it is output via the IIS interface. When
FIFO underflow is imminent, the decoder will gate of the output interface by
disabling bclk
„ Slave (audio) mode : In this case, the bclk is continuously clocking. The
application is responsible for matching the input rate (EFM bitrate coming from the
disc) to the selected output rate (IIS bclk speed), and keeping FIFOFilling
between 118 and 128. This is done by regulating the disc speed. See Motor
section for more details.
The FIFO is only storing data, not subcode. This means that the data will be delayed
as it comes from the demodulator, but the subcode is sent straight through over the
IIS interface. The difference in delay between subcode and data is always fixed. It is
absolutely fixed in Master mode, but can have small local variations during Slave
mode.
6.5.7.3
risky and safe correction modes
The CD CIRC decoding standard uses a Reed Solomon error correction scheme.
Reed Solomon error correction has always a very small chance on miscorrection,
which means that a corrupted codeword is modified into a valid but wrong codeword.
(Meaning : the codeword after correction is a valid existing RS codeword, but not the
word that used to be present at this location before corruption). The chance on such
miscorrections increases exponentially for every extra byte that needs to be
corrected in a codeword, and so is the highest when doing the maximum number of
corrections possible with a certain RS correction scheme.
Miscorrections should be avoided, since they will result in corrupted data being sent
to the backend, without their corresponding invalid flag being set. Certainly for
CD-Audio this is real problem, since not flagged wrong data will not get interpolated,
which can result in audible clicks.
Both C1 and C2 correction logic can be programmed to operate in a ’risky’ or ’safe’
mode via register ErcoControl. In risky mode, the maximum number of corrections
will always be done (if required). In safe mode, corrections will not be done when they
are considered too ’risky’, which means there is a realistic chance they could lead to
a miscorrection.
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For C1, risky mode will allow 2 bytes per codeword to be corrected, safe mode only 1.
For C2, both modes will allow up to 4 erasures per codeword to be corrected. When
there are more then 4 erasures and therefore erco switches back to error correction,
risky mode will allow 2 bytes to be corrected, safe mode only 1.
Remark : From experiments and theory it is advised to use C1risky - C2safe for
CD-audio as a good trade-off between safety and maximum error correction
capability. For CD-ROM one can use C1risky - C2risky, if there is at least a C3 error
correction and if the flyhweels in the CD-ROM block decoder are robust against
possible invalid but not flagged headers.
6.5.8
6.5.8.1
Error corrector statistics
CFLG
The error corrector outputs status information on the CFLG pin. The format of this
information is serial, similar to the one used on the MEAS1 pin.
The serial format consists of a pause bit followed by a start bit. This start bit is
followed by the data bits. The format of the data is explained in Table 7.
Bit length : 7 sysclk periods.
Frame length : 11 bits.
Bit no
Value
Meaning
Note
0
‘1’
Start bit
1
1:3
CorMode(2:0)
Type of correction
2
4
FlagFail
Failure flag set because correction too risky
3
5
CorFail
Failure flag set because correction impossible
3
9,6:8
ErrorCount(3:0)
Number of errors corrected
4
10
‘0’
Pause bit
1
Table 7: Format description on CFLG serial bus
Notes:
The repetition rate on the CFLG is not fixed. May be longer or shorter depending on
disc speed and output interface speed. There is always at least one pause bit.
Cormode definition:
“000" : C1 correction
"011" : C2 correction
"100" : Corrector not active
Others : not used
Corfail and FlagFail indicate failure status on previous codeword
ErrorCount indicates the number of errors found in the Chien search.
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6.5.8.2
BLER counters
There’s also a set of 2 BLER counters which count the number of frames (C1/C2)
with at least one error (for C2, erasures coming from C1 will also be counted). It
doesn’t matter whether the frame was correctable or not.
These registers are reset on read, and the user is responsible for reading them in
regular intervals. The BLER counters can be read on C1Bler and C2Bler.
6.5.9
Audio backend + data output interfaces
The channel decoder backend is shown on Fig 20.
Memproc
Interpolate/
hold
Soft mute
Deemph
Hard mute
EBU
Interface
Upsample
IIS
To I2S Handler
IIS
Error detect
Kill
generation
silence
detect
Left KILL
Right KILL
Fig 20. Back End Audio Functions
Decoded and error corrected CD-data streams into the backend from the memory
processor to the output-interfaces. In between some audio-filtering can be done (in
case of playing CD-DA).
6.5.9.1
Audio processing
Following audio features are present in the backend :
„ Interpolate / hold for IIS
„ Soft mute for IIS
„ Deemphasis filter for IIS
„ Upsample filter for IIS
„ error detection
„ silence detection
„ Kill generation
Some status-bits concerning this audio-features can be read back via register
MuteKillStatus.
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6.5.9.2
Interpolate and hold
On CD audio disks with a lot of (large) defects, where C1/C2 correction cannot
correct all the errors anymore, the audio data can be interpolated/held, to avoid
audible clicks/plops when playing back the disk. This feature is enabled by setting
FilterConfig(InterpolateEn).
The principle is depicted in figure 21
Hold
Interpolation
Interpolation
OK
Error
OK
Error
Error
Error
OK
OK
Fig 21. Error Concealment on CD Audio
Audio samples flagged as uncorrectable, neighbored by 2 good samples - or a held
and a good sample, will be interpolated. Audio samples flagged as uncorrectable,
which are not followed by a good sample, will hold the previous (correct or held)
sample value.
This feature is enabled/disabled for IIS and EBU together.
6.5.9.3
Soft mute and error detection
The audio data going to the IIS and/or EBU interface can be processed by a soft mute
block. This block can ramp the audio volume down from 0 dB till -90 dB, making use
of 64 stages of about -1.5 dB each. The current stage can be monitored and changed
in software by reading or writing register MuteVolume. This allows the
implementation of a software mute-scheme. If the hardware mute logic is triggered by
the error detection block (see below), it will ramp the volume down from maximum till
fully muted in 3/N ms, with N the X-rate of the disc. The mute-logic can be enabled
separately for the IIS and EBU outputs, by setting the corresponding bits in register
MuteConfig.
The backend also contains an error detection block, that scans the data for a
programmable number (via register MuteOnDefectDelay) of consecutive corrupted
stereo-samples. If such a pattern is found, and MuteConfig(MuteErrEn) is turned on,
the softmute will be triggered to start it’s volume ramp down. This detection will also
trigger a InterruptStatus1(AudioErrorDetected) interrupt.
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6.5.9.4
Hard mute on EBU
The EBU can be hard muted (EBU main data and flags set to 0, status and user
channel still valid) by setting EBUConfig(EBUHardMute).
6.5.9.5
Silence detection and kill generation
The silence detector looks for 250 ms of digital silence (2’s complement data = all ’1’s
or all ’0’s) on either one or both channels and can trigger the kill-logic when it is
found. Enabling of this feature is done via KillConfig(KillSilenceEn).
The kill-logic generates a left and a right KILL signal, which are brought out of the
channel decoder and can be used to gate of the left and the right channel of an audio
DAC. The kill signals can be triggered on both channels together by the detection of
stereo-silence, or on each channel separately by the detection of mono-silence.
Which operation is active is depending on the setup in register KillConfig. It’s also
possible to set the left and right kill signals in software by writing directly to the KillLeft
and KillRight bits in this register.
Another condition that will set both left and right kill signals is the soft mute block
reaching ’fully muted’ (volume-stage 0).
6.5.9.6
Deemphasis filter
This feature has only effect on the IIS, not the EBU output. The deemphasis filter can
be used to remove pre-emphasis from tracks which have been recorded making use
of the standard emphasis as described in the CD red book. The deemphasis filter has
the inverse response of the emphasis characteristics as described in the standard.
Gain
(dB)
0dB
-10 dB
τ = 50 µs
(3.18 kHz)
τ = 15 µs
Frequency
(10.6 kHz)
Fig 22. De-emphasis Characteristics
Control over the deemphasis filter is done via FilterConfig(DeemphControl). The
filter can be enabled/disabled under software control, or fully automatic in hardware.
In the latter case, the filter will be turned on when a ’pre-emphasis’ bit is detected in
the control byte of the Q-channel subcode, and turned off when this bit is missing.
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There are 2 detection modes possible :
„ according to red book : pre-emphasis bit is only checked (so allowed to change)
during the lead-in area, and during pauses between tracks
„ according to orange book : pre-emphasis in checked on every subcode frame
6.5.9.7
Upsample filter (4 times)
This feature has only effect on the IIS, not the EBU output. When it is enabled, the
audio data will be upsampled by a factor of 4. The upsampling provides the frequency
response described in Table 8.
.
Pass Band
Stop Band
Attenuation
0 - 9 kHz
-
=< 0.001 dB
9 - 20 kHz
-
=< 0.03 dB
-
24 kHz
=> 25 dB
-
24 - 27 kHz
=> 38 dB
-
27 - 35 kHz
=> 40 dB
-
35 - 64 kHz
=> 50 dB
-
64 - 68 kHz
=> 31 dB
-
68 kHz
=> 35 dB
-
69 - 88 kHz
=> 40 dB
Table 8: Upsample filter frequency response
When upsampling is enabled, the audio-data output rate on the IIS interface will be 4
times higher as without upsampling. Therefore also the IISWclk frequency has to be 4
times higher. This means the IISBclk speed needs to be programmed to a 4 times
higher speed then normally required for that X-rate when upsampling would be
disabled.
Another result of the upsampling is that every sample will have 18 bits precision iso
16 after the upsample filter. To make use of this extra bit-precision, the user should
select IIS-24 of -32 format. When using IIS-16 format, the 2 lowest bits will not be
output.
6.5.9.8
Data output interfaces
There are 3 interfaces via which data can be output from the channel decoder block.
„ Main data can be output via IIS
„ Subcode can be output via the subcode(V4) interface
„ Main data + subcode can be output via EBU/SPDIF
All interfaces can be used at the same time if needed, although there are a few
restrictions on the EBU, see “subcode(V4) interface” on page 55.
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6.5.9.9
IIS interface
The IIS is a 6 wire interface (4 main + 2 subcode). It supports 16, 24 and 32 bit IIS
and EIAJ(sony) modes. Timing is shown in and next (to be added). The required
format can be selected in register IISFormat.
BCLK
DATA
FLAG
D0
D15
D14
D13
Flag - MSB
WCLK
D12
D11
D10
D9
D8
D7
D6
(1 is unreliable)
Left
D5
D4
D3
Flag - LSB
D2
D1
D0
D15
D14
Flag-MSB
Right
SYNC
Fig 23. I2S format1 - 16 clocks per word, I2S format
Compliant with the IIS spec, IISWclk, IISData, IISFlag and IISSync are all clocked on
the falling edge of IISBclk.
„ IISBclk : all other IIS signals are clocked on IISBclk
„ IISWclk : indicates the start of a new 16/18-bit word on the dataline, + distincts
between left and right sample
„ IISData : 16/18-bit data words are outputted via this line, 1 bit / bclk-period
„ IISFlag : contains the byte reliability flag; bytes that are indicated as erasures
(possible errors) after C1 and C2 correction, are flagged.
„ IISSync : Indicates that the serial subcode line (V4) contains the MSBit of a
subcode word; it will be asserted every 6 Wclk-periods for half a Wclk-period. If a
subcode sync is transferred on the subcode line, this signal will be asserted for a
full Wclk period.
The IIS interface can either work in master or slave mode. In master mode, the
IISBclk can be gated off by the channel decoder. In slave mode, the IISBclk is
continuously running. To prevent the internal FIFO from overflow, the filling of the
buffer must be regulated (see “Data Latency + FIFO operation” on page 48).
IISBclk and IISWclk can either be input (generated outside the channel decoder) or
output (generated internally in the clockcontrol block). Selection can be done via
WclkSel and BclkSel in register IISConfig.
The IIS output rate is determined by the speed of the IISBclk clock, which is
configured via register BitClockConfig. One can configure the IIS interface to run at
1 or 2X CD.
In case of gated bitclock, when BitClockConfig(BclkGEn) is high, the speed must be
configured such that the maximum rate available on the bus is 20% higher then the
average data throughput rate. Or in other words : the bus should have at least 20%
idle time in between 2 bursts of data.
Default after reset, the IIS-pins on the IC will be put into tristate. They can be
activated via register IISConfig. This register also contains the possibility to ’kill’ the
IIS interface, such that all datalines output constant ’0’.
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6.5.9.10
subcode(V4) interface
Subcode data is output via the IISSubo (V4) port. This data can be sampled using the
IISSync signal (see “IIS interface” on page 54). The sync indicates that the serial
subcode line (V4) contains the MSBit of a subcode word; it will be asserted every 6
Wclk-periods for half a Wclk-period. If a subcode sync is transferred on the subcode
line, this signal will be asserted for a full Wclk period.
During normal operation (upsampling disabled), the subcode output via IISSubo will
have the format as shown on fig 24.
1 subcode byte every 24 IIS data bytes
wclk
b7 b6
(Start)
v4
b5
b3
b4
b2
b1
b0
b7 b6
(Start)
b5
b4
sync
Fig 24. Subcode output (upsampling disabled)
When upsampling is enabled, the IIS interface will run at 4 times the non upsampled
rate. The subcode bitperiod however will stay at the non-upsampled rate a shown on
Fig 25. This means that the IISSubO and IISSync signal will appear to be 4 times
slower relative to the IISWclk. In this case the receiver must use the IISWclk divided
by 4 to sample the subcode.
wclk
v4
v4_sync
b[7] = start
b[6]
S0
S1
b[5]
b[7] = start
b[6]
S0
2 x U.S. wclk periods
(0.5 x Non U.S. wclk period)
24 x U.S. wclk periods
(6 x Non U.S. wclk periods)
Fig 25. Subcode output (upsampling enabled)
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When slave mode is used, so no IISBclk gating, it’s also possible to use the
IISSubO(V4) output port as a true single-line interface. In that case the receiver
needs to sample the data on the line with a frequency equal to FIISWclk x 2 (since
subcode is output at a rate of 1 bit / half IISWclk). Two characteristics of the interface
can be used in this case to synchronise the bit and byte detection in the stream in
absence of an IISSync signal
„ The first bit (P-bit) of a subcode-byte is used as a start-bit and therefore always 1,
(so no real P-channel information available on the interface); in-between 2
subcode bytes there are 4 zero-bits. This can be used to identify the start of the
subcode bytes within the stream.
„ The Subcode syncs S0 and S1 are presented as all 0’s on the interface (even
P-channel), such that the last subcode byte of a subcode-frame, and the first byte
of the next frame are separated by 28 zero-bits. This can be used to identify the
start of the subcode-frames within the stream.
6.5.10 Motor
A block diagram of the motor interface is given in Fig 26.
Frequency / Tacho
Setpoint
Overflow detect
0
Tacho Freq
PLL Freq
Filling
Setpoint
FIFO
Filling
G
Sw
1
PDM/PWM
Modulator
Moto
PADS
Int
K I Ki_Mul
t
Sw
2
K F Kf_Mult
24T
delay
preset/
readback
GE
motor
Analog output stage gain
Fig 26. Motor Servo Block Diagram
It consists of a PI filter and a PWM/PDM modulator. When put in a closed loop, the
motor controller can control both speed/frequency and position error (FIFOFILL). It
can be operated as a P, I or PI controller, by switching on and off the appropriate
switches (SW1, SW2).
The frequency and position error integrator gain, KI and KF, and gain G are
programmable. Frequency and filling setpoints are programmable as well.
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The frequency input source can be selected between PLL frequency and 0. The
position input source is always FIFOfilling.
When operated in a stable operation point in closed loop, the motor controller will
regulate the frequency input source and the fifofilling to their respective setpoints, this
by speeding up/slowing down the motor by changing the DC content in the
PDM/PWM output motor signals.
All parameters can be configured by programming the motor registers.
6.5.10.1
Frequency setpoint
When operating the motor in CLV mode, based on EFM, for a certain overspeed, the
motor frequency setpoint to be programmed is given by
6

N ⋅ 4.3218 ×10 
MotorFrequencySetpoint [7:0] = 256 ⋅  1 – -------------------------------------
⋅
2.667
f

sys 
with fsys the system clock frequency and N the overspeed factor.
The setpoint can be programmed via register MotorFreqSet. The selection of the
motor frequency input is programmed via MotorGainSet2(MotorFreqSource).
6.5.10.2
Position error
The position error will be used to fine tune the motor speed during ’slave mode’, were
the incoming EFM-bitrate is locked on the programmed fixed IIS bclk output speed.
The setpoint must be chosen between 118 and 128, since this is the usable FIFOsize
in the decoder. See “Data Latency + FIFO operation” on page 48 for more info.
The setpoint can be programmed via register MotorFifoSet.
6.5.10.3
Motor control loop gains (KP, KF and KI)
The control loop gains are all programmable, through registers MotorGainSet1 and
MotorGainSet2. To be able to set integrator bandwidth low enough at high system
clock speeds an extra divider for the factors KI and KF is added. These factors can be
written through the register MotorMultiplier.
The resulting KI,tot is then the KI multiplied by KImult. The resulting KF,tot is then the
KF multiplied by KFmult. The integrator bandwidth must be scaled with the same
factor KImult.
Notes:
„ KFmult operates by sampling the input. E.g. for KFmult = 1, every sample of the
input is passed through to the integrator circuit, for a KFmult of 0.5, every 2nd
sample is passed through, for a KFmult of 0.25 every 4th sample is passed
through, and so on.
„ For a DC input signal, KF x KFmult should always give the same result. If however,
the input is varying quickly, the KF x KFmult combinations with the same product
will not always give the same result, especially for low values of KFmult, where the
sampling in the extreme becomes 1 out of every 128 samples. (The input samples
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to the block that performs the KFmult multiplication occur at a rate of 1 sample
every 24 system clock periods.). Sub-sampling might effect the actual resulting
gain.
6.5.10.4
Operation modes
The motor controller mode is programmed in register MotorControl. It can operate
open loop, just sending a fixed power to the motor, for start-up and stopping, closed
loop, or shut down. Also selection between PDM and PWM format is done in this
register.
Motor start and stop modes will put a fixed duty-cycle PWM or fixed density PDM
signal on the motor outputs. During start or stop, motor speed can be monitored by
reading MotorIntLSB and MotorIntMSB.
Motorov
When not setting the appropriate gains in the loop, an overflow might occur inside the
PWM/PDM modulator block, or in the programmable gain stage. This is signalled by
the MotorOv interrupt, which can be read back on InterruptStatus2. The interrupt
disappears when the overflow disappears.
Motorov can also automatically open SW1/SW2. This is enable by writing a ’1’ to bit
OvfSw in register MotorControl.
6.5.10.5
Writing, reading motor integrator value
It is possible to obtain the integrator value by reading the registers MotorIntLSB and
MotorIntMSB. The integrator can be written at the same location. By opening all
switches, the user can bypass the whole control and filter part, and just use the block
as a DAC towards the motor drivers. The control part could then be done in software.
6.5.10.6
Some notes on application motor servo
The motor servo can be used to control the motor during CLV playback and also
during CAV or pseudo-CLV lock-to-disc or jump mode.
„ In CLV mode both Sw1 and Sw2 must be closed
„ In CAV / pseudo-CLV mode Sw2 must be open and Sw1 may be open.
„ The motor servo will revolve the disc at the speed corresponding with the
frequency setpoint. In CLV mode with lock to EFM, the frequency setpoint must
be selected equal to the desired readout frequency of the HF-PLL
„ Accelerating the disc must be done in one of the start modes
„ Braking the disc must be done in one of the stop modes
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6.5.10.7
Tacho
Transition
detect
+
debounce
compare
T1
T2
T3
tacho
set
K tacho
tacho
interrupt
To
motor-loop
Fig 27. Tacho block diagram
The tacho circuit accepts the tacho input on the T1 or the T1-T2-T3 input, coming
from the hall sensors on the spindle motor. The Tacho block will measure the
frequency of the input pulses and filter the measurements by means of a
second-order low-pass filter - this filters off noise on the tacho signal.
The measured tacho frequency can be read by the microprocessor, can be used as a
frequency input to the motor control, and can be used to generate the tacho trip
frequency interrupt.
The relationship between the actual motor speed (in Hz) and the TachoFreq[7:0]
value read back in TBF (TachoFrequency) is given by
MotorFreq ⋅ Ktacho (7:0) ⋅ 2h ⋅ p
TachoFrequency (7:0) = ------------------------------------------------------------------------------------F sample
with
„ TachoFrequency(7:0) : the value read from register TBF ; when doing CAV
mode motor control, it is compared to the motor frequency setpoint programmed
in register MotorFreqSet ; this value is an unsigned value
„ MotorFreq is the actual angular velocity, in rounds per second (Hz)
„ Ktacho(7:0): gain-value written to register TBF
„ 2h : h is the number of hall sensors : 1 or 3, depending on motor and setting of bit
OnePinMode in register TBF.
„ p: the number of motor pole-pairs, usually 1
„ Fsample: sampling frequency of the filter; this can be configured via bits FSamSel in
register TBF;
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Tacho gain Ktacho
The tacho gain, Ktacho can be chosen so that the value read from TachoFrequency
in reg TBF is the motor frequency in Hz. However, it is advised to select Ktacho such
that a mimum amount of ripple is seen on the measured tacho frequency. This must
be tuned experimentally.
Tests have shown that with good selection of Ktacho and TachoSampleRate, a
minimum amount of variation on the measured frequency can be obtained.
Tacho trip frequency
It is possible for the software to be notified with an interrupt, when reaching a specific
speed during spin-up or spin-down. This is done by programming the desired
frequency trippoint in register TBF. When the tacho frequency goes above/below
this trippoint, an interrupt gets generated (bit 3 of register TBF). With bit 1
(TachoInterruptSelect) of register TBF , one can select if an interrupt must be
generated when the frequency goes above or below the trippoint.
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6.6 Digital Servo - PDSIC
The digital servo block on SAA7838 is an evolution of the design used on the
SAA7824 IC and is referred to as PDSIC - Parallel Digital Servo IC. The “parallel”
description refers to the microprocessor interface to the servo block - this is now a
high speed parallel interface, whereas it was a previously a serial interface on (e.g.
SAA7824 3/4 wire, I2C) the other features of the PDSIC are listed below.
„
„
„
„
„
„
„
„
„
„
„
„
6.6.1
Programmable ADC for CD-RW playback compatibility
Diode Signal Processing
Signal Conditioning
Focus and Radial Control System
Access Control
Sledge Control
Shock Detector
Defect Detector
Off-track Counting and Detection
Automatic closed-loop gain control available for focus and radial loops
Hi-Level features
Flexiable Servo
PDSIC Registers and servo RAM control
The servo block is controlled by two parts of the design - the servo control registers
which are used to control the writing of commands and parameters to the servo; and
the servo RAM. The Servo RAM has two roles, storage of the servo parameters and
capture of commands and parameters during the command process.
All of the servo-write commands consist of a command byte followed by a number of
parameter bytes (between 1 and 7), all of which have to be loaded into the DSIC
using a serial communication interface.
The command byte is the first to be loaded and can be considered as 2 nibbles. The
upper (most significant) nibble represents the command itself whilst the lower (least
significant) nibble tells the DSIC how many parameter bytes to expect. The command
byte gets placed into memory location 31h (called oldcom).
Subsequently, parameter bytes get loaded sequentially and these get placed into a
stack space that has been reserved within the memory (locations 30h down to 2Bh).
With each parameter byte that is loaded, the value in oldcom is decremented. In other
words, the byte count decreases until it reaches 0, when the DSIC knows it has a
complete servo command (a command byte and its full compliment of parameter
bytes). At this point, the DSIC acts upon the command and the appropriate function is
carried out based upon the values in the stack space.
There are two of special case servo commands that require a mention include
Write_parameter (opcode = A2h) and Write_decoder_reg (opcode = D1h).
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Write_parameter allows the micro-controller to write directly to any memory location.
It carries 2 parameter bytes; the memory address and the data that is to be written.
When this command is executed the command byte is loaded into oldcom and the
first parameter byte (<RAM_address>) is loaded onto the stack. The second
parameter byte (<data>) is loaded directly into the location specified by
<RAM_address>.
Write_decoder_reg allows decoder registers to be written to when the I2C interface is
being used. This command carries only one parameter byte, which is the decoder
register/data pair (2 nibbles). When this command is received by the DSIC, the
register/data pair is loaded into memory location 4Dh.
The servo-read commands operate slightly differently in that they carry no parameter
bytes and the lower nibble of the command byte is always 0 to indicate this. When the
DSIC receives a read command it will make certain information available (mostly from
memory, although some status information is retrieved from the decoder) on the
serial interface for collection by the micro-controller.
If a sequence of values are being read from the servo RAM (e.g. a series of values
related to a PID loop), it’s important to ensure that the values are consistent with each
other, i.e. the servo hasn’t updated some of the values during the period that they are
being read. To avoid this, an interrupt signal is available from the servo to the ARM
which raises an IRQ when it is safe to read related values. The interrupt generator
monitors these signals and raises an IRQ whenever the correct state is achieved.
Applying a pulse to the "Inreq_Clr" register bit will then clear the interrupt. If the interrupt is not cleared, it will automatically be reset when the valid reading state is no
longer true.
Fig 29 shows the operation of the IRQ signal. Int#1 shows the full duration of an interrupt that does not get cleared by the ARM. Int#2 and Int#3 are shown being cleared
by pulses being written to the inreq_clr register. The time between interrupts is
approximately 15µs and the total interrupt cycle time is ~60µs.
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IRQ cycle time of ~60µs
IRQ cycle time of ~60µs
IRQ cycle time of ~60µs
srv_fc0
srv_fc1
Int #1
IRQ
Int #2
Int #3
IRQ #2
cleared by
inreq_clr
pulse
IRQ #3
cleared by
inreq_clr
pulse
inreq_clr
Natural duration of
IRQ (~45µs)
Fig 28. Function of servo IRQ signal with respect to srv_fc0, srv_fc1 and inreq_clr
SAA7838 contains additional circuits to implement a servo feature called Flexible
servo.
The purpose of the flexible servo system is, in conjunction with the existing analogue
and digital LF path, to provide maximum flexibility in the use of the entire servo loop.
This scheme extends from the point of diode PDM generation at the analogue ADC
outputs through to the servo actuator signals (RA, FO,SL) themselves.
From a system perspective, the simplest configuration provides an LF path that is
equivalent to the hardware servo (DSICS) of the other audio devices such as
SAA7826, which uses the onboard hardware servo controller logic. However, an
alternative set-up will provide additional fine DC-offset compensation (in addition to
the coarse compensation already found in the analogue ADCs) and the potential for
full software servo control via the ARM microprocessor (full system configuration
details are given in the block diagrams below).
6.6.2
Diode Signal Processing
The photo detector in conventional two-stage three-beam Compact Disc systems
normally contains six discrete diodes. Four of these diodes (three for single foucault
systems) carry the Central Aperture signal (CA) while the other two diodes (satellite
diodes) carry the radial tracking information. The CA signals are summed into an
HF signal for the decoder function and are also differenced (after analogue to digital
conversion) to produce the low frequency focus control signals.
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The low frequency content of the six (five if single Foucault) photo diode inputs are
converted to Pulse-Density-Modulated bit streams by a multiplexed 6 bit ADC
followed by a digital PDM generation circuit. This supports a range of OPUs in
Voltage mode mechanisms by having sixteen selectable gain ranges in two sets, one
set for D1-D4 and the other for R1 and R2.
6.6.3
Signal Conditioning
The digital codes retrieved from the ADC and PDM generator are applied to logic
circuitry to obtain the various control signals. The signals from the central aperture
diodes are processed to obtain a normalised focus error signal.
D1 – D2 D3 – D4
FE n = --------------------- – --------------------D1 + D2 D3 + D4
where the detector set-up is assumed to be as shown in Fig.20.
In the event of single Foucault focusing method, the signal conditioning can be
switched under software control such that the signal processing is as follows:
D1 – D2
FE n = 2 × --------------------D1 + D2
The error signal, FEn, is further processed by a Proportional Integral and
Differential (PID) filter section.
An internal flag is generated by means of the central aperture signal and an adjustable
reference level. This signal is used to provide extra protection for the Track-Loss (TL)
generation, the focus start-up procedure and the dropout detection.
The radial or tracking error signal is generated by the satellite detector signals
R1 and R2. The radial error signal can be formulated as follows:
REs = (R1 - R2) × re_gain + (R1 + R2) × re_offset
where the index ‘s’ indicates the automatic scaling operation which is performed on the
radial error signal. This scaling is necessary to avoid non-optimum dynamic range
usage in the digital representation and reduces the radial bandwidth spread.
Furthermore, the radial error signal will be made free from offset during start-up of the
disc.
The four signals from the central aperture detectors, together with the satellite detector
signals generate a Track Position Signal (TPI) which can be formulated as follows:
TPI = sign [(D1 + D2 + D3 + D4) - (R1 + R2) × sum_gain]
where the weighting factor sum_gain is generated internally by the SAA7838 during
initialization.
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Fig 29. Detector Arrangement
6.6.4
6.6.4.1
Focus Servo System
Focus Start Up
Five initially loaded coefficients influence the start-up behaviour of the focus controller.
The automatically generated triangular voltage can be influenced by 3 parameters; for
height (ramp_height) and DC offset (ramp_offset) of the triangle and its steepness
(ramp_incr).
For protection against false focus point detections two parameters are available which
are an absolute level on the CA signal (CA_start) and a level on the FEn signal
(FE_start). When this CA level is reached then focus has been achieved.
With focus achieved and the level on the FEn signal is reached, the focus PID is
enabled to switch-on when the next zero crossing is detected in the FEn signal.
6.6.4.2
Focus Position Control Loop
The focus control loop contains a digital PID controller which has 5 parameters that
are available to the user. These coefficients influence the integrating (foc_int),
proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead,
part of foc_parm1) action of the PID and a digital low-pass filter (foc_pole_noise, part
of foc_parm2) following the PID. The fifth coefficient foc_gain influences the loop
gain. Figure 30 shows the transfer function of the controller, and the coefficients
which determine the behavior.
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Amplitude
(dB)
foc_gain
I
D
P
ω5
ω1
foc_int_strength
ω2
foc_int
ω3
foc_lead_length
ω4
foc_pole_noise
Frequency
(log Hz)
foc_pole_lead
Fig 30. Bode diagram of focus PID system
A simplified block diagram of the focus PID system is given in Figure 31
P
Focus Error, FEn
I
+
1/jω
Zero On
Defect
Or Shock
ω1
D
+
ω2/ω3
ω4
G
GE
Focus
Actuator
jω/ω3
1+jω/ω3
internal
external
Fig 31. Block diagram of focus PID system
By using a zero error signal, the actuator position can be held. This action is taken if a
defect or shock is encountered. The PID is followed by a low-pass filter to reduce
audible noise in the control loop.
The desired frequencies for the loop (ω1 to ω4) are used to calculate the coefficient
values (full tables are given in the HSI). An explanation of the different parameters in
these diagrams is given in Table 9.
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Focus PID parameters
Table 9:
Parameter
Controlled by
ω1
-
ω2
-
ω3
foc_parm1
foc_pole_lead; end of focus lead
(differentiating part)
ω4
foc_parm2
foc_pole_noise; low-pass function
following PID
ω3/ω2
foc_parm3
foc_lead_length; lead length
(proportional part)
ω1 = (ω5.ω3/ω2)
foc_int_strength
G
foc_gain
GE
end stage gain
6.6.4.3
Refer to
See table 2 of Hardware
Software Interface
Specification
Comment
Focus integrator bandwidth
Begin of focus lead
Integrator strength
Focus loop gain
Defined as peak-to-peak voltage
swing over focus actuator
Dropout detection
This detector can be influenced by one parameter (CA_drop). Focus will be lost and
the integrator of the PID will hold if the CA signal drops below this programmable
absolute CA level. When focus is lost it is assumed, initially, to be caused by a black
dot.
6.6.4.4
Focus loss detection and fast restart
Whenever focus is lost for longer than approximately 3 ms, it is assumed that the focus
point is lost. A fast restart procedure is initiated which is capable of restarting the focus
loop within 200 to 300 ms depending on the programmed coefficients of the
microcontroller.
6.6.4.5
Focus loop gain switching
The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or
divided by a factor of 2 during normal operation. The integrator value of the PID is
corrected accordingly. The differentiating (foc_pole_lead) action of the PID can be
switched at the same time as the gain switching is performed.
6.6.4.6
Focus automatic gain control loop
The loop gain of the focus control loop can be corrected automatically to eliminate
tolerances in the focus loop. This gain control injects a signal into the loop which is
used to correct the loop gain. Since this decreases the optimum performance, the gain
control should only be activated for a short time (for example, when starting a new
disc).
6.6.5
6.6.5.1
Radial servo system
Radial PID - On-Track Mode
When the radial servo is in on-track mode (i.e.: normal play mode), a PID controller is
active for the fast actuator, while the sledge is steered using either a PI or
pulsed-mode system. A simplified diagram of the radial PID system is given in Figure :
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Sat 1
Sat 2
Scaled
Radial Error
Normalizer
D
jω/ω3
ω4
+
1+jω/ω3
G
Zero On
Defect
Or Drop Out
GE
Radial
Actuator
I
+
1/jω
ω1
internal
ω2/ω3
P
external
Sledge error signal
Fig 32. Block Diagram of Radial PID System
An explanation of the different parameters is given below. The frequency response of
this system is given in Figure 33:
Table 10: Radial PID Parameters
Parameter
Controlled by
Refer to
ω1
-
ω2
-
ω3
rad_parm_play
End of radial lead (differentiating
part)
ω4
rad_pole_noise
Low-pass function following PID
ω3 / ω2
rad_length_lead
Lead length (proportional part)
ω5 = (ω1.ω2/ω3)
rad_int_strength
Integrator strength
G
rad_gain
GE
end stage gain
See table 2 of Hardware
Software Interface
Specification
Radial integrator bandwidth
Begin of radial lead
Radial loop gain
Defined as peak-to-peak voltage
swing over radial actuator
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Amplitude
(dB)
rad_gain
I
D
P
ω5
rad_int_strength
ω1
ω2
ω3
rad_int
rad_lead_length
rad_pole_lead
ω4
rad_pole_noise
Frequency
(log Hz)
Fig 33. Bode diagram of radial PID system
6.6.5.2
Level initialization
During start-up an automatic adjustment procedure is activated to set the values of the
radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI
level generation. The initialization procedure runs in a radial open loop situation and is
≤300 ms. This start-up time period may coincide with the last part of the motor start-up
time period:
„ Automatic gain adjustment: as a result of this initialization the amplitude of the
RE signal is adjusted to within +/-10% around the nominal RE amplitude
„ Offset adjustment: the additional offset in RE due to the limited accuracy of the
start-up procedure is less than +/-50 nm
TPI level generation: the accuracy of the initialization procedure is such that the duty
factor range of TPI becomes 0.4 < duty factor < 0.6 (default duty factor = TPI
HIGH/TPI period).
6.6.5.3
Dropout detection
This detector can be influenced by one parameter (CA_drop). Focus will be lost and
the integrator of the PID will hold if the CA signal drops below this programmable
absolute CA level. When focus is lost it is assumed, initially, to be caused by a black
dot.
6.6.5.4
Focus loss detection and fast restart
Whenever focus is lost for longer than approximately 3 ms, it is assumed that the focus
point is lost. A fast restart procedure is initiated which is capable of restarting the focus
loop within 200 to 300 ms depending on the programmed coefficients of the
microcontroller.
6.6.5.5
Focus loop gain switching
The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or
divided by a factor of 2 during normal operation. The integrator value of the PID is
corrected accordingly. The differentiating (foc_pole_lead) action of the PID can be
switched at the same time as the gain switching is performed.
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6.6.5.6
Focus automatic gain control loop
The loop gain of the focus control loop can be corrected automatically to eliminate
tolerances in the focus loop. This gain control injects a signal into the loop which is
used to correct the loop gain. Since this decreases the optimum performance, the gain
control should only be activated for a short time (for example, when starting a new
disc).
6.6.6
6.6.6.1
Radial servo system
Level initialization
During start-up an automatic adjustment procedure is activated to set the values of the
radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI
level generation. The initialization procedure runs in a radial open loop situation and is
≤300 ms. This start-up time period may coincide with the last part of the motor start-up
time period:
„ Automatic gain adjustment: as a result of this initialization the amplitude of the
RE signal is adjusted to within +/-10% around the nominal RE amplitude
„ Offset adjustment: the additional offset in RE due to the limited accuracy of the
start-up procedure is less than +/-50 nm
„ TPI level generation: the accuracy of the initialization procedure is such that the
duty factor range of TPI becomes 0.4 < duty factor < 0.6 (default duty factor = TPI
HIGH/TPI period).
6.6.6.2
Sledge control
The microcontroller can move the sledge in both directions via the steer sledge
command.
6.6.6.3
Tracking control
The actuator is controlled using a PID loop filter with user defined coefficients and
gain. For stable operation between the tracks, the S-curve is extended over 0.75 of the
track. On request from the microcontroller, S-curve extension over 2.25 tracks is used,
automatically changing to access control when exceeding those 2.25 tracks.
Both modes of S-curve extension make use of a track-count mechanism. In this mode,
track counting results in an ‘automatic return-to-zero track’, to avoid major
disturbances in the audio output and providing improved shock resistance. The sledge
is continuously controlled, or provided with step pulses to reduce power consumption
using the filtered value of the radial PID output. Alternatively, the microcontroller can
read the average voltage on the radial actuator and provide the sledge with step
pulses to reduce power consumption. Filter coefficients of the continuous sledge
control can be preset by the user.
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6.6.6.4
Access
The access procedure is divided into two different modes (see Table 11), depending
on the requested jump size.
Table 11:
ACCESS TYPE
JUMP SIZE
ACCESS SPEED
Actuator jump
brake_distance [1]
decreasing velocity
Sledge jump
brake_distance - 32 768
maximum power to
sledge<.Normal_XRef><.Superscrip
t>(1)
[1]Microcontroller presettable.
The access procedure makes use of a track counting mechanism, a velocity signal
based on a fixed number of tracks passed within a fixed time interval, a velocity set
point calculated from the number of tracks to go and a user programmable parameter
indicating the maximum sledge performance.
If the number of tracks remaining is greater than the brake_distance then the sledge
jump mode should be activated or, the actuator jump should be performed.
The requested jump size together with the required sledge breaking distance at
maximum access speed defines the brake_distance value.
During the actuator jump mode, velocity control with a PI controller is used for the
actuator. The sledge is then continuously controlled using the filtered value of the
radial PID output. All filter parameters (for actuator and sledge) are user
programmable.
In the sledge jump mode maximum power (user programmable) is applied to the
sledge in the correct direction while the actuator becomes idle (the contents of the
actuator integrator leaks to zero just after the sledge jump mode is initiated). The
actuator can be electronically damped during sledge jump. The gain of the damping
loop is controlled via the hold_mult parameter.
The fast track jumping circuitry can be enabled/disabled via the xtra_preset
parameter.
6.6.6.5
Radial automatic gain control loop
The loop gain of the radial control loop can be corrected automatically to eliminate
tolerances in the radial loop. This gain control injects a signal into the loop which is
used to correct the loop gain. Since this decreases the optimum performance, the gain
control should only be activated for a short time (for example, when starting a new
disc).
This gain control differs from the level initialization. The level initialization should be
performed first. The disadvantage of using the level initialization without the gain
control is that only tolerances from the front-end are reduced.
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6.6.7
Off-track counting
The Track Position Signal (TPI) is a flag which is used to indicate whether the radial
spot is positioned on the track, with a margin of ±1⁄4 of the track-pitch. In combination
with the Radial Polarity flag (RP) the relative spot position over the tracks can be
determined.
These signals can have uncertainties caused by:
„ Disc defects such as scratches and fingerprints
„ The HF information on the disc, which is considered as noise by the detector
signals.
In order to determine the spot position with sufficient accuracy, extra conditions are
necessary to generate a Track Loss signal (TL) and an off-track counter value. These
extra conditions influence the maximum speed and this implies that, internally, one of
the following three counting states is selected:
1. Protected state: used in normal play situations. A good protection against false
detection caused by disc defects is important in this state.
2. Slow counting state: used in low velocity track jump situations. In this state a fast
response is important rather than the protection against disc defects (if the phase
relationship between TL and RP of 1⁄2p radians is affected too much, the direction
cannot then be determined accurately).
3. Fast counting state: used in high velocity track jump situations. Highest obtainable
velocity is the most important feature in this state.
6.6.8
Defect detection
A defect detection circuit is incorporated into the SAA7838. If a defect is detected, the
radial and focus error signals may be zeroed, resulting in better playability. The defect
detector can be switched off, applied only to focus control or applied to both focus and
radial controls under software control (part of foc_parm1).
The defect detector has programmable set points selectable by the parameter
defect_parm.
6.6.9
Off-track detection
During active radial tracking, off-track detection has been realised by continuously
monitoring the off-track counter value. The off-track flag becomes valid whenever the
off-track counter value is not equal to zero. Depending on the type of extended
S-curve, the off-track counter is reset after 0.75 extend or at the original track in the
2.25 track extend mode.
Fig 34. Block Diagram of defect detector
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6.6.10 High level features
6.6.10.1
Automatic error handling
Three Watchdogs are present:
• Focus: detects focus dropout of longer than 3 ms, sets focus lost interrupt, switches
off radial and sledge servos, disables drive to disc motor
• Radial play: started when radial servo is in on-track mode and a first subcode frame
is found; detects when maximum time between two subcode frames exceeds the
time set by playwatchtime parameter; then sets radial error interrupt, switches radial
and sledge servos off, puts disc motor in jump mode
• Radial jump: active when radial servo is in long jump or short jump modes; detects
when the off-track counter value decreases by less than 4 tracks between two
readings (time interval set by jumpwatchtime parameter); then sets radial jump error,
switches radial and sledge servos off to cancel jump.
The focus Watchdog is always active, the radial Watchdogs are selectable via the
radcontrol parameter.
6.6.10.2
Automatic sequencers and timer interrupts
Two automatic sequencers are implemented (and must be initialized after power-on):
• Autostart sequencer: controls the start-up of focus, radial and motor
• Autostop sequencer: brakes the disc and shuts down servos.
When the automatic sequencers are not used it is possible to generate timer
interrupts, defined by the time_parameter coefficient.
6.6.11
Driver interface
The control signals (pins RA, FO and SL) for the mechanism actuators are pulse
density modulated. The modulating frequency can be set to either 1.0584 or
2.1168 MHz; controlled via the xtra_preset parameter. An analog representation of the
output signals can be achieved by connecting a 1st-order low-pass filter to the outputs.
During reset (i.e. RESET pin is held low) the RA, FO, and SL pins are
high-impedance. At all other times, when the laser is switched off, the RA and FO pins
output a 2MHz 50% duty cycle signal.
6.7 Flexible servo options
The flexi servo contains some additional hardware:
The flexi servo contains some additional hardware:
LPF: The low-pass filters construct a multi-bit representation of the incoming PDM
stream arriving from the analogue ADCs. The cut-off frequencies of all the filters are
user programmable from registers.
Fine DC offset subtraction: The fine DC offset values are held in CD-Slim registers.
These values can be subtracted from the LPF outputs.
Decimation filter: The decimation filter behavior is controlled by the LPF cut-off frequency selection and passes only the nth sample,
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Interrupt generator: This block raises an interrupt every time the output of the decimation filter becomes valid. The interrupt will either clear itself after a given time or
can be cleared by the ARM microprocessor.
Servo registers: Registers that exist within the Servo register address range.
Depending upon their function they will be either read-only or write/read registers.
Some of the flexible servo registers utilise the full 32-bits available to improve bandwidth performance for certain flexible servo operations.
Sigma-delta noise shaper: This block regenerates a PDM data stream from a given
multi-bit value, which is provided at its inputs.
6.7.1
Modes of operation
The flexible servo can be used in six main modes, they are identified below.
6.7.2
Hardware servo only
This mode uses the hardware servo (PDSIC) only without any additional processing
taking place on either the diode input signals or the servo output signals.
6.7.2.1
Hardware servo with fine offset compensation
This mode is the same as mode 1 but has the addition of the fine offset compensation
functionality in the digital domain. The fine offset compensation is additional to the
coarse offset compensation, which is available in all flexible servo modes.
6.7.2.2
Fully flexible servo
Also known as software servo. The diode signals have the fine offset applied to them
and are passed to registers for reading by the ARM microprocessor. The complete
servo functionality is implemented in software running on the ARM and the PDSICS
hardware servo is switched out of the loop entirely. The ARM calculates values,
which are used to generate servo signals for driving the mechanism actuators. The
PDM generation for the servo output signals is performed by hardware (the
Sigma-delta block on the diagram).
6.7.2.3
Pre-processing with hardware servo
The diode signals have the fine offset applied to them and are passed to registers for
reading by the ARM microprocessor. The ARM pre-processes these signals and they
are fed back to the inputs of the hardware servo via sigma-delta noise shapers. The
hardware servo (PDSICS) performs all the control functions (on the modified input
signals) and outputs the servo signals as mode 1.
6.7.2.4
Hardware servo with post-processing
The diode signals are passed directly to the hardware servo inputs (can be with or
without fine offset compensation added). The PDSICS servo output signals are
passed to registers for reading by the ARM microprocessor. The ARM executes any
post-processing it deems necessary on the signals and passes new values back
which are used to drive the mechanism actuators. The servo outputs are therefore
generated by the ARM, rather than the PDSICS, but based on the signals provided by
the PDSICS.
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6.7.2.5
Pre-processing with hardware servo plus post-processing
The diode signals have the fine offset applied to them and are passed to registers for
reading by the ARM microprocessor. The ARM pre-processes these signals and they
are fed back to the inputs of the hardware servo via sigma-delta noise shapers. The
hardware servo performs all the control and the servo output signals are passed to
registers for reading by the ARM microprocessor. The ARM executes any post-processing it deems necessary on the signals and passes new values back which are
used to drive the mechanism
6.8 BLOCK DECODER
The general features of the cMusic block decoder are:
„ cMusic compatible 32-bit microprocessor interface
„ channel decoder compatible C2I interface
„ segmentation manager compatible MiMeD2 interface
The main CD decode features of the cMusic block decoder are:
„ 16-bit data channel
„ Data byte swapping
„ Sync pattern (0x00, 0xFF, ..., 0xFF, 0x00) detection and interpolation
„ Main data descrambling (as per CD Yellow Book for Mode 1, Mode 2 Form 1
and Mode 2 Form 2 sectors)
„ Header (MSF address) monitoring, interpolation and repair
„ Firmware programmable 1-hit stream filtering on sector boundaries (CD-ROM
only)
„ Fast real-time C3 error correction (including automatic detection of Mode 1,
Mode 2 Form 1, and Mode 2 Form 2 sectors) using an internal 2 sector SRAM
„ Separate 8-bit subcode channel
„ Subcode P+Q channel deinterleaving and Q channel CRC checking
„ Subcode CD-Text Mode 4 packet extraction and CRC checking
„ Automatic subcode stream filtering associated with the data stream filter
„ Stream building (the main data stream, the block error byte, the error flag bytes
and the subcode channel will be merged into a single datastream for
transmission to the segment manager
„ Status Word Tag creation(which contains sector specific information)
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ARM AHB Register
Interface
Silicon Debug Bus
Silicon Debug Bus
Interface
(Block Verification)
CD-ROM C3 Error
Corrector
Debug
CD Rom Main Data
Read/Write/Debug
CD Main Data
CD-ROM Descrabler
CD-ROM Sync Detector
Sector Sync Flywheel
CD-ROM MSF
Flywheel
SRAM
CD Subcode Data
Fig 35. Block Decoder Datapath
CD Subcode Data
CD Subcode Datapath
Segmentation Manager
Interface
MiMeD
cMusIC (SAA7838)
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CD data
CD Main Data
C2I
Stream Filter
(Start/Stop)
One Chip CD Audio Device with Integrated MP3/WMA decoder
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6.8.1
Supported modes of operation
The block decoder supports CD-DA and CD-ROM decode transfers.
CD main data and subcode data are received from CDSlim over the C2I interface.
The main data is processed by the decode main datapath functions before being
passed to the memory controller. In the memory controller the main data is
assimilated with the subcode data and the C3 error corrector is run on CD-ROM main
data. The sector data and some status information are then passed to the cMusic
segment manager over the MiMeD2 interface.
6.8.2
Channel decoder to Block decoder Interface(C2I).
The data interface between the channel decoder and the block decoder is an asynchronous interface; channel decoder and the block decoder operate in independent
clock domains
Data is transferred over C2I in bursts of one EFM frame. Each EFM frame consists of
one subcode data byte plus twelve 16-bit main data words with associated reliability
flags.
CD-ROM data is word aligned as per the CD Yellow Book with the first word of the
CD-ROM sync pattern appearing on a left audio word. The subcode sync may or may
not be aligned with the first word of the CD-ROM sync pattern depending on the
alignment on the disc.
Subcode data is provided at the rate of one byte per EFM frame. Each byte contains
a bit for each of the subcode channels, P-W (P channel is bit 7).
The alignment between the main channel and the subcode channel must be the
same each time a sector is read.
6.8.3
Block decoder to Segmentation manager interface
The MiMeD2 interface is the data interface between the block decoder and the
cMusic segment manager. It is an asynchronous interface; the block decoder and
cMusic segment manager operate in independent clock domains.
Data is transferred over MiMeD2 in bursts of one sector. The size and speed of the
transfer is determined by the settings in the OP_CTRL register. Each transaction on
MiMeD2 is accompanied by a toggle of the bld_req signal. The data and flags are
updated on each transaction.
The transfer order is:
1) main data
1176 word16 (2352 bytes)
2) flags data (optional)
148 word16 (296 bytes)
3) subcode data (optional)
57 word16 (114 bytes)
4) status words
2 word16 (4 bytes)
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6.9 Segmentation Manager
6.9.1
General
The segmentation manager controls the flow of block decoded data from block
decoder and synchronous arm system bus.
The segmentation manager consists of a 2K buffer, that is accessible on the arm subsystem bus once the entire sector has been transferred from block decoder into the
segmentation buffer.
The DMA cycle is then initiated to transfer sector data from segmentation manager to
the arm processor memory for MP3 decoding to commence. The DMA transfers are
expected to be continues burst transfers to arm processor memory and completed at
sector boundary.
The segmentation manager register SEL_WRITE_MODE allows access to segmentation buffer either to block decoder MiMeD interface or the synchronous arm ystem
bus.
NOTE: Access to segmentation buffer from MiMeD interface are WRITE access only
or Access only from synchronous arm processor system bus are READ access only.
The segmentation buffer memory is 692 x 32 bit sram. The maximum number of 32
bit words per complete sector is 692 words.
6.9.2
Interrupt Generation
An interrupt is generated on completion of transfer very sector from block decoder.
The signal memory_full is used to generate an interrupt.
The Interrupt once serviced by software can be cleared by register write to inreq_clr
Once the interrupt has been triggered, it will remain asserted until cleared by the
inreq_clr signal. However, after being cleared, it is then free to fire again on the next
tranistion
Note that the register bit ’inreq_clr’ retains the latest value written by the Arm processor so a typical sequence will be to write logic 0 followed some time later by logic 1 in
order to return to the un-reset state.
6.9.3
Segmentation buffer ARM subsystem Interface
The segmentation buffer access to the arm subsystem is fully synchronous. The
implementation allows for minimum latency overhead so as to maximise the available
bandwidth on the ARM processor. The synchronous interface is AMBA AHB
compliant.
Note: The synchronous transfers are initiated by the DMA (Direct Memory Access)
controller. Once sector transfer have been initiated the recommendation is that these
transfers should not be interrupted and the application must allow for the complete
sector to be copied to main arm sub-system 110Kbyte internal memory.
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Objective Spec
cMusIC (SAA7838)
One Chip CD Audio Device with Integrated MP3/WMA decoder
Rev. 1.1 — 15 April 2005
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Fig 36. cMusIC Data Path with Segmentation Manager
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
6.10 Laser interface
The laser diode pre-amp function is built onto the SAA7838 and is illustrated in Fig.37.
The current can be regulated, up to 120mA, in four steps ranging from 58% up to full
power. The voltage derived from the monitor diode is maintained at a steady state by
the laser drive circuitry, regulating the current through the laser diode.
LPOWER
Vmon_dac
laser power
laser_pdmin
laser_comp_out
counter
DAC
laser_ion
MONITOR
UP/DOWN
DAC
LASER
laser_clk8MHz
laser_clk32MHz
Timing and Control Logic
Laser diode
&
Monitor
Fig 37. Block Diagram of laser control circuit
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One Chip CD Audio Device with Integrated MP3/WMA decoder
7. ARM7 System
The following diagram identifies the component parts which make up the system. The
following sections give you a top-level description of the individual blocks.
7.1 ARM7TDMI-S Microprocessor
The ARM7TDMI-S processor is a member of ARM family of 32bit microprocessors.
The ARM processor offers a high performance for low power consumption and low
gate count. The ARM architecture is based upon RISC (Reduced Instruction Set
Computer). The RISC principles provide the following keys benefits.
•High instruction throughput.
•Excellent real time interrupt response.
Table 12: Performance characteristics for ARM7TDMI-S
Process
Technology
Performance
MIPS/MHz
Power Consumption
(mW/MHz)
Maximum
Operating
Frequency
Typical
operating
frequency
requirements
for SAA7838
0.18um
0.9
0.39
76
76[1]
[1] The frequency of operation will be dependent on the performance required for the SAA7838
application and the Software complexity. MP3/WMA decoding would require most of high speed
peripherals to operate at this frequency. The MP3/WMA decoding library is implemented in
software.
The ARM7TDMI processor has 2 instruction sets:
i ). The 32 bit ARM instruction set
ii ).The 16 bit ARM thumb instruction.
The ARM uses a 3 stage pipeline to increase the throughput of the flow of instructions
to the processor. This would enable several operations to operate simultaneously and
the processor and memory systems to operate continuously.
The 3 stage pipelines can be defined in the following stages:
•Fetch Cycle. This is used to fetch the instruction from the memory.
•Decode Cycle. This is used to decode the registers, used in the instructions fetched.
•Execute Cycle. This is used to fetch the data from register banks, the shift and ALU
operations performed and the data is written bank into the memory.
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One Chip CD Audio Device with Integrated MP3/WMA decoder
The microprocessors have traditionally the same width for the instructions and data.
The 32 bit architecture would be more efficient in performance and could also
address a much larger address space as compared to 16 bit architectures. The code
density for 16 bit architecture would be much higher then 32 bit and the performance
would be greater than half of 32 bit performance.
The ARM thumb instructions concept addresses the issues when 16 bit instructions
are used but the performance required is of 32 bit architecture. Therefore the aim of
thumb instruction set can be summarised as follows:
Higher performance for 16 bit architecture, if 16 bit instructions are to be used.
The code density achieved for 16 bit instructions in a 32 bit architecture is much more
efficient usage of memory space.
7.2 Static memory Interface Unit (SMIU)
The AHB SRAM Controller implements an AHB slave interface to an external SRAM.
This interface is only available in the development version this device. The
specification of this interface is identified below
„ 32 bit AHB interface width
„ 76 MHz Maximum AHB operating frequency
„ Configured for low latency
„ Maximum of 2 SRAMs of 16MByte each can be accessible
„ 32 bit data
„ AMBA AHB Compliant
7.3 Program ROM Interface
The ROM interface provides an interface between the onboard 130K byte KEROM
memory and the ARM via the AHB bus. The specification of this interface is described
below
„ 32 bit AHB interface width
„ 76MHz Maximum AHB operating frequency
„ Configured for low latency
„ 32 bit data
„ AMBA AHB Compliant
The low latency architecture is optimised for low speed operation. No wait states are
used and the ROM control signals are taken directly from the AHB bus. This means
that the maximum frequency is likely to be limited by the speed at which the control
signals arrive from the AHB master
7.4 Boot Rom Interface
The ROM interface provides an interface between the onboard 42KByte KEROM
memory and the ARM via the AHB bus. The specification of this interface is described
below
„ 32 bit AHB interface width
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One Chip CD Audio Device with Integrated MP3/WMA decoder
„
„
„
„
76MHz Maximum AHB operating frequency
Configured for low latency
32 bit data
AMBA AHB Compliant
The low latency architecture is optimised for low speed operation. No wait states are
used and the ROM control signals are taken directly from the AHB bus. This means
that the maximum frequency is likely to be limited by the speed at which the control
signals arrive from the AHB master
7.5 Embedded KFlash Interface
The Kflash controller is an interface between the embedded flash memory device
and an AHB Bus.
The AHB Embedded Flash Controller connects embedded Flash memory devices
to the AHB-bus.
The Embedded Flash Controller supports full AHB-bus protocol and will never
generate a retry or split response.
The datapath between the memory instance and the controller is fixed to 128 bit
width to implement a double 128 bit cache line for creating SRAM like read
performance for cache hits.
The controller features a programmable number of wait cycles. A user can select
between 0 and 255 wait cycles, to allow for an optimal performance with the chosen
Flash instance at the clock frequency of specific application.
The design is optimized to interface to a ARM cpu with embedded JTAG tap
controller.
„ 32 bit AMBA AHB protocol with 76Mhz AHB operating frequency
„ AHB Reads for sub word and word size
„ AHB register interface
„ Zero wait states sustained read throughput on linear reads
„ Programmable wait state counter for read with cache miss, including zero wait
state for low frequencies
„ Cache for 2x128 bit words
„ JTAG interface access to flash
7.6 RAM Interface
The RAM interface provides an interface between the onboard 110K byte SRAM
memories and the ARM via the AHB bus. The specification of this interface is
described below
„ 32 bit AHB interface width
„ 76 MHz Maximum AHB operating frequency
„ Configured for low latency
„ AHB Reads and Writes for sub words and word sizes
„ 32 bit data
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One Chip CD Audio Device with Integrated MP3/WMA decoder
7.7 I2C Interface
This interface can be used as an I2C slave or master and is fully compliant with the
I2C bus specification. The specification of this interface is described below
„ Master/Slave Configurations
„ Address 0x6E
„ 76 MHz Maximum AHB operating frequency
„ 8.4672 MHz I2C operating frequency
„ 4 byte Rx FIFO Depth
„ 4 byte Tx FIFO Depth
„ Max I2C bus frequency of 400 kHz
„ Compatible with 7-bit and 10-bit addressing
7.8 General Purpose I/O’s
The GPIO’s are linked to the VPB bus. This interface provides individual control over
each bidirectional pin. Each pin can be configured to be an input, output or
bidirectional
„ 32 Bi-Directional IO’s
7.9 Interrupt Controller
„ 26 dedicated internal interrupts
„ 2external interrupt which has programmable polarity
„ Two interrupt types available Interrupt Request (IRQ) and Fast Interrupt Request
(FIQ)
„ Interrupts can be defined as IRQ or FRQ
„ One of 32 priority levels can be assigned to an interrupt
„ Interrupt priority threshold level
„ All interrupts can be masked
7.10 2 x UART Interfaces
„
„
„
„
„
„
„
„
„
„
„
„
„
„
Compatibility with the industry-standard 550,
16 deep transmit and receive FIFO size
Receive FIFO with error flags
Software selectable Baud Rate Generator including fractional pre-scaler
Four selectable Receive FIFO interrupt trigger levels
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun,
Break)
Maximum Uart Clock of 50MHz
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Fully programmable character formatting:
Auto-baud functionality for detecting the incoming baud-rate
False start-bit detection (debounce)
Complete status reporting capabilities
Line Break generation and detection
Loop-back controls for communications link fault isolation
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One Chip CD Audio Device with Integrated MP3/WMA decoder
„ Prioritized interrupt system controls
„ Optional ARM DMA controller flow control interface
„ AMBA VPB Compliant register Interface
7.11 2 x Timers
„ Conforms to the VLSI Peripheral BUS (VPB) interface specification.
„ Clock prescaler for external high frequency sources.
„ The VPB Timer operates on two fully independent clock domains, which are
:vpb_clk domain for accessing control and status registers(Max 76MHz). timer_clk
domain for the timer/counter function(Max 50MHz).
„ The VPB Timer can support up to four match registers, with :
- Continuous operation with optional interrupt generation on match.
- Stop on match with or without interrupt generation.
- Reset on match with or without interrupt generation.
„ Optional external match notification pins with the following features :
- Set low on match.
- Set high on match.
- Toggle on match.
- No action on match.
„ Up to four capture registers and capture trigger pins with optional interrupt
generation on a capture event.
„ Interrupt generation on match event, capture event
7.12 Watch Dog Timer
„ Configurable Watchdog feature, which include :
- Watchdog timer restart trigger protection by key.
- Watchdog timer reload value protection by key access sequence.
- Watchdog timer reset disable (for debug) protection by key.
„ Interrupt generation watchdog time-out event.
7.13 Real Time Clock
Zero wait state to access all registers from the VPB interface.
Provide coherent fraction and seconds time.
Requirement for external 32KHz crystal..
Alarm and tick interrupts will be generated even when the vpb clock is switched
off.
„ The VPB RTC interrupt
„
„
„
„
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One Chip CD Audio Device with Integrated MP3/WMA decoder
„ Real time clock and vpb clock may be asynchronous (the vpb clock frequency
could be higher or lower than the rtc clock frequency).
„ Maximum VPB slaves frequency of 50MHz
7.14 DMA Controller
The Simple (Small) DMA interface, or SDMA, is a small AHB bus master specifically
designed for bulk memory transfers over the ARM AHB bus..
For memory to memory transfers, the length of the operation is specified. When half
of this length is reached, or when the end of the transfer has been reached, the CPU
can be interrupted or the CPU can poll for notification of this event.
The SDMA controller has a maximum of 6 channels, Each channel can be configured
with its own source, destination, length and control information.
The SDMA controller is primarily dedicated from sector transfers from segmentation
manager to the ARM subsystem RAM.
„ Performs mem-to-mem copies in 2 AHB cycles, and mem to peripheral or
peripheral to mem in 3 AHB cycles
„ Supports byte, halfword and word transfers, and correctly allings it over the AHB
bus
„ Compatible with ARM flow control, for single requests (sreq), last single
requests(lsreq), terminal count info(tc) and dma clearing (clr).
„ cMusIC architecture supports little endian for data transfers
„ Contains maskable interrupts for each raw IRQ .
7.15 Backend audio processing
The backend audio processing entails the parallel to serial I2S conversion, sample
rate conversion for MP3 decoding and EBU data format generation.
7.15.1 Parallel to Serial I2S conversion
„
„
„
„
„
„
„
„
„
Can operate in both master and slave mode.
Capable of handling Philips. I2S format of 8, 16 and 32 bits word sizes.
Mono and stereo audio data supported.
The sampling frequency can range (in practice) from 16-48 kHz. (16, 22.05, 32,
44.1, 48)
Two fifo.s have been provided as data buffers, one for transmitting and onefor
reception, the depth of these fifo.s is configurable in HDLi.
Generates interrupt request.
Generates two dma requests.
Controls include reset, stop and mute options.
DMA Acknowledge signals
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7.15.2 Variable sample rate converter
The hardware sample rate conversion receives inputs from a varying input source.
The input is an IIS stereo audio signal. The sample rate conversion block converts
the frequency into a fixed 44.1kHz output audio signal. The block works on a fixed
frequency: 16.9344MHz (equals 384*44.1kHz, or 67.7376MHz/4).
The audio input frequencies can range between 8kHz and 48kHz. The block converts
the signal input an IIS signal with fixed sampling frequency of 44.1kHz.
The incoming IIS signal is stored in a buffer. The signal is upsampled by a variable
upsampling factor N. After a variable hold, the signal is downconverted with a fixed
downsample factor M.
Fig 38. VSRC Block Diagram
7.15.3 EBU Interface
The channel decoder contains a digital 1 wire EBU or SPDIF output interface. It
formats data according to the IEC958 specification. The EBU rate can be selected to
be 1 or 2X CD
For proper operation of the EBU interface, the IISBclk must be internally generated,
bitclock gating must be disabled and the following relation between EBUClk, IISBclk
and IIS-format must be true :
EBUClk = Wclk * 64
Some fields in the user channel of the EBU-stream can be filled in by software.
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One Chip CD Audio Device with Integrated MP3/WMA decoder
8. Characteristics
Table 13: Characteristics
VDDP = VDDA = 3.0 to 3.6V;
VDDD = 1.65 to 1.95V; Tamb = 25°C unless otherwise stated
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supply
VDDD
supply voltage, digital regulator
1.65
1.8
1.95
V
VDDP
supply voltage, digital pads
3.0
3.3
3.6
V
VDDA
supply voltage, analogue
3.0
3.3
3.6
V
supply current, digital
VDDD = 1.8V
9.6 [2]
15.5 [3]
42.4 [4]
mA
supply current, analogue
VDDA = 3.3V
63.6[2]
63.6[3]
63.6[4]
mA
supply current, peripheral
VDDP = 3.3V
11.1[2]
11.1[3]
11.1[4]
mA
IDD
D [1]
IDD
A [5]
IDDP [6]
Voltage Regulator
VDCD
supply voltage, digital core
1.65
1.8
1.95
V
VDCTX
supply voltage, analogue
(transmitter)
1.65
1.8
1.95
V
VDCRX
supply voltage, analogue (receiver)
1.65
1.8
1.95
V
Peak signal amplitude voltag5e
range. (16 steps)
20(uni)
-
960(uni)
mV
Gtolabs
Gain tolerance absolute
-20
-
20
%
Gtolrel
Relative gain tolerance between
channels within a pair
-3
0
3
%
Deccal range
DC offset cancellation range
-
+/-66(uni)
-
% fullscale
Analogue Section (VDDA = 3.3V; VSSA = 0; Tamb = 25 °C)
LF Path
Inputs: R1, R2
Vrange
+/-20(bi)
+/-960(bi)
+/-33(bi)
Cal acc
cancellation accuracy
-
+/- 4.1
-
% fullscale
FS
Sample frequency
-
4.2336
-
MHz
FSx2
Input frequency
-
8.4672
-
MHz
BW
Recovered bandwidth
20
-
-
kHz
Signal to noise ratio 0-20 kHz
55
-
-
dB
THD
0-20 kHz
-
-
-30
dB
Rinv
Rin voltage mode, BW=0-20 kHz
20
-
-
kΩ
Rinvtol
Voltage resistance tolerance
-30
-
30
%
Vcomin
Input common mode range
Vinoff
Input offset relative to
OPU_REF_OUT
1.6
-30
-
V
30
mV
HF Path
Inputs: D1, D2, D3 & D4
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One Chip CD Audio Device with Integrated MP3/WMA decoder
Table 13: Characteristics…continued
VDDP = VDDA = 3.0 to 3.6V;
VDDD = 1.65 to 1.95V; Tamb = 25°C unless otherwise stated
SYMBOL
PARAMETER
6 bit ADC input
range
peak-peak differential
CONDITIONS
MIN
TYP
1.4
6 bit ADC common
mode V
MAX
1.4
2
-
1.4
UNIT
V
V
Bandwidth
Up to 6X (2MHz x X-rate)
12
-
-
MHz
Phase delay
flatness
Up to 6X (10nS/X-rate)
-
-
1.66
nS
Noise
Signal to noise ratio 100Hz-12MHz
-
-
28
dB
Output Swing
At 6 MHz pk-pk
-
-
1
V
Distortion
At 6 MHz
-
-
-35
dB
Power supply
rejection
40
-
-
dB
Total gain range
2.4
-
38.4
dB
20
20
20
kΩ
27
-
46
MHz
Input impedance
Nominal
HF MON bandwidth -3dB point
Audio DAC
Input/Output: DAC_VREF Outputs: DAC_LN, DAC_LP, DAC_RN and DAC_RP
Signal to noise ratio A weighted
-
90
-
dB
THD
-
-
-80
dB
Total Harmonic Distortion @ 1 KHz
Audio Feature
Inputs: Aux_L & Aux_R
Signal to noise ratio refer to LF Path values
THD
refer to LF Path values
Laser Driver
Input: Monitor
lLaser_out max
output current
120
-
-
mA
Iint_noise
integrated noise (10Hz-100kHz)
-
-
-
nA
Tstartup
Time for laser to reach final value
1
-
-
mS
Vwindow
Voltage excursion at Monitor pin
(noise)
-1
-
1
mV
Vmonitor
DC voltage at monitor pin
sel180 = 0
145
-
155
mV
sel180 = 1
175
-
185
IREF Reference
Output: OPU_REF_OUT
V(Iref)
Bandgap reference voltage
1.14
1.2
1.26
V
Iout
output current
20
25
30
µA
Noise
output noise
-
µV
Oscillator
Pin: OSCIN (external clock)
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One Chip CD Audio Device with Integrated MP3/WMA decoder
Table 13: Characteristics…continued
VDDP = VDDA = 3.0 to 3.6V;
VDDD = 1.65 to 1.95V; Tamb = 25°C unless otherwise stated
SYMBOL
PARAMETER
VIN
input voltage
th
input high time
IIN
CIN
CONDITIONS
MIN
TYP
MAX
UNIT
-
VDDA/2
-
V
45
-
55
%
input leakage current
-20
-
+20
µA
input capacitance
-
-
7
pF
crystal [7]
8.4672
-
16.9344
MHz
relative to period
Pin: OSCOUT
fcsc
resonator
8.4672
-
16.9344
MHz
gm
mutual conductance at start-up
17
-
-
mS
CF
feedback capacitance
-
-
2
pF
COUT
output capacitance
-
-
7
pF
Rbias
internal bias resistor
-
200
-
kΩ
0.8x1.8
1.8
0.2x1.8
V
45
-
55
%
Real Time Clock
Oscillator
Pin: OSC_32K_IN (external clock)
VIN
input voltage
th
input high time
IIN
input leakage current
-
1.5
2.5
µA
CIN
input capacitance
-
-
7
pF
crystal [8]
32.768
32.768
32.768
KHz
resonator
32.768
32.768
32.768
KHz
gm
mutual conductance at start-up
-
4
-
mS
CF
feedback capacitance
-
-
-
pF
COUT
output capacitance
-
100
300
pF
Rbias
internal bias resistor
-
-
-
kΩ
relative to period
Pin: OSC_32K_OUT
fcsc
Pinning Characteristics
General
IINL
input current low
VIN = 0 No pull up -
-
1
µΑ
IINH
input current high
VIN = VDDP
-
-
1
µΑ
IOUTZ
tri-state output leakage
VO = 0 or VO =
VDDE
-
-
1
µΑ
ILatchup
I/O latch-up current
-(0.5xVDDP)< V
(1.5xVDDP)
100
-
-
mA
Tj < 125 Co
VESD
Human Body Model
kV
Machine model
V
Power
Imax
Max continuous current
-
-
98
mA
Digital Pins
DC Specifications - Input
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Table 13: Characteristics…continued
VDDP = VDDA = 3.0 to 3.6V;
VDDD = 1.65 to 1.95V; Tamb = 25°C unless otherwise stated
SYMBOL
PARAMETER
VIH
CONDITIONS
MIN
TYP
MAX
UNIT
input voltage HIGH
2.0
-
-
V
VIL
input voltage LOW
-
-
0.8
V
Vhys
hysteresis voltage
0.4
-
-
V
VDDP 0.4
-
-
-
0.4
V
-5
-
-
mA
-13
-
-
mA
-28
-
-
mA
4
-
-
mA
11
-
-
mA
27
-
-
mA
VOH = 0V
-
-
-45
mA
VOL = VDDP
-
-
50
mA
VIN = VDDP
20
50
75
µA
VIN = 5V
20
50
75
µA
VIN = 0V
-13
DC Specifications - Output
VOH
output voltage HIGH
VOL
output voltage LOW
IOH
output current high
5ns slew rate
output
V
VOH = VDDP-0.4V
12mA output
VOH = VDDP-0.4V
27mA output
VOH = VDDP-0.4V
IOL
output current low
5ns slew rate
output
VOL= 0.4V
12mA output
VOL = 0.4V
27mA output
VOL = 0.4V
IOH
high level short circuit current
(short period of time)
IOL
low level short circuit current
(short period of time)
IPD
IPU
pull-down current
pull-up current
-50
-40
µA
VDDP < VIN < 5.0V 0
0
0
µA
-
6
200
ns
-
4.0
-
ns
AC Specifications - Input
tR, tF
rise and fall time
AC Specifications - output
tTHL, tTLH
Output transition times
5ns slew rate
Load = 30 pF Transitions time read output
at 10% and 90% of output slope
12mA output
2.9
ns
27mA output
3.8
ns
Pin Parameters
Analogue inputs
Pins designated as Type “AI” (input)
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Table 13: Characteristics…continued
VDDP = VDDA = 3.0 to 3.6V;
VDDD = 1.65 to 1.95V; Tamb = 25°C unless otherwise stated
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
See analogue section
Pins designated as Type “AIO” (input, output)
See analogue section
Pins designated as Type “AO” (output)
See analogue section
Pin parameters for type “AOBS” (bi-directional)
VIH, VIL, VOH, VOL, IOH, IOL, tTHL/ tTLH (5ns slew rate), 12mA source/sink
Pin parameters for type “BTS” (bi-directional, tri-state & slew rate limited)
VIH, VIL, VOH, VOL, IOH, IOL, tTHL/ tTLH (5ns slew rate)
Pin parameters for type “BTSU” (bi-directional, tri-state, slew rate limited & pull-up)
VIH, VIL, VOH, VOL, IOH, IOL, tTHL/tTLH (5ns slew rate), IPU
Pin parameters for type “I” (input)
VIH, VIL, tri, tfi
Pin parameters for type “ID” (input &pull-down)
VIH, VIL, tri, tfi, Ipd
Pin parameters for type “IDH” (input, pull-down & hysteresis)
VIH, VIL, tri, tfi, Ipd, Vhys
Pin parameters for type “IU” (input, pull-up)
VIH, VIL, tri, tfi, Ipu
Pin parameters for type “IUH” (input, pull-up & hysteresis)
VIH, VIL, tri, tfi, Ipu, Vhys
Pin parameters for type “OS” (output)
VOH, VOL, IOH, IOL, 27mA source/sink
Pin parameters for type “OTS” (output, tri-state & slew rate limited)
VOH, VOL, IOH, IOL, tTHL/ tTLH (5ns slew rate)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
VDDD1 & VDDD2
Initial Reset value with primary clk = 76MHz , AHB & Decoder =4MHz
VDDA1, VDDA2, VDDA3 & DAC_VPOS
VDDP1, VDDP2 & VDDP3
It is recommended that the nominal running series resistance of the crystal or ceramic resonator is ≤60Ω
It is recommended that the nominal running series resistance of the crystal or ceramic resonator is ≤60Ω
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cMusIC (SAA7838)
One Chip CD Audio Device with Integrated MP3/WMA decoder
Rev. 1.1 — 15 April 2005
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Fig 39. Typical Application Diagram
IC Datasheet
Objective Spec
12NC
9. Application information
SAA7838
Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
10. Package outline
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
c
y
X
80
A
51
81
50
ZE
e
A
E HE
A2
(A 3)
A1
θ
wM
Lp
pin 1 index
bp
L
31
100
detail X
30
1
ZD
wM
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
max.
A1
A2
3.20
0.25
0.05
2.90
2.65
A3
bp
c
D (1)
E (1)
0.25
0.40
0.25
0.25
0.14
20.1
19.9
14.1
13.9
e
HD
HE
0.65
24.2
23.6
18.2
17.6
L
Lp
1.95
1.0
0.6
v
0.2
w
0.15
Z D (1) Z E (1)
y
0.1
0.8
0.4
1.0
0.6
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT317-2
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-08-01
99-12-27
MO-112
Fig 40. SOT317-2 Package Outline (LQFP100)
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IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
11. References
12. Glossary
AHB — ARM Advanced High Performance Bus
ARM — Advanced Risc Machines (32 bit microprocessor design)
ARM7TDMI-S — Specific version of ARM micro used in SAA7838 (ARM7 family)
FIFO — First in, first out
Flexi Servo — Hardware which gives the ARM micro access to the servo input
signals and to drive the servo outputs. Allows servo algorithms to be performed in
software in the ARM core.
GPAI — General Purpose Analogue Input
GPIO — General purpose input, output
HSI — Hardware Software Interface specification
I2C — Inter IC Communication format
I2S — Inter IC Sound format
PDSIC — Parallel Digital Servo IC (digital servo block within SAA7838)
RISC — Reduced Instruction Set Computer
Thumb — ARM 16bit instruction set
UART — Universal Asynchronous Receiver Transmitter
VPB — VLSI Peripheral Bus
VSRC -- Variable Sample Rate Converter
SMIU -- Static Memory Interface Unit
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IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
13. Revision history
Table 14: Revision history
Rev Date
CPCN
Description
0.1 1/02/05
Initial SAA7838 Release for CE Draft Editiont
1.0 1/04/05
Updated Diagrams for clarification, application circuitry added, Updated analogue
sections.
1.1 15/04/05
Ammendements to Pinning Names for Aux Inputs, Channel Decoder to clarify
Tacho CAV support, Updated Diagrams for better resolution, EBU Interface in
channel decoder. Register Names for Tacho to be added in version 1.2, once HSI
is updated
14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended. In these situations
reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
— for all BGA, HTSSON..T and SSOP..T packages
— for packages with a thickness ≥Š 2.5 mm
— for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
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IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
— larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
— smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
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One Chip CD Audio Device with Integrated MP3/WMA decoder
14.5 Package related soldering information
Table 15:
Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, USON, VFBGA
Wave
Reflow[2]
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
suitable
PLCC[5], SO, SOJ
suitable
suitable
recommended[5][6]
LQFP, QFP, TQFP
not
SSOP, TSSOP, VSO, VSSOP
not recommended[7]
suitable
CWQCCN..L[8],
not suitable
not suitable
PMFP[9],
WQCCN..L[8]
suitable
[1]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side,
the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the
heatsink on the top side, the solder might be deposited on the heatsink surface.
[5]
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6]
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7]
Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than
0.5 mm.
[8]
Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.
Hot bar soldering or manual soldering is suitable for PMFP packages.
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Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
15. Datasheet status
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS
[1]
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
16. Definitions
Short-form specification  The data in a short-form specification is extracted from
a full data sheet with the same type number and title. For detailed information see the
relevant data sheet or data handbook.
Limiting values definition  Limiting values given are in accordance with the
Absolute Maximum Rating System (IEC 60134). Stress above one or more of the
limiting values may cause permanent damage to the device. These are stress ratings
only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Application information  Applications that are described herein for any of these
products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
17. Disclaimers
Life support applications  These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can reasonably
be expected to result in personal injury. Philips Semiconductors customers using or
selling these products for use in such applications do so at their own risk and agree to
fully indemnify Philips Semiconductors for any damages resulting from such
application.
Right to make changes  Philips Semiconductors reserves the right to make
changes, without notice, in the products, including circuits, standard cells, and/or
software, described or contained herein in order to improve design and/or
performance. Philips Semiconductors assumes no responsibility or liability for the use
of any of these products, conveys no licence or title under any patent, copyright, or
mask work right to these products, and makes no representations or warranties that
these products are free from patent, copyright, or mask work right infringement,
unless otherwise specified.
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Philips Semiconductors
IC Datasheet
One Chip CD Audio Device with Integrated MP3/WMA decoder
18. Licenses
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
19. Ordering information
Table 16:
Ordering information
Type number
SAA7838
Package
Name
Description
Version
FP100
Plastic quad flat package
SOT317GF29
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One Chip CD Audio Device with Integrated MP3/WMA decoder
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