INTEGRATED CIRCUITS DATA SHEET SAA7377 Digital servo processor and Compact Disc decoder (CD7) Product specifications File under Integrated Circuits, IC01 1998 Jul 06 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.13 7.13.1 7.13.2 7.13.3 7.13.4 7.13.5 7.13.6 7.13.7 7.13.8 7.13.9 7.13.10 7.13.11 7.14 7.14.1 7.14.2 7.14.3 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 Decoder part Principle operational modes of the decoder Crystal frequency selection Standby modes Crystal oscillator Data slicer and clock regenerator Demodulator Frame sync protection EFM demodulation Subcode data processing Q-channel processing EIAJ 3 and 4-wire subcode (CD graphics) interfaces V4 subcode interface FIFO and error corrector Flags output (CFLG) C2FAIL Audio functions De-emphasis and phase linearity Digital oversampling filter Concealment Mute, full scale, attenuation and fade Peak detector DAC interface EBU interface Format KILL circuit The VIA interface Spindle motor control Motor output modes Spindle motor operating modes Loop characteristics FIFO overflow 7.5.3 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.8 7.9 7.9.1 7.10 7.11 7.12 7.12.1 7.12.2 7.12.3 7.12.4 1998 Jul 06 2 SAA7377 7.14.4 7.14.5 Servo part Diode signal processing Signal conditioning Focus servo system Radial servo system Off-track counting Defect detection Off-track detection high-level features Driver interface Laser interface Radial shock detector Microcontroller interface Microprocessor interface (4-wire bus mode) Microcontroller interface (I2C-bus mode) Summary of functions controlled by registers 0 to F Summary of servo commands Summary of servo command parameters 8 LIMITING VALUES 9 OPERATING CHARACTERISTICS 10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) 11 OPERATING CHARACTERISTICS (I2S-BUS TIMING) 12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 15.2 15.3 15.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 18 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 1 SAA7377 FEATURES • Single-speed mode • Full error correction strategy, t = 2 and e = 4 • Full CD graphics interface • All standard decoder functions implemented digitally on chip 2 • FIFO overflow concealment for rotational shock resistance GENERAL DESCRIPTION The SAA7377 is a single chip combining the functions of a CD decoder IC and digital servo IC. The decoder part is based on the SAA7345 (CD6) with an improved error correction strategy. The servo part is based on the TDA1301T (DSIC2) with improvements incorporated, extra features have also been added. • Digital audio interface (EBU), audio only • 2 and 4 times oversampling integrated digital filter, including fs mode • Audio data peak level detection Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application. • Kill interface for DAC deactivation during digital silence • All TDA1301 (DSIC2) digital servo functions, plus extra high-level functions • Low focus noise • Improved playability on ABEX TCD-721R, TCD-725 and TCD-714 discs • Automatic closed loop gain control available for focus and radial loops • Pulsed sledge support • Microcontroller loading LOW • High-level servo control option • High-level mechanism monitor • Communication may be via TDA1301/SAA7345 compatible bus or I2C-bus • On-chip clock multiplier allows the use of 8.4672 MHz crystal. 3 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage 3.4 5.0 5.5 V IDD supply current − 49 − mA fxtal crystal frequency 8 8.4672 35 MHz Tamb operating ambient temperature −40 − +85 °C Tstg storage temperature −55 − +125 °C 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7377GP QFP64 1998 Jul 06 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 × 14 × 2.7 mm 3 VERSION SOT393-1 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 5 SAA7377 BLOCK DIAGRAM handbook, full pagewidth VRL D1 D2 6 R1 R2 3 D3 4 5 VSSA2 VDDA1 VSSD1 VSSD3 VDDD1(P) VDDD3(C) D4 IrefT VSSA1 VSSA3 VDDA2 VSSD2 VSSD4 VDDD2(P) 7 10 1 12 16 2 19 32 39 49 56 30 47 59 8 CONTROL FUNCTION PREPROCESSING ADC 9 26 OUTPUT STAGES 27 28 VRH SCL SDA RAB SILD HFIN HFREF ISLICE Iref TEST1 TEST2 TEST3 SELPLL CRIN CROUT CL16 CL11 CL4 SBSY SFSY SUB RCK 11 Vref GENERATOR CONTROL PART 52 64 RESET 53 SL LDON MICROCONTROLLER INTERFACE 54 SAA7377 15 14 33 DIGITAL PLL 17 MOTOR CONTROL FRONT END 34 MOTO1 MOTO2 18 EFM DEMODULATOR 20 23 ERROR CORRECTOR TEST 29 61 FLAGS 60 21 22 24 CFLG SRAM 13 TIMING 25 C2FAIL AUDIO PROCESSOR RAM ADDRESSER 50 EBU INTERFACE 31 DOBM 35 36 SUBCODE PROCESSOR 38 PEAK DETECT 37 58 DECODER MICROCONTROLLER INTERFACE 46 SERIAL DATA INTERFACE VERSATILE PINS INTERFACE 45 44 KILL 57 62 63 42 41 40 43 MGR291 V1 V2 V3 V4 V5 Fig.1 Block diagram. 1998 Jul 06 FO 51 48 STATUS RA 4 KILL SCLK WCLK DATA TEST4 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 6 SAA7377 PINNING SYMBOL PIN DESCRIPTION VSSA1 1(1) analog ground 1 VDDA1 2(1) analog supply voltage 1 D1 3 unipolar current input (central diode signal input) D2 4 unipolar current input (central diode signal input) D3 5 unipolar current input (central diode signal input) VRL 6 reference voltage input for ADC D4 7 unipolar current input (central diode signal input) R1 8 unipolar current input (satellite diode signal input) R2 9 unipolar current input (satellite diode signal input) IrefT 10 current reference output for ADC calibration VRH VSSA2 11 12(1) reference voltage output from ADC analog ground 2 SELPLL 13 selects whether internal clock multiplier PLL is used ISLICE 14 current feedback output from data slicer HFIN 15 comparator signal input VSSA3 16(1) analog ground 3 HFREF 17 comparator common mode input Iref 18 reference current output pin (nominally 0.5VDD) VDDA2 19(1) TEST1 20 test control input 1; this pin should be tied LOW CRIN 21 crystal/resonator input CROUT 22 crystal/resonator output TEST2 23 test control input 2; this pin should be tied LOW CL16 24 16.9344 MHz system clock output CL11 25 11.2896 or 5.6448 MHz clock output (3-state) RA 26 radial actuator output analog supply voltage 2 FO 27 focus actuator output SL 28 sledge control output TEST3 29 test control input 3; this pin should be tied LOW VDDD1(P) 30(1) DOBM 31 VSSD1 32(1) digital supply voltage 1 for periphery bi-phase mark output (externally buffered; 3-state) digital ground 1 MOTO1 33 motor output 1; versatile (3-state) MOTO2 34 motor output 2; versatile (3-state) SBSY 35 subcode block sync output (3-state) SFSY 36 subcode frame sync output (3-state) RCK 37 subcode clock input SUB 38 P-to-W subcode output bits (3-state) VSSD2 39(1) V5 1998 Jul 06 40 digital ground 2 versatile output pin 5 5 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SYMBOL PIN SAA7377 DESCRIPTION V4 41 versatile output pin 4 V3 42 versatile output pin 3 (open-drain) KILL 43 kill output (programmable; open-drain) TEST4 44 test output pin; this pin should be left unconnected DATA 45 serial data output (3-state) WCLK 46 word clock output (3-state) VDDD2(P) 47(1) SCLK 48 VSSD3 49(1) digital supply voltage 2 for periphery serial bit clock output (3-state) digital ground 3 CL4 50 4.2336 MHz microcontroller clock output SDA 51 microcontroller interface data I/O line (open-drain output) SCL 52 microcontroller interface clock line input RAB 53 microcontroller interface R/W and load control line input (4-wire bus mode) SILD 54 microcontroller interface R/W and load control line input (4-wire-bus mode) n.c. VSSD4 RESET 55 not connected 56(1) digital ground 4 57 power-on reset input (active LOW) STATUS 58 VDDD3(C) 59(1) servo interrupt request line/decoder status register output (open-drain) C2FAIL 60 indication of correction failure output (open-drain) CFLG 61 correction flag output (open-drain) V1 62 versatile input pin 1 V2 63 versatile input pin 2 LDON 64 laser drive on output (open-drain) digital supply voltage 3 for core Note 1. All supply pins must be connected to the same external power supply voltage. 1998 Jul 06 6 Philips Semiconductors Product specifications 49 V SSD3 50 CL4 51 SDA 52 SCL 53 RAB 54 SILD SAA7377 55 n.c. 56 V SSD4 57 RESET 58 STATUS 60 C2FAIL 61 CFLG 62 V1 63 V2 64 LDON handbook, full pagewidth 59 V DDD3(C) Digital servo processor and Compact Disc decoder (CD7) V SSA1 1 48 SCLK VDDA1 2 47 V DDD2(P) D1 3 46 WCLK D2 4 45 DATA D3 5 44 TEST4 VRL 6 43 KILL D4 7 42 V3 R1 8 41 V4 SAA7377 R2 9 40 V5 IrefT 10 39 V SSD2 VRH 11 38 SUB VSSA2 12 37 RCK SELPLL 13 36 SFSY ISLICE 14 35 SBSY Fig.2 Pin configuration. 1998 Jul 06 7 VSSD1 32 DOBM 31 VDDD1(P) 30 TEST3 29 SL 28 FO 27 RA 26 CL11 25 CL16 24 TEST2 23 CROUT 22 CRIN 21 TEST1 20 33 MOTO1 VDDA2 19 VSSA3 16 Iref 18 34 MOTO2 HFREF 17 HFIN 15 MGR292 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7 CRIN, CROUT, CL16 and CL4: no interaction. Normal operation continues. FUNCTIONAL DESCRIPTION 7.1 Decoder part 7.1.1 V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction. Normal operation continues. PRINCIPLE OPERATIONAL MODES OF THE DECODER The decoding part operates at single-speed and supports a full audio specification. 7.2 CRYSTAL FREQUENCY SELECTION The SAA7377, which has an internal phase-locked loop clock multiplier, can be used with 33.8688, 16.9344 or 8.4672 MHz crystal frequencies by setting register B and SELPLL as shown in Table 1. The internal clock multiplier, controlled by SELPLL, should only be used if a 8.4672 MHz crystal, ceramic resonator or external clock is present. It should be noted that the CL11 output is a 5.6448 MHz clock if a 16.9344 MHz external clock is used. Table 1 Crystal oscillator The crystal oscillator is a conventional 2 pin design operating between 8 and 35 MHz. This oscillator is capable of operating with ceramic resonators and also with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are 8.4672, 16.9344 or 33.8688 MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled. A simplified data flow through the decoder part is illustrated in Fig.6. 7.1.2 SAA7377 SAA7377 Crystal frequency selection OSCILLATOR REGISTER B SELPLL CRYSTAL FREQUENCY (MHz) 00xx 0 33.8688 00xx 1 8.4672 01xx 0 16.9344 CROUT 8.4672 MHz CRIN 330 Ω 100 kΩ 7.1.3 STANDBY MODES 22 pF The SAA7377 may be placed in two standby modes selected by register B (it should be noted that the device core is still active) 22 pF MGR293 Fig.3 8.4672 MHz fundamental configuration. Standby 1: “CD-STOP” mode. Most I/O functions are switched off. Standby 2: “CD-PAUSE” mode. Audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. This is also called a “Hot Pause”. SAA7377 OSCILLATOR In the standby modes the various pins will have the following values; CROUT MOTO1 and MOTO2: put in high-impedance, PWM mode (standby 1 and RESET, operating in standby 2). Put in high-impedance, PDM mode (standby 1 and RESET, operating in standby 2). 330 Ω CRIN 3.3 µH 100 kΩ 10 pF SCL, SDA, SILD and RAB: no interaction. Normal operation continues. 10 pF 1 nF MGR294 SCLK, WCLK, DATA, CL11 and DOBM: 3-state in both standby modes. Normal operation continues after reset. 1998 Jul 06 33.8688 MHz Fig.4 33.8688 MHz overtone configuration. 8 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.3 The master counter is only reset if: Data slicer and clock regenerator • A sync coincidence detected; sync pattern occurs 588 ±1 EFM clocks after the previous sync pattern The SAA7377 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the crystal frequency clock (if SELPLL is set HIGH while using an 8.4672 MHz crystal, and register 4 is set to 0xxx). The slice level is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop (DPLL). • A new sync pattern is detected within ±6 EFM clocks of its expected position. The sync coincidence signal is also used to generate the PLL lock signal, which is active HIGH after 1 sync coincidence found, and reset LOW if, during 61 consecutive frames, no sync coincidence is found. The PLL lock signal can be accessed via the SDA or STATUS pins selected by register 2 and 7. Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization. Also incorporated in the demodulator is a Run Length 2 (RL2) correction circuit. Every symbol detected as RL2 will be pushed back to RL3. To do this, the phase error of both edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability. For certain applications an off-track input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the V1 pin if selected by register C. If this flag is HIGH, the SAA7377 will assume that its servo part is following on the wrong track and will flag all incoming HF data as incorrect. 7.4 7.4.1 SAA7377 7.4.2 EFM DEMODULATION The 14-bit EFM data and subcode words are decoded into 8-bit symbols. Demodulator FRAME SYNC PROTECTION A double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. crystal clock HF input 2.2 kΩ 2.2 nF HFIN 47 pF D Q HFREF DPLL 22 kΩ 1/2VDD Iref 22 nF 100 µA VSS VSSA 100 nF ISLICE VDD MGA368 - 1 100 µA VSSA Fig.5 Data slicer showing typical application components. 1998 Jul 06 9 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... V4 CD GRAPHICS INTERFACE 0 : reg D = xx01 V4 SUBCODE INTERFACE reg F SBSY SFSY SUB MICROCONTROLLER INTERFACE SDA SUBCODE PROCESSOR EBU INTERFACE DOBM reg A output from data slicer DIGITAL PLL AND DEMODULATOR 10 1 : reg 3 = xx10 (1fs mode) 0 : reg 3 ≠ xx10 FIFO 1 ERROR CORRECTOR FADE/MUTE/ INTERPOLATE DIGITAL FILTER 0 PHASE COMPENSATION Philips Semiconductors 0 Digital servo processor and Compact Disc decoder (CD7) handbook, full pagewidth 1998 Jul 06 1 1 : no pre-emphasis detected OR reg D = 01xx (de-emphasis signal at V5) 0 : pre-emphasis detected AND reg D ≠ 01xx 1 0 1 0 I2S-BUS INTERFACE SCLK WCLK DATA reg 3 reg 3 KILL KILL V3 MGD039 DE-EMPHASIS FILTER Product specifications Fig.6 Simplified data flow of decoder functions. SAA7377 reg C Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.5 7.5.1 Subcode data processing 7.5.3 V4 SUBCODE INTERFACE Data of subcode channels, Q-to-W, may be read via pin V4 if selected via register D. The format is similar to RS232 and is illustrated in Fig.8. The subcode sync word is formed by a pause of 200 µs minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between 11.3 µs and 90 µs. Q-CHANNEL PROCESSING The 96-bit Q-channel word is accumulated in an internal buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the SDA or STATUS pins, selected via register 2. Good Q-channel data may be read from SDA. 7.5.2 SAA7377 The subcode data is also available in the EBU output (DOBM) in a similar format. EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS) INTERFACES Data from all the subcode channels (P-to-W) may be read via the subcode interface, which conforms to EIAJ CP-2401. The interface is enabled and configured as either a 3-wire or 4-wire interface via register F. The subcode interface output formats are illustrated in Fig.7, where the RCK signal is supplied by another device such as a CD graphics decoder. handbook, full pagewidth SF0 SF1 SF2 SF3 SF97 P-W P-W P-W SF0 SF1 SF0 SF1 SBSY SFSY RCK SUB EIAJ 4-wire subcode interface SF0 SF1 SF2 SF3 SF97 P-W P-W P-W SFSY RCK SUB EIAJ 3-wire subcode interface SFSY RCK P Q R S T U V W SUB MBG410 Fig.7 EIAJ subcode (CD graphics) interface format. 1998 Jul 06 11 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 200 µs min W96 SAA7377 11.3 µs min 90 µs max 11.3 µs 1 Q R S T U V W 1 Q MGD038 Fig.8 Subcode format and timing on pin V4. 7.6 FIFO and error corrector 7.6.1 The SAA7377 has a ±8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level. The flags output pin CFLG (open-drain) shows the status of the error corrector and interpolator and is updated every frame (7.35 kHz). In the SAA7377 chip a 1-bit flag is present on the CFLG pin as illustrated in Fig.9. This signal shows the status of the error corrector and interpolator. The first flag bit, F1, is the absolute time sync signal, the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). This flag may also be used in a super FIFO or in the synchronization of different players. The output flags can be made available at bit 4 of the EBU data format (LSB of the 24-bit data word), if selected by register A. The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM). handbook, full pagewidth 33.9 µs F8 FLAGS OUTPUT (CFLG) 11.3 µs F1 33.9 µs F2 F3 F4 F5 F6 F7 F8 F1 MGD037 Fig.9 Flag output timing diagram. 1998 Jul 06 12 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) Table 2 SAA7377 Output flags F1 F2 F3 F4 F5 F6 F7 F8 0 x x x x x x x no absolute time sync 1 x x x x x x x absolute time sync x 0 0 x x x x x C1 frame contained no errors x 0 1 x x x x x C1 frame contained 1 error x 1 0 x x x x x C1 frame contained 2 errors x 1 1 x x x x x C1 frame uncorrectable x x x 0 0 x x 0 C2 frame contained no errors x x x 0 0 x x 1 C2 frame contained 1 error x x x 0 1 x x 0 C2 frame contained 2 errors x x x 0 1 x x 1 C2 frame contained 3 errors x x x 1 0 x x 0 C2 frame contained 4 errors x x x 1 1 x x 1 C2 frame uncorrectable x x x x x 0 0 x no interpolations x x x x x 0 1 x at least one 1 sample interpolation x x x x x 1 0 x at least one hold and no interpolations x x x x x 1 1 x at least one hold and one 1 sample interpolation 7.6.2 DESCRIPTION These attenuations do not include the sample-and-hold at the external DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled −0.5 dB down, to avoid overflow on full-scale sine wave inputs (0 to 20 kHz). C2FAIL The C2FAIL pin indicates that invalid data has occurred on the I2S-bus interface. However, due to the structure of the corrector it is impossible to determine which byte has failed. C2FAIL will go LOW for 140 µs when invalid data is detected, this data may then occur 15 ms before or after the pin is activated. 7.7 Table 3 Audio functions Filter specification PASS BAND STOP BAND ATTENUATION 0 to 9 kHz − ≤0.001 dB 19 to 20 kHz − ≤0.03 dB When pre-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to ≤ ±1° within the band 0 to 16 kHz. With de-emphasis the filter is not phase linear. − 24 kHz ≥25 dB − 24 to 27 kHz ≥38 dB − 27 to 35 kHz ≥40 dB − 35 to 64 kHz ≥50 dB − 64 to 68 kHz ≥31 dB − 68 kHz ≥35 dB If the de-emphasis signal is set to be available at V5, selected via register D, then the de-emphasis filter is bypassed. − 69 to 88 kHz ≥40 dB 7.7.1 7.7.2 DE-EMPHASIS AND PHASE LINEARITY DIGITAL OVERSAMPLING FILTER The SAA7377 contains a 2 to 4 times oversampling IIR filter. The filter specification of the 4 times oversampling filter is given in Table 3. 1998 Jul 06 13 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.7.3 Fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07 dB steps CONCEALMENT A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.10). 7.7.4 SAA7377 128 = full scale. 120 = −0.5 dB (i.e. full scale if oversampling filter used). 32 = −12 dB. 0 = mute. 7.7.5 MUTE, FULL SCALE, ATTENUATION AND FADE PEAK DETECTOR The peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via SDA. A digital level controller is present on the SAA7377 which performs the functions of soft mute, full scale, attenuation and fade; these are selected via register 0: Mute: signal reduced to 0 in a maximum of 128 steps; 3 ms. Attenuate: signal scaled by −12 dB. Full scale: ramp signal back to 0 dB level. From mute takes 3 ms. Interpolation OK Error Hold OK Error Interpolation Error Error OK OK MGA372 Fig.10 Concealment mechanism. 1998 Jul 06 14 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.8 SAA7377 DAC interface The SAA7377 is compatible with a wide range of digital-to-analog converters (DACs). Nine formats are supported and are given in Table 4. Figures 11 and 12 show the Philips I2S-bus and the EIAJ data formats respectively. All formats are MSB first and fs is 44.1 kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7. Table 4 DAC interface formats REGISTER 3 SAMPLE FREQUENCY NUMBER OF BITS SCLK (MHz) FORMAT INTERPOLATION 1110 fs 16/18(1) 2.1168 Philips I2S-bus; 16/18 bits(1) yes 0010 fs 16 2.1168 EIAJ 16 bits yes 0110 fs 18 2.1168 EIAJ 18 bits yes 0000 4fs 16 8.4672 EIAJ 16 bits yes 0100 4fs 18 8.4672 EIAJ 18 bits yes 1100 4fs 18 8.4672 Philips I2S-bus; 18 bits yes 0011 2fs 16 4.2336 EIAJ 16 bits yes 0111 2fs 18 4.2336 EIAJ 18 bits yes 1111 2fs 18 4.2336 Philips I2S-bus; 18 bits yes Note 1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data. 1998 Jul 06 15 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 15 14 0 1 LEFT CHANNEL DATA (WCLK NORMAL POLARITY) 15 14 0 WCLK MGD036 Fig.11 Philips I2S-bus data format (16-bit word length shown). Philips Semiconductors DATA 16 Digital servo processor and Compact Disc decoder (CD7) 1998 Jul 06 SCLK SCLK DATA 0 17 0 17 LEFT CHANNEL DATA WCLK SAA7377 Fig.12 EIAJ data format (18-bit word length shown). Product specifications MGD035 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.9 EBU interface 7.9.1 The bi-phase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC958 specification. The DOBM pin can be held LOW and selected via register A. Table 5 FORMAT The digital audio output consists of 32-bit words (‘subframes’) transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. Table 5 gives the formats. Format FUNCTION BITS DESCRIPTION Sync 0 to 3 − Auxiliary 4 to 7 not used; normally zero Error flags Audio sample 4 8 to 27 CFLG error and interpolation flags when selected by register A first 4 bits not used (always zero). 2’s compliment. LSB = bit 12, MSB = bit 27 Validity flag 28 valid = logic 0 User data 29 used for subcode data (Q-to-W) Channel status 30 control bits and category code Parity bit 31 even parity for bits 4 to 30 Table 6 SAA7377 Description of Table 5 FUNCTION DESCRIPTION Sync The sync word is formed by violation of the bi-phase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample (no block start) and sync W: word contains right sample. Audio sample Left and right samples are transmitted alternately. Validity flag Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This flag remains the same even if data is taken after concealment. User data Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. Channel status The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is given in Table 7. Table 7 Bit assignment FUNCTION Control BITS DESCRIPTION 0 to 3 copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis Reserved mode 4 to 7 always zero Category code 8 to 15 CD: bit 8 = logic 1, all other bits = logic 0 Clock accuracy 28 to 29 set by register A; 10 = level I; 00 = level II; 01 = level III Remaining 1998 Jul 06 16 to 27 and 30 to 191 always zero 17 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.10 SAA7377 2 pin kill: KILL active LOW indicates silence detected on left channel. V3 active LOW indicates silence detected on right channel. KILL circuit The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel before the digital filter. The output is switched active LOW when silence has been detected for at least 250 ms, or if mute is active. Two modes are available which can be selected by register C: 7.11 The VIA interface The SAA7377 has five pins that can be reconfigured for different applications (see Table 8). 1 pin kill: KILL active LOW indicates silence detected on both left and right channels. Table 8 Pin applications PIN NAME PIN NUMBER TYPE CONTROL REGISTER ADDRESS CONTROL REGISTER DATA V1 62 input 1100 xxx1 external off-track signal input − xxx0 internal off-track signal used, input may be read via decoder status bit; selected via register 2 FUNCTION V2 63 input − − V3 42 output 1100 xx0x KILL output for right channel − x01x output = 0 V4 41 V5 7.12 7.12.1 40 output output input may be read via decoder status bit; selected via register 2 − x11x output = 1 1101 0000 4-line motor drive (using V4 and V5) − xx01 Q-to-W subcode output − xx10 output = 0 − xx11 output = 1 1101 01xx de-emphasis output (active HIGH) − 10xx output = 0 − 11xx output = 1 7.12.1.1 Spindle motor control Pulse density output mode In the pulse density mode the motor output pin (MOTO1) is the pulse density modulated motor output signal. A 50% duty factor corresponds with the motor not actuated, higher duty factors mean acceleration, lower mean braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a 1 MHz internal clock signal. Possible application diagrams are illustrated in Fig.13. MOTOR OUTPUT MODES The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal ±8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes, selected by register 6, are supported: • Pulse density, 2-line (true complement output), 1 MHz sample frequency • PWM output, 2-line, 22.05 kHz modulation frequency 7.12.1.2 • PWM output, 4-line, 22.05 kHz modulation frequency In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output. The motor braking signal is pulse-width modulated on the MOTO2 output. The timing is illustrated in Fig.14. A typical application diagram is illustrated in Fig.15. • CDV motor mode. 1998 Jul 06 18 PWM output mode (2-line) Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 22 kΩ 22 kΩ MOTO1 + – 10 nF VDD MOTO2 + – M VSS 10 nF VSS 22 kΩ 22 kΩ MOTO1 + – 10 nF 22 kΩ M VSS 22 kΩ VSS VSS 22 kΩ VDD MGA363 - 1 Fig.13 Motor pulse density application diagrams. t rep = 45 µs t dead 240 ns MOTO1 MOTO2 Accelerate Brake MGA366 Fig.14 2-line PWM mode timing. + M 10 Ω 100 nF MOTO1 MOTO2 VSS MGA365 - 2 Fig.15 Motor 2-line PWM mode application diagram. 1998 Jul 06 19 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.12.1.3 SAA7377 PWM output mode (4-line) Using two extra outputs from the versatile pins interface, it is possible to use the SAA7377 with a 4-input motor bridge. The timing is illustrated in Fig.16. A typical application diagram is illustrated in Fig.17. t rep = 45 µs t dead 240 ns MOTO1 MOTO2 V4 V5 t ovl = 240 ns Accelerate MGA367 - 1 Brake Fig.16 4-line PWM mode timing. + V4 V5 M 10 Ω 100 nF MOTO1 MOTO2 VSS MGA364 - 2 Fig.17 Motor 4-line PWM mode application diagram. 1998 Jul 06 20 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.12.1.4 SAA7377 This voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. The following power limits are possible; CDV/CAV output mode In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin (carrier frequency = 300 Hz). The PLL frequency signal will be put in pulse-density modulated form (carrier frequency = 4.23 MHz) on the MOTO2 pin. The integrated motor servo is disabled in this mode. 100% (no power limit), 75%, 50%, or 37% of maximum. 7.12.3 LOOP CHARACTERISTICS The gain and crossover frequencies of the motor control loop can be programmed via registers 4 and 5. The following parameter values are possible; The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position (half full) will result in a PWM output of 60%. Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32 7.12.2 SPINDLE MOTOR OPERATING MODES Crossover frequency f4: 0.5 Hz, 0.7 Hz, 1.4 Hz, 2.8 Hz The operation modes of the motor servo is controlled by register 1 (see Table 9). Crossover frequency f3: 0.85 Hz, 1.71 Hz, 3.42 Hz. 7.12.4 In the SAA7377 decoder there is an anti-wind-up mode for the motor servo, selected via register 1. When the anti-wind-up mode is activated the motor servo integrator will hold if the motor output saturates. 7.12.2.1 FIFO OVERFLOW If FIFO overflow occurs during Play mode (e.g. as a result of motor rotational shock), the FIFO will be automatically reset to 50% and the audio interpolator tries to conceal as much as possible to minimise the effect of data loss. Power limit In start mode 1, start mode 2, stop mode 1 and stop mode 2, a fixed positive or negative voltage is applied to the motor. Table 9 Operating modes MODE DESCRIPTION Start mode 1 The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved and the PLL is reset. No disc speed information is available for the microcontroller. Start mode 2 The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status signals selectable via register 2 are valid. Jump mode Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is possible to read the subcode. Jump mode 1 Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large change in disc speed. Play mode FIFO released after resetting to 50%. Audio mute released. Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved. Stop mode 2 The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode. Off mode Motor not steered. 1998 Jul 06 21 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 MGA362 - 2 G f4 BW f3 f Fig.18 Motor servo mode diagram. 7.13 7.13.1 current generated by the external resistor on IrefT. In the application VRL is connected to VSSA1. The maximum input currents for a range of resistors is given Table 10. Servo part DIODE SIGNAL PROCESSING The photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. Four of these diodes (three for single Foucault systems) carry the central aperture signal (CA) while the other two diodes (satellite diodes) carry the radial tracking information. The CA signal is processed into an HF signal (for the decoder function) and LF signal (information for the focus servo loop) before it is supplied to the SAA7377. Table 10 Maximum current input DIODE INPUT CURRENT RANGE RIrefT (kΩ) The analog signals from the central and satellite diodes are converted into a digital representation using analog-to-digital converters (ADCs). The ADCs are designed to convert unipolar currents into a digital code. The dynamic range of the input currents is adjustable within a given range, which is dependent on the value of the external resistor connected to pin IrefT. The maximum current for the central diodes and satellite diodes is given in the following formulae; 2.4 × 10 6 I in ( max, central ) = ------------------------ µA R IrefT 1.2 × 10 6 I in ( max, satellite ) = ------------------------ µA R IrefT R1 AND R2 (µA) 220 10.909 5.455 240 10.000 5.000 270 8.889 4.444 300 8.000 4.000 330 7.273 3.636 360 6.667 3.333 390 6.154 3.077 430 5.581 2.791 470 5.106 2.553 510 4.706 2.353 560 4.286 2.143 620 3.871 1.935 This mode of VRH automatic adjustment can be selected by the preset latch command. Alternatively, the dynamic range of the input currents can be made dependent on the ADC reference voltages VRL and VRH. The maximum current for the central diodes and satellite diodes is given in the following formulae; The VRH voltage is internally generated by control circuitry which ensures that the VRH voltage is adjusted depending on the spread of internal capacitors, using the reference 1998 Jul 06 D1 TO D4 (µA) 22 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) I in ( max, central ) = f sys × ( V RH – V RL ) × 1.0 × 10 –6 I in ( max, satellite ) = f sys × ( V RH – V RL ) × 0.5 × 10 –6 The error signal, FEn, is further processed by a proportional integral and differential (PID) filter section. µA A Focus OK (FOK) flag is generated by means of the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for the track-loss (TL) generation, the focus start-up procedure and the drop out detection. µA Where fsys = 4.2336 MHz. VRH is generated internally, and there are 32 levels which can be selected under software control via the preset latch command. With this command the VRH voltage can be set to 2.5 V then modified, decremented one level or incremented, by re-sending the command the required number of times. In the application VRL is connected to VSSA1. 7.13.2 SAA7377 The radial or tracking error signal is generated by the satellite detector signals R1 and R2. The radial error signal can be formulated as follows; RE s = ( R1 – R2 ) × re_gain + ( R1 – R2 ) × re_offset where the index ‘s’ indicates the automatic scaling operation which is performed on the radial error signal. This scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. Furthermore, the radial error signal will be made free from offset during start up of the disc. SIGNAL CONDITIONING The digital codes retrieved from the ADCs are applied to logic circuitry to obtain the various control signals. The signals from the central aperture diodes are processed to obtain a normalised focus error signal. D1 – D2 D3 – D4 FE n = ---------------------- – ---------------------D1 + D2 D3 + D4 The four signals from the central aperture detectors, together with the satellite detector signals generate a track position signal (TPI) which can be formulated as follows; where the detector set-up is assumed as shown in Fig.19. TPI = sign [(D1 + D2 + D3 + D4) − (R1 + R2) × sum_gain] In the event of single Foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows; Where the weighting factor sum_gain is generated internally by the SAA7377 during initialization. D1 – D2 FE n = 2 × ---------------------D1 + D2 handbook, full pagewidth SATELLITE DIODE R1 SATELLITE DIODE R1 D1 D2 D1 D2 D4 D3 D3 SATELLITE DIODE R1 D1 D2 D3 D4 SATELLITE DIODE R2 SATELLITE DIODE R2 SATELLITE DIODE R2 single Foucault astigmatic focus double Foucault MBG422 Fig.19 Detector arrangement. 1998 Jul 06 23 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.13.3 7.13.3.1 action of the PID can be switched at the same time as the gain switching is performed. FOCUS SERVO SYSTEM Focus start-up 7.13.3.6 Five initially loaded coefficients influence the start-up behaviour of the focus controller. The automatically generated triangle voltage can be influenced by 3 parameters; for height (ramp_height) and DC offset (ramp_offset) of the triangle and its steepness (ramp_incr). 7.13.4 7.13.4.1 Focus position control loop The focus control loop contains a digital PID controller which has 5 parameters which are available to the user. These coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the PID and a digital low-pass filter (foc_pole_noise, part of foc_parm2) following the PID. The fifth coefficient foc_gain influences the loop gain. Offset adjustment: the additional offset in RE due to the limited accuracy of the start-up procedure is less than ± 50 nm. TPI level generation: the accuracy of the initialization procedure is such that the duty factor range of TPI becomes 0.4 < duty factor < 0.6 (definition of duty factor = TPI HIGH/TPI period). Drop-out detection 7.13.4.2 7.13.3.4 7.13.4.3 Sledge control The microcontroller can move the sledge in both directions via the steer sledge command. Focus loss detection and fast restart Tracking control The actuator is controlled using a PID loop filter with user defined coefficients and gain. For stable operation between the tracks, the S-curve is extended over ± 0.75 of the track. On request from the microcontroller, S-curve extension over ± 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. Whenever FOK is false for longer than approximately 3 ms, it is assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the programmed coefficients of the microcontroller. Focus loop gain switching Both modes of S-curve extension make use of a track-count mechanism. In this mode, track counting results in an ‘automatic return-to-zero track’, to avoid major music rhythm disturbances in the audio output for improved shock resistance. The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. The integrator value of the PID is corrected accordingly. The differentiating (foc_pole_lead) 1998 Jul 06 Level initialization Automatic gain adjustment: as a result of this initialization the amplitude of the RE signal is adjusted to within ±10% around the nominal RE amplitude. This detector can be influenced by one parameter (CA_drop). The FOK signal will become false and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false it is assumed, initially, to be caused by a black dot. 7.13.3.5 RADIAL SERVO SYSTEM During start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI level generation. The initialization procedure runs in a radial open loop situation and is ≤ 300 ms. This start-up time period may coincide with the last part of the motor start-up time period. If the FOK signal is true and the level on the FEn signal is reached, the focus PID is enabled to switch on when the next zero crossing is detected in the FEn signal. 7.13.3.3 Focus automatic gain control loop The loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). For protection against false focus point detections two parameters are available which are an absolute level on the CA-signal (CA_start) and a level on the FEn signal (FE_start). When this CA level is reached the FOK signal becomes true. 7.13.3.2 SAA7377 24 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 The sledge is continuously controlled, or provided with step pulses to reduce power consumption using the filtered value of the radial PID output. Alternatively, the microcontroller can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control can be preset by the user. 7.13.4.5 7.13.4.4 This gain control differs from the level initialization. The level initialization should be performed first. The disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced. The loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). Access The access procedure is divided into two different modes (see Table 11), depending on the requested jump size. Table 11 Access modes ACCESS TYPE JUMP SIZE(1) decreasing velocity Sledge jump maximum power to sledge(1) brake_distance - 32768 7.13.5 ACCESS SPEED Actuator jump 1 - brake_distance OFF-TRACK COUNTING The track position signal (TPI) is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of ±1⁄4 of the track-pitch. In combination with the radial polarity flag (RP) the relative spot position over the tracks can be determined. These signals are, however, afflicted with some uncertainties caused by; • Disc defects such as scratches and fingerprints Note • The HF information on the disc, which is considered as noise by the detector signals. 1. Microcontroller presettable. In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a track loss signal (TL) and an off-track counter value. These extra conditions influence the maximum speed and this implies that, internally, one of the following three counting states is selected; The access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity set point calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. 1. Protected state: used in normal play situations. A good protection against false detection caused by disc defects is important in this state. If the number of tracks remaining is greater than the brake_distance then the sledge jump mode should be activated, or, the actuator jump should be performed. The requested jump size together with the required sledge breaking distance at maximum access speed defines the brake_distance value. 2. Slow counting state: used in low velocity track jump situations. In this state a fast response is important rather than the protection against disc defects (if the phase relationship between TL and RP of 1⁄2π radians is affected too much, the direction cannot then be determined accurately). During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuously controlled using the filtered value of the radial PID output. All filter parameters (for actuator and sledge) are user programmable. 3. Fast counting state: used in high velocity track jump situations. Highest obtainable velocity is the most important feature in this state. In the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated). 1998 Jul 06 Radial automatic gain control loop 25 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.13.6 SAA7377 DEFECT DETECTION handbook, full pagewidth + sat1 − DECIMATION FILTER FAST FILTER SLOW FILTER DEFECT GENERATION PROGRAMMABLE HOLD-OFF defect output MBG421 sat2 Fig.20 Block diagram of defect detector. A defect detection circuit is incorporated into the SAA7377. If a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. The defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1). been crossed during time defined by jumpwatchtime parameter. 6. Autosequencer state change. 7. Autosequencer error. 8. Subcode interface blocked: the internal decoder interface is being used. The defect detector (see Fig.20) has programmable set points selectable by the parameter defect_parm. 7.13.7 It should be noted that if the STATUS pin output is selected via register 2 and either the microcontroller writes a different value to register 2 or the decoder interface is enabled then the STATUS output will change. OFF-TRACK DETECTION During active radial tracking, off-track detection has been realised by continuously monitoring the off-track counter value. The off-track flag becomes valid whenever the off-track counter value is not equal to zero. Depending on the type of extended S-curve, the off-track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode. 7.13.8 7.13.8.1 7.13.8.2 The decoder interface allows registers 0 to F to be programmed and subcode Q-channel data to be read via servo commands. The interface is enabled/disabled by the preset latch command (and the xtra_preset parameter). 7.13.8.3 HIGH-LEVEL FEATURES Automatic error handling Three watchdogs are present: Interrupt mechanism and STATUS pin 1. Focus: detects focus drop out of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos, disables drive to disc motor. The STATUS pin is an output which is active LOW, its output is selected by register 7 to be either the status bit (active LOW) selected by register 2 (only available in 4-wire bus mode) or the interrupt signal generated by the servo part. 2. Radial play: started when radial servo is on-track mode and a first subcode frame is found. Detects when maximum time between two subcode frames exceeds time set by playwatchtime parameter; then sets radial error interrupt, switches radial and sledge servos off, puts disc motor in jump mode. 8 signals from the interrupt status register are selectable from the servo part via the interrupt_mask parameter. The interrupt is reset by sending the read high-level status command. The 8 signals are as follows: 3. Radial jump: active when radial servo in long jump or short jump modes. Detects when the off-track counter value decreases by less than 4 tracks between two readings (time interval set by jumpwatchtime parameter); then sets radial jump error, switches radial and sledge servos off to cancel jump. 1. Focus lost: drop out of longer than 3 ms. 2. Subcode ready. 3. Subcode absolute seconds changed. 4. Subcode discontinuity detected: new subcode time before previous subcode time, or more than 10 frames later than the previous subcode time. The focus watchdog is always active, the radial watchdogs are selectable via the radcontrol parameter. 5. Radial error: during radial on-track, no new subcode frame occurs within time defined by playwatchtime parameter. During radial jump, less than 4 tracks have 1998 Jul 06 Decoder interface 26 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.13.8.4 During reset (i.e. RESET pin is held LOW) the RA, FO and SL pins are high impedance. Automatic sequencers and timer interrupts Two automatic sequencers are implemented (and must be initialized after power-on): 7.13.10 LASER INTERFACE 1. Autostart sequencer: controls the start-up of focus, radial and motor. The LDON pin (open-drain output) is used to switch the laser off and on. When the laser is on the output is high impedance. The action of the LDON pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active. 2. Autostop sequencer: brakes the disc and shuts down servos. When the automatic sequencers are not used it is possible to generate timer interrupts, defined by the time_parameter coefficient. 7.13.8.5 7.13.11 RADIAL SHOCK DETECTOR The shock detector (see Fig.21) can be switched on during normal track following, and detects within an adjustable frequency whether disturbances in the radial spot position relative to the track exceed an adjustable level (controlled by shock_level). Every time the radial tracking error (RE) exceeds this level the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4. High-level status The read high-level status command can be used to obtain the interrupt, decoder, autosequencer status registers and the motor start time. Use of the read high-level status command clears the interrupt status register, and re-enables the subcode read via a servo command. 7.13.9 DRIVER INTERFACE The shock detection level is adjustable in 16 steps from 0 to 100% of the traverse radial amplitude which is sent to an amplitude detection unit via an adjustable band-pass filter (controlled by sledge_parm1); lower corner frequency can be set at either 0 or 20 Hz, and upper corner frequency at 750 or 1850 Hz. The shock detector is switched off automatically during jump mode. The control signals (pins RA, FO and SL) for the mechanism actuators are pulse density modulated. The modulating frequency can be set to either 1.0584 MHz (DSD mode) or 2.1168 MHz; controlled via the xtra_preset parameter. An analog representation of the output signals can be achieved by connecting a first-order low-pass filter to the outputs. handbook, full pagewidth RE HIGH-PASS FILTER (0 or 20 Hz) SAA7377 LOW-PASS FILTER (750 or 1850 Hz) AMPLITUDE DETECTION SHOCK OUTPUT MGC914 Fig.21 Block diagram of radial shock detector. 1998 Jul 06 27 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.14 MOTSTART1: HIGH if motor is turning at 75% or more of nominal speed. Microcontroller interface Communication on the microcontroller interface can be set-up in two different modes: MOTSTART2: HIGH if motor is turning at 50% or more of nominal speed. 1. 4-wire bus mode: protocol compatible with SAA7345 (CD6) and TDA1301 (DSIC2) where: MOTSTOP: HIGH if motor is turning at 12% or less of nominal speed. Can be set to indicate 6% or less (instead of 12% or less) via register E. a) SCL = serial bit clock b) SDA = serial data PLL Lock: HIGH if sync coincidence signals are found. c) RAB = R/W control and data strobe (active HIGH) for writing to registers 0 to F, reading status bit selected via register 2 and reading Q-channel subcode. V1: follows input on V1 pin. V2: follows input on V2 pin. MOTOR-OV: HIGH if the motor servo output stage saturates. d) SILD = R/W control and data strobe (active LOW) for servo commands. 2. I2C-bus SAA7377 FIFO-OV: HIGH if FIFO overflows. I2C-bus mode: protocol where SAA7377 behaves as slave device, activated by setting RAB = HIGH and SILD = LOW where: SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV + FIFO-OV + servo interrupt signal + OTD (HIGH if shock detected). a) I2C-bus slave address (write mode) = 30H. LA-SHOCK: latched SHOCK signal. b) I2C-bus slave address (read mode) = 31H. The status read protocol is shown in Fig.24. It should be noted that SILD must be held HIGH. c) Maximum data transfer rate = 400 kbits/s It should be noted that only servo commands can be used therefore, writing to registers 0 to F, reading decoder status and reading Q-channel subcode data must be performed by servo commands. 7.14.1 7.14.1.1 7.14.1.4 To read the Q-channel subcode direct in the 4-wire bus mode, the SUBQREADY-I signal should be selected as status signal. The subcode read protocol is illustrated in Fig.25. MICROCONTROLLER INTERFACE (4-WIRE BUS MODE) It should be noted that SILD must be held HIGH; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation; when enough subcode has been read (1 to 96 bits), terminate reading by pulling RAB LOW. Writing data to registers 0 to F The sixteen 4-bit programmable configuration registers, 0 to F (see Table 12), can be written to via the microcontroller interface using the protocol shown in Fig.22. Alternatively, the Q-channel subcode can be read using a servo command as follows: It should be noted that SILD must be held HIGH; A3 to A0 identifies the register number and D3 to D0 is the data; the data is latched into the register on the LOW-to-HIGH transition of RAB. 7.14.1.2 • Use the read high-level status command to monitor the subcode ready signal. • Send the read subcode command, and read the required number of bytes (up to 12). Writing repeated data to registers 0 to F • Send the read high-level status command; to re-enable the decoder interface. The same data can be repeated several times (e.g. for a fade function) by applying extra RAB pulses as shown in Fig.23. It should be noted that SCL must stay HIGH between RAB pulses. 7.14.1.3 7.14.1.5 Behaviour of the SUBQREADY-I signal When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I status signal will react as shown in Fig.26. Reading decoder status information on SDA There are several internal status signals, selected via register 2, which can be made available on the SDA line; When the CRC is good and the subcode is being read, the timing in Fig.27 applies. SUBQREADY-I: LOW if new subcode word is ready in Q-channel register. 1998 Jul 06 Reading Q-channel subcode 28 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) If t1 (SUBQREADY-I status LOW to end of subcode read is below 2.6 ms, then t2 = 13.1 ms (i.e. the microcontroller can read all subcode frames if it completes the read operation within 2.6 ms after the subcode is ready). If this criterion is not met, it is only possible to guarantee that t3 will be below 26.2 ms (approximately). 7.14.2 The sequence for a write data command (that requires 3 data bytes) is as follows; • Send START condition • Send address 30H (write) • Write command byte Write servo commands • Write data byte 1 A write data command is used to transfer data (a number of bytes) from the microcontroller, using the protocol shown in Fig.28. The first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. • Write data byte 2. • Write data byte 3 • Send STOP condition. It should be noted that more than one command can be sent in one write sequence. It should be noted that RAB must be held LOW; the command or data is interpreted by the SAA7377 after the HIGH-to-LOW transition of SILD; there must be a minimum time of 70 µs between SILD pulses. 7.14.1.7 MICROCONTROLLER INTERFACE (I2C-BUS MODE) Bytes are transferred over the interface in groups (i.e. servo commands) of which there are two types: write data commands and read data commands. If subcode frames with failed CRCs are present, the t2 and t3 times will be increased by 13.1 ms for each defective subcode frame. 7.14.1.6 SAA7377 The sequence for a read data command (that reads 2 data bytes) is as follows; • Send START condition Writing repeated data in servo commands • Send address 30H (write) The same data byte can be repeated by applying extra SILD pulses as shown in Fig.29. SCL must stay HIGH between the SILD pulses. • Write command byte 7.14.1.8 • Send address 31H (read) • Send STOP condition. • Send START condition Read servo commands • Read data byte 1 A read data command is used to transfer data (status information) to the microcontroller, using the protocol shown in Fig.30. The first byte written determines the type of command. After this byte a variable number of bytes can be read. It should be noted that RAB must be held LOW; after the end of the command byte (LOW-to-HIGH transition on SILD) there must be a delay of 70 µs before reading data is started (i.e the next HIGH-to-LOW transition on SILD); there must be a minimum time of 70 µs between SILD pulses. 1998 Jul 06 • Read data byte 2 • Send STOP condition. It should be noted that the timing constraints specified for the read and write servo commands must still be adhered to. 29 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) A3 A2 A1 SDA (SAA7377) A0 D3 D2 D1 D0 high-impedance MGR295 Fig.22 Microcontroller write protocol for registers 0 to F. RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) A3 SDA (SAA7377) A2 A1 A0 D3 D2 D1 D0 high-impedance MGR296 Fig.23 Microcontroller write protocol for registers 0 to F (repeat mode). RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) high-impedance SDA (SAA7377) STATUS MGR297 Fig.24 Microcontroller read protocol for decoder status on SDA. 1998 Jul 06 30 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 RAB (microcontroller) SCL (microcontroller) CRC OK SDA (SAA7377) Q1 Q2 Q3 Qn–2 Qn–1 Qn STATUS MGR298 Fig.25 Microcontroller protocol for reading Q-channel subcode. RAB (microcontroller) SCL (microcontroller) SDA (SAA7377) high impedance CRC OK CRC OK 10.8 ms 15.4 ms 2.3 ms READ start allowed Fig.26 SUBQREADY-I status timing when no subcode is read. 1998 Jul 06 31 MGR299 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 t2 t1 t3 RAB (microcontroller) SCL (microcontroller) SDA (SAA7377) Q1 Q2 Q3 Qn MGR300 Fig.27 SUBQREADY-I status timing when subcode is read. handbook, full pagewidth SILD (microcontroller) SCL (microcontroller) SDA (microcontroller) D7 D6 D5 D4 D3 D2 D1 D0 command or data byte SDA (SAA7377) high-impedance microcontroller write (one byte: command or data) SILD (microcontroller) SDA (microcontroller) COMMAND DATA1 DATA2 DATA3 MGR301 microcontroller write (full command) Fig.28 Microcontroller protocol for write servo commands. 1998 Jul 06 32 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 handbook, full pagewidth SILD (microcontroller) SDA (microcontroller) COMMAND DATA1 MBG413 microcontroller write (full command) Fig.29 Microcontroller protocol for repeated data in write servo commands. SILD handbook, full pagewidth (microcontroller) SCL (microcontroller) SDA (SAA7377) D7 D6 D5 D4 D3 D2 D1 D0 data byte microcontroller read (one data byte) SILD (microcontroller) DATA1 SDA (SAA7377) SDA (microcontroller) DATA2 DATA3 COMMAND MGR302 microcontroller read (full command) Fig.30 Microcontroller protocol for read servo commands. 1998 Jul 06 33 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.14.3 SAA7377 SUMMARY OF FUNCTIONS CONTROLLED BY REGISTERS 0 TO F Table 12 Registers 0 to F REGISTER 0 (fade and attenuation) 1 (motor mode) 2 (status control) 3 (DAC output) 1998 Jul 06 DATA 0000 0000 mute 0010 attenuate − 0001 full scale − 0100 step down − 0001 0010 0011 FUNCTION INITIAL(1) ADDRESS reset − 0101 step up x000 motor off mode x 001 motor stop mode 1 − x010 motor stop mode 2 − reset x011 motor start mode 1 − x100 motor start mode 2 − x101 motor jump mode − x111 motor play mode − x110 motor jump mode 1 − 1xxx anti-windup active − 0xxx anti-windup off reset 0000 status = SUBQREADY-I reset 0001 status = MOTSTART1 − 0010 status = MOTSTART2 − 0011 status = MOTSTOP − 0100 status = PLL Lock − 0101 status = V1 − 0110 status = V2 − 0111 status = MOTOR-OV − 1000 status = FIFO overflow − 1001 status = shock detect − 1010 status = latched shock detect − 1011 status = latched shock detect reset − 1100 I2S-bus; 1111 I2S-bus; 18-bit; 2fs mode − 1110 I2S-bus; − 0000 EIAJ; 16-bit; 4fs − 0011 EAIJ; 16-bit; 2fs − 0010 EIAJ; 16-bit; fs − 0100 EIAJ; 18-bit; 4fs − 0111 EIAJ; 18-bit; 2fs − 0110 EIAJ; 18-bit; fs − 18-bit; 4fs mode 16-bit; fs mode 34 reset Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) REGISTER 4 (motor gain) 5 (motor bandwidth) 6 (motor output configuration) 7 (DAC output and status control) DATA 0100 x000 motor gain G = 3.2 reset x001 motor gain G = 4.0 − x010 motor gain G = 6.4 − x011 motor gain G = 8.0 − x100 motor gain G = 12.8 − x101 motor gain G = 16.0 − x110 motor gain G = 25.6 − x111 motor gain G = 32.0 − 0xxx disable comparator clock divider 1xxx enable comparator clock divider; only if SELLPLL set HIGH xx00 motor f4 = 0.5 Hz reset xx01 motor f4 = 0.7 Hz − xx10 motor f4 = 1.4 Hz − xx11 motor f4 = 2.8 Hz − 00xx motor f3 = 0.85 Hz reset 01xx motor f3 = 1.71 Hz − 10xx motor f3 = 3.42 Hz − 0101 0110 0111 reset − xx00 motor power maximum 37% reset xx01 motor power maximum 50% − xx10 motor power maximum 75% − xx11 motor power maximum 100% − 00xx MOTO1, MOTO2 pins 3-state reset 01xx motor PWM mode − 10xx motor PDM mode − − 11xx motor CDV mode xx00 interrupt signal from servo at STATUS pin xx10 status bit from decoder status register at STATUS pin x0xx DAC data normal value reset x1xx DAC data inverted value − 0xxx left channel first at DAC (WCLK normal) 1xxx 1998 Jul 06 FUNCTION INITIAL(1) ADDRESS 8 (PLL loop filter bandwidth) 9 (PLL equalization) SAA7377 right channel first at DAC (WCLK inverted) reset − reset − see Table 13 1001 0011 PLL loop filter equalization 0001 PLL 30 ns over-equalization − 0010 PLL 15 ns over-equalization − 0100 PLL 15 ns under-equalization − 0101 PLL 30 ns under-equalization − 35 reset Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) REGISTER A (EBU output) B (speed control) C (versatile pins interface) D (versatile pins interface) E F (subcode interface) INITIAL(1) ADDRESS DATA FUNCTION 1010 x010 level II clock accuracy (<1000 ppm) x011 level I clock accuracy (<50 ppm) − x110 level III clock accuracy (>1000 ppm) − x111 EBU off - output LOW − 0xxx flags in EBU off reset 1xxx flags in EBU on − 00xx 33.8688 MHz crystal present, or 8.4672 MHz crystal with SELPLL set HIGH 01xx 16.9344 MHz crystal present − xx00 standby 1:’CD-STOP’ mode reset xx10 standby 2:’CD-PAUSE’ mode − xx11 operating mode − xxx1 external off-track signal input at V1 xxx0 internal off-track signal used (V1 may be read via STATUS) xx0x kill-L at KILL output, kill-R at V3 output 001x V3 = 0; single KILL output reset 011x V3 = 1; single KILL output − 0000 4-line motor (using V4 and V5) − xx01 Q-to-W subcode at V4 − xx10 V4 = 0 − xx11 V4 = 1 reset 01xx de-emphasis signal at V5, no internal de-emphasis filter − 10xx V5 = 0 − 11xx V5 = 1 reset 1011 1100 1101 1110 1111 reset reset − reset − 0100 motor brakes to 12% reset 0101 motor brakes to 6% − x000 subcode interface off reset x100 subcode interface on − 0xxx 4-wire subcode reset 1xxx 3-wire subcode − Note 1. The initial column shows the power-on reset state. 1998 Jul 06 SAA7377 36 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 Table 13 Loop filter bandwidth FUNCTION REGISTER 8 (PLL loop filter bandwidth) ADDRESS DATA LOOP BANDWIDTH (Hz) INTERNAL BANDWIDTH (Hz) LOW-PASS BANDWIDTH (Hz) INITIAL(1) 1000 0000 1640 525 8400 − 0001 3279 263 16800 − 0010 6560 131 33600 − 0100 1640 1050 8400 − 0101 3279 525 16800 − 0110 6560 263 33600 − 1000 1640 2101 8400 − 1001 3279 1050 16800 reset 1010 6560 525 33600 − 1100 1640 4200 8400 − 1101 3279 2101 16800 − 1110 6560 1050 33600 − Note 1. The initial column shows the power-on reset state. 1998 Jul 06 37 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.14.4 SAA7377 SUMMARY OF SERVO COMMANDS A list of the servo commands are given in Table 14. It should be noted that these are not fully backwards compatible with DSIC2. Table 14 CD7 servo commands COMMANDS CODE BYTES PARAMETERS Write_focus_coefs1 17H 7 <foc_parm3> <foc_int> <ramp_incr> <ramp_height> <ramp_offset> <FE_start> <foc_gain> Write_focus_coefs2 27H 7 <defect_parm> <rad_parm_jump> <vel_parm2> <vel_parm1> <foc_parm1> <foc_parm2> <CA_drop> Write_focus_command 33H 3 <foc_mask> <foc_stat> <shock_level> Focus_gain_up 42H 2 <foc_gain> <foc_parm1> Focus_gain_down 62H 2 <foc_gain> <foc_parm1> Write_radial coefs 57H 7 <rad_length_lead> <rad_int> <rad_parm_play> <rad_pole_noise> <rad_gain> <sledge_parm2> <sledge_parm_1> Preset_Latch 81H 1 <chip_init> Radial_off C1H 1 ‘1CH’ Radial_init C1H 1 ‘3CH’ Short_jump C3H 3 <tracks_hi> <tracks_lo> <rad_stat> Long_jump C5H 5 <brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo> <rad_stat> Steer_sledge B1H 1 <sledge_level> Preset_init 93H 3 <re_offset> <re_gain> <sum_gain> Write_decoder_reg(1) D1H 1 <decoder_reg_data> Write_parameter A2H 2 <param_ram_addr> <param_data> Read_Q_subcode(1)(2) 0H up to 12 <Q_sub1..10> <peak_l> <peak_r> Read_status 70H up to 5 <foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi> <tracks_lo> Read_hilevel_status(3) E0H up to 4 <intreq> <dec_stat> <seq_stat> <motor_start_time> Read_aux_status F0H up to 3 <re_offset> <re_gain> <sum_gain> Write commands Read commands Notes 1. These commands only available when internal decoder interface is enabled. 2. <peak_l> and <peak_r> bytes are clocked out LSB first. 3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled. 1998 Jul 06 38 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) 7.14.5 SAA7377 SUMMARY OF SERVO COMMAND PARAMETERS Table 15 Servo command parameters RAM ADDRESS AFFECTS POR VALUE foc_parm_1 − focus PID − foc_parm_2 − focus PID − PARAMETER DETERMINES end of focus lead defect detector enabling focus low-pass focus error normalising foc_parm_3 − − focus PID focus lead length minimum light level foc_int 14H focus PID − foc_gain 15H focus PID 70H CA_drop 12H focus PID − sensitivity of drop-out detector ramp_offset 16H focus ramp − asymmetry of focus ramp ramp_height 18H focus ramp − peak-to-peak value of ramp voltage focus integrator crossover frequency focus PID loop gain − focus ramp − slope of ramp voltage FE_start 19H focus ramp − minimum value of focus error rad_parm_play 28H radial PID − end of radial lead ramp_incr rad_pole_noise 29H radial PID − radial low-pass rad_length_lead 1CH radial PID − length of radial lead rad_int 1EH radial PID − radial integrator crossover frequency rad_gain 2AH radial PID 70H rad_parm_jump 27H radial jump − filter during jump vel_parm1 1FH radial jump − PI controller crossover frequencies vel_parm2 32H radial jump − jump pre-defined profile speed_threshold 48H radial jump − maximum speed in fastrad mode hold_mult 49H radial jump 00H brake_dist_max 21H radial jump − sledge_long_brake 58H radial jump 7FH − sledge − voltage on sledge during long jump sledge_Umax radial loop gain sledge bandwidth during jump maximum sledge distance allowed in fast actuator steered mode brake distance of sledge − sledge − voltage on sledge when steered sledge_parm_1 36H sledge − sledge integrator crossover frequency sledge_parm_2 17H sledge − sledge low-pass frequencies sledge_level sledge gain sledge operation mode sledge_pulse1 46H pulsed sledge − pulse width sledge_pulse2 64H pulsed sledge − pulse height defect_parm − defect detector − defect detector setting shock_level − shock detector − shock detector operation playwatchtime 54H watchdog − radial on-track watchdog time jumpwatchtime 57H watchdog − radial jump watchdog time-out 1998 Jul 06 39 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) PARAMETER radcontrol chip_init SAA7377 RAM ADDRESS AFFECTS POR VALUE 59H watchdog − enable/disable automatic radial off feature − set-up − VRH level setting DETERMINES enable/disable decoder interface xtra_preset 4AH set-up 38H laser on/off RA, FO and SL PDM modulating frequency microcontroller communication to decoder part cd6cmd 4DH decoder interface − decoder part commands interrupt_mask 53H STATUS pin − enabled interrupts seq_control 42H autosequencer − autosequencer control focus_start_time 5EH autosequencer − focus start time motor_start_time1 5FH autosequencer − motor start 1 time motor_start_time2 60H autosequencer − motor start 2 time radial_init_time 61H autosequencer − radial initialization time brake_time 62H autosequencer − brake time RadCmdByte 63H autosequencer − radial command byte osc_inc 68H focus/radial AGC − AGC control frequency of injected signal phase_shift 67H focus/radial AGC − phase shift of injected signal level1 69H focus/radial AGC − amplitude of signal injected level2 6AH focus/radial AGC − amplitude of signal injected agc_gain 6CH focus/radial AGC − focus/radial gain 1998 Jul 06 40 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V VI(max) maximum Input voltage (any input) −0.5 VDD + 0.5 V VO output voltage (any output) −0.5 +6.5 V note 1 VDDdiff difference between VDDA and VDDD − ± 0.25 V IO output current (continuous) − ± 20 mA IIK DC input diode current (continuous) − ± 20 mA Tamb operating ambient temperature −40 +85 °C Tstg storage temperature Ves electrostatic handling −55 +125 °C note 2 −2000 +2000 V note 3 −200 +200 V Notes 1. All VDD and VSS connections must be made externally to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a rise time of 15 ns. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. 9 OPERATING CHARACTERISTICS VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage IDD supply current VDD = 5 V 3.4 5.0 5.5 V − 49 − mA Decoder analog front-end (VDDA = 5 V; VSSA = 0 V; Tamb = 25 °C) COMPARATOR INPUTS: HFIN AND HFREF fclk clock frequency 8 − 70 MHz Vth(sw) switching voltage threshold 1.2 − VDD − 0.8 V Vtpt HFIN input voltage level − 1.0 − V − 0.5VDD − V note 1 REFERENCE GENERATOR: Iref VIref 1998 Jul 06 reference voltage level (pin 18) 41 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SYMBOL PARAMETER SAA7377 CONDITIONS MIN. TYP. MAX. UNIT Servo analog part (VDDA = 5 V; VSSA = 0 V; Tamb = 25 °C) PINS D1 TO D4, R1, R2, VRH, VRL AND IrefT IrefT input reference current 1.935 − 5.45 µA RIrefT external resistor on pin 10 220 − 620 kΩ VIrefT voltage on reference current input − 1.2 − V ID(max) maximum input current for central diode input signal note 2 3.871 − 10.9 µA IR(max) maximum input current for satellite diode input signal note 2 1.935 − 5.45 µA VRL LOW level reference voltage 0 0 0 V VRH HIGH level reference voltage output state 0; note 3 − 0.5 − V output state v; note 3 −30% 0.5 × 10v/44.4 +30% V output state 31; note 3 − 2.5 − V (THD+N)/S total harmonic distortion plus at 0 dB; note 4 noise − −50 −45 dB S/N signal-to-noise ratio − 55 − dB PSRR power supply ripple rejection note 5 at VDDA2 − 45 − dB Gtol gain tolerance −12 0 +12 % ∆Gv variation of gain between channels − − 2 % αcs channel separation − 60 − dB note 6 Digital inputs INPUTS: RESET, V1, V2, SELPLL (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS) Vthr(sw) switching voltage threshold rising − − 0.8VDDD V Vthf(sw) switching voltage threshold falling 0.2VDDD − − V − 0.33VDDD − V − 50 − kΩ − − 10 pF 1 − − µs −0.3 − 0.3VDD V Vhys hysteresis voltage RI(pu) input pull-up resistance Cin input capacitance tresL reset pulse width (active LOW) Vi = 0 V RESET only INPUTS: SCL, RAB, SILD AND RCK (CMOS INPUT) VIL LOW level input voltage VIH HIGH level input voltage ILI input leakage current Cin input capacitance 1998 Jul 06 Vi = 0 − VDD 42 0.7VDD − VDD + 0.3 V −10 − +10 µA − − 10 pF Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SYMBOL PARAMETER SAA7377 CONDITIONS MIN. TYP. MAX. UNIT Digital outputs OUTPUT: CL4 VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −1 mA VDDD − 0.4 − VDDD V CL load capacitance − − 25 pF tr output rise time CL = 20 pF; 0.8 to (VDDD − 0.8) − − 20 ns tf output fall time CL = 20 pF; (VDDD − 0.8) to 0.8 − − 20 ns 0 − 0.4 V OUTPUT: CL16 VOL LOW level output voltage IOL = 1 mA IOH = −1 mA VOH HIGH level output voltage CL load capacitance tr output rise time tf output fall time VDDD − 0.4 − VDDD V − − 50 pF CL = 20 pF; 0.8 − (VDDD − 0.8) − − 15 ns CL = 20 pF; (VDDD − 0.8) − 0.8 − − 15 ns VDDD = 4.5 to 5.5 V; IOL = 10 mA 0 − 1.0 V VDDD = 3.4 to 5.5 V; IOL = 5 mA 0 − 1.0 V VDDD = 4.5 to 5.5 V; IOH = −10 mA VDDD − 1 − VDDD V VDDD = 3.4 to 5.5 V; IOH = −5 mA VDDD − 1 − VDDD V − − 50 pF OUTPUTS: V4 AND V5 VOL VOH LOW level output voltage HIGH level output voltage CL load capacitance tr output rise time CL = 20 pF; 0.8 − (VDDD − 0.8) − − 10 ns tf output fall time CL = 20 pF; (VDDD − 0.8) − 0.8 − − 10 ns Open-drain outputs OUTPUTS: CFLG, C2FAIL, STATUS, KILL, V3 AND LDON (OPEN-DRAIN OUTPUT WITH PROTECTION DIODE TO VDD) VOL LOW level output voltage IOL LOW level output current CL load capacitance tf output fall time 1998 Jul 06 IOL = 1 mA CL = 20 pF; (VDDD − 0.8) − 0.8 43 0 − 0.4 V − − 2 mA − − 25 pF − − 30 ns Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SYMBOL PARAMETER SAA7377 CONDITIONS MIN. TYP. MAX. UNIT 3-state outputs OUTPUTS: CLK, WCLK, DATA AND CL11 VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −1 mA VDD − 0.4 − VDD V CL load capacitance − − 50 pF tr output rise time CL = 20 pF; 0.8 − (VDD − 0.8) − − 15 ns tf output fall time CL = 20 pF; (VDD − 0.8) − 0.8 − − 15 ns IZO output 3-state leakage current Vi = 0 − VDD −10 − +10 µA 45 50 55 % OUTPUT: CL11 tH output HIGH time (relative to Vo = 1.5 V clock period) OUTPUTS: RA, FO, SL, SBSY, SFSY AND SUB VOL LOW level output voltage IOL = 1 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −1 mA VDD − 0.4 − VDD V CL load capacitance − − 25 pF tr output rise time CL = 20 pF; 0.8 − (VDD − 0.8) − − 20 ns tf output fall time CL = 20 pF; (VDD − 0.8) − 0.8 − − 20 ns IZO 3-state leakage current Vi = 0 − VDD −10 − +10 µA VDD = 4.5 to 5.5 V; IOL = 10 mA 0 − 1.0 V VDD = 3.4 to 5.5 V; IOL = 5 mA 0 − 1.0 V VDD = 4.5 to 5.5 V; IOL = −10 mA VDD − 1 − VDD V VDD = 3.4 to 5.5 V; IOL = −5 mA VDD − 1 − VDD V OUTPUTS: MOTO1, MOTO2 AND DOBM VOL VOH LOW level output voltage HIGH level output voltage CL load capacitance − − 50 pF tr output rise time CL = 20 pF; 0.8 − (VDD − 0.8) − − 10 ns tf output fall time CL = 20 pF; (VDD − 0.8) − 0.8 − − 10 ns IZO 3-state leakage current Vi = 0 − VDD −10 − +10 µA 1998 Jul 06 44 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SYMBOL PARAMETER SAA7377 CONDITIONS MIN. TYP. MAX. UNIT Digital input/output INPUT/OUTPUT: SDA [CMOS INPUT/OPEN-DRAIN I2C-BUS OUTPUT (WITH PROTECTION DIODE TO VDDD)] VIL LOW level input voltage −0.3 − 0.3VDDD V VIH HIGH level input voltage 0.7VDDD − VDDD + 0.3 V −10 − +10 µA − − 10 pF 0 − 0.4 V IZO 3-state leakage current Cin input capacitance VOL LOW level output voltage Vi = 0 − VDDD IOL = 2 mA IOL LOW level output current − − 4 mA CL load capacitance − − 50 pF tf output fall time − − 15 ns CL = 20 pF; (VDDD − 0.8) − 0.8 Crystal oscillator INPUT: CRIN (EXTERNAL CLOCK) VIL LOW level input voltage −0.3 − 0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V ILI input leakage current −10 − +10 µA Cin input capacitance − − 10 pF 8 8.4672 35 MHz − 10 − mA/V − 18 − V/V OUTPUT: CROUT; see Figs 3 and 4 fxtal crystal frequency note 7 gm mutual conductance at 100 kHz Gv small signal voltage gain Cfb feedback capacitance − − 5 pF Cout output capacitance − − 10 pF Gv = gm × RO Notes 1. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode. 2. VRL = 0 V, fsys = 4.2336 MHz. The maximum input current depends on the value of the external resistor connected to IrefT: a) For D1 to D4: Imax = 2.4/RIrefT ⇒ 2.4/220 kΩ = 10.9 µA b) For R1 and R2: Imax = 1.2/RIrefT ⇒ 1.2/20 kΩ = 5.45 µA 3. Internal reference source with 32 different output voltages. Selection is achieved during a calibration period or via the serial interface. The values given are for an unloaded VRH. 4. VRH = 2.5 V and VRL = 0 V, measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz. 5. fripple = 1 kHz, Vripple = 0.5 V (p-p). 6. Gain of the ADC is defined as GADC = fsys/Imax (counts/µA); thus digital output = Ii × GADC where; a) Digital output = the number of pulses at the digital output in counts/s and Ii = the DC input current in µA. b) The maximum input current depends on the system frequency (fsys = 4.2336 MHz) and on VRH − VRL. c) The gain tolerance is the deviation from the calculated gain regarding note 2. 7. It is recommended that the series resistance of the crystal or ceramic resonator is ≤60 Ω. 1998 Jul 06 45 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Subcode interface timing; see Fig.31 INPUT: RCK 6 µs 4 6 µs − 80 ns − 80 ns 10 − 20 µs ms tH input clock HIGH time 2 tL input clock LOW time 2 tr input clock rise time − tf input clock fall time − tdC delay time SFSY to RCK 4 OUTPUTS: SBSY, SFSY AND SUB (CL = 20 pF) tBcy block cycle 12.0 13.3 14.7 tBW SBSY pulse width − − 300 µs tFcy frame cycle 122 136 150 µs tFW SFSY pulse width (3-wire mode only) − − 366 µs tFH SFSY HIGH time − − 66 µs tFL SFSY LOW time − − 84 µs tdPAC delay time SFSY to SUB (P data) valid − − 1 µs tdAC delay time RCK falling to SUB − − 0 µs thD hold time RCK to SUB − − 0.7 µs 1998 Jul 06 46 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 tW(SBSY) handbook, full pagewidth Tcy(block) SBSY tSFSYH SFSY (4-wire mode) tW(SFSY) tcy(frame) SFSY (3-wire mode) tSFSYL SFSY 0.8 V td(SFSY−RCK) tf tr VDD – 0.8 V RCK 0.8 V td(SFSY−SUB) th(RCK−SUB) td(RCK−SUB) VDD – 0.8 V SUB 0.8 V MBG414 Fig.31 Subcode interface timing diagram. 1998 Jul 06 47 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 11 OPERATING CHARACTERISTICS (I2S-BUS TIMING) VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I2S-bus timing; see Fig.32 CLOCK OUTPUT: SCLK (CL = 20 pF) Tcy tCH tCL output clock period clock HIGH time clock LOW time sample rate = fs − 472.4 − ns sample rate = 2fs − 236.2 − ns sample rate = 4fs − 118.1 − ns sample rate = fs 166 − − ns sample rate = 2fs 83 − − ns sample rate = 4fs 42 − − ns sample rate = fs 166 − − ns sample rate = 2fs 83 − − ns sample rate = 4fs 42 − − ns sample rate = fs 95 − − ns sample rate = 2fs 48 − − ns sample rate = 4fs 24 − − ns sample rate = fs 95 − − ns sample rate = 2fs 48 − − ns sample rate = 4fs 24 − − ns OUTPUTS: WCLK AND DATA (CL = 20 pF) tsu th set-up time hold time clock period Tcy t CH t CL V DD – 0.8 V SCLK 0.8 V t su th V DD – 0.8 V WCLK DATA 0.8 V MGD026 Fig.32 I2S-bus timing diagram. 1998 Jul 06 48 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Microcontroller interface timing (4-wire bus mode; writing to registers 0 to F; reading Q-channel subcode and decoder status); see Figs 33 and 34 INPUTS SCL AND RAB tCL input LOW time 500 − − ns tCH input HIGH time 500 − − ns tr rise time − − 480 ns tf fall time − − 480 ns READ MODE (CL = 20 pF) tdRD delay time RAB to SDA valid − − 50 ns tPD propagation delay SCL to SDA 700 − 980 ns tdRZ delay time RAB to SDA high-impedance − − 50 ns 700 − − ns WRITE MODE ((CL = 20 pF) tsuD set-up time SDA to SCL thD hold time SCL to SDA − − 980 ns tsuCR set-up time SCL to RAB 260 − − ns tdWZ delay time SDA high-impedance to RAB 0 − − ns note 1 Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 35 and 36 INPUTS SCL AND SILD tL input LOW time 710 − − ns tH input HIGH time 710 − − ns tr rise time − − 240 ns tf fall time − − 240 ns READ MODE (CL = 20 pF) tdLD delay time SILD to SDA valid − − 25 ns tPD propagation delay SCL to SDA − − 950 ns tdLZ delay time SILD to SDA high-impedance − − 50 ns tsCLR set-up time SCL to SILD 480 − − ns thCLR hold time SCL to SILD 830 − − ns WRITE MODE (CL = 20 pF) tsD set-up time SDA to SCL 0 − − ns thD hold time SCL to SDA 950 − − ns tsCL set-up time SCL to SILD 480 − − ns thCL hold time SILD to SCL 120 − − ns tdPLP delay between two SILD pulses 70 − − µs tdWZ delay time SDA high-impedance to SILD 0 − − ns Notes 1. Negative set-up time means that the data may change after clock transition. 1998 Jul 06 49 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 tr tf V DD – 0.8 V RAB tr tf V tdRD SCL 0.8 V tCH DD − 0.8 V 0.8 V tdRZ tCL tPD V DD − 0.8 V SDA (SAA7377) high-impedance 0.8 V MGR303 Fig.33 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information). tr handbook, full pagewidth t CH tf V DD – 0.8 V t suCR RAB 0.8 V t tf t CL tr CH VDD – 0.8 V SCL 0.8 V t CL t t suD V SDA (microcontroller) DD t dWZ hD – 0.8 V high-impedance 0.8 V MBG405 Fig.34 4-wire bus microcontroller timing; write mode (registers 0 to F). 1998 Jul 06 50 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 VDD – 0.8 V handbook, full pagewidth SILD 0.8 V thCLR tsCLR VDD − 0.8 V SCL 0.8 V tPD tdLD tdLZ VDD − 0.8 V SDA (SAA7377) 0.8 V MGR304 Fig.35 4-wire bus microcontroller timing; read mode (servo commands). handbook, full pagewidth VDD - 0.8 V SILD 0.8 V tsCL tL tH tdPLP VDD – 0.8 V SCL 0.8 V thCL tL tsD tdWZ thD VDD – 0.8 V SDA (microcontroller) 0.8 V MBG416 Fig.36 4-wire bus microcontroller timing (servo commands) write mode. 1998 Jul 06 51 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 11 12 13 100 nF 22 kΩ 14 15 RFE VDDA 9 16 CL4 VSSD3 SCL SDA RAB n.c. SILD VSSD4 RESET V1 VSSD2 VRH SUB VSSA2 RCK SELPLL SFSY ISLICE SBSY HFIN VSSA3 2.2 nF 2.2 kΩ 47 pF CFLG IrefT 100 nF MOTO2 VSSD1 270 kΩ V5 DOBM (3) R2 VDDD1(P) TDA1300 V4 SAA7377 48 MOTO1 2.2 Ω VDDD 100 nF 46 to DAC 45 44 43 42 41 40 39 38 37 36 to CD graphics MOTOR INTERFACE 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (1) 22 nF (2) to power amplifiers VDD to DOBM transformer 2.2 Ω Fig.37 Typical SAA7377 application diagram. MGR305 Product specifications 100 nF SAA7377 (1) The diagram is for 5 V application. For 3.4 V application an additional resistor of 150 kΩ should be connected between pin 18 and ground. (2) For crystal oscillator circuit see Figs 3 and 4. (3) The connections to TDA1300 are shown for single Foucault mechanisms. handbook, full pagewidth 52 10 R1 TEST3 9 V3 SL 220 pF D4 FO 8 KILL RA 220 pF TEST4 VRL CL11 100 kΩ 7 D3 CL16 220 pF DATA TEST2 4 6 D2 CROUT 5 WCLK CRIN 220 pF D1 TEST1 100 kΩ 4 SCLK VDDD2(P) 47 VDDA2 220 pF STATUS VDDA1 C2FAIL 2 VDDD3C VSSA1 3 220 pF D5 5 2 D6 1 V2 LDON 6 3 D3 1 D4 D1 100 nF 33 µF HFREF Iref D2 100 nF Philips Semiconductors 2.2 Ω VDDA 4.7 kΩ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 +V 7 +V 4.7 kΩ 100 nF 33 µF LDON microcontroller interface +V VDDD Digital servo processor and Compact Disc decoder (CD7) 2.2 Ω 13 APPLICATION INFORMATION 1998 Jul 06 +V Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 14 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 θ wM Lp bp pin 1 index L 17 64 detail X 16 1 w M bp e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 3.00 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 14.1 13.9 0.8 HD HE L 17.45 17.45 1.60 16.95 16.95 Lp v w y 1.03 0.73 0.16 0.16 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 1998 Jul 06 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-05-21 97-08-04 MS-022 53 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: 15 SOLDERING 15.1 Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 15.2 Reflow soldering Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Jul 06 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 15.3 SAA7377 54 Philips Semiconductors Product specifications Digital servo processor and Compact Disc decoder (CD7) SAA7377 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Short-form specification The data in this specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Jul 06 55 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545102/00/01/pp56 Date of release: 1998 Jul 06 Document order number: 9397 750 04003