PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN CONFIGURATION (Top View) 16 SEL0^ XIN 2 15 SEL1^ XOUT 3 14 GND SEL3^ 4 13 CLKC SEL2^ 5 12 VDD OE 6 11 CLKT VCON 7 10 GND GND 8 9 GND BLOCK DIAGRAM 14 SEL2^ 15 OE 16 SEL1^ 10 9 P520-0x 1 2 3 4 GND XOUT 11 8 GND 7 CLKC 6 VDD 5 CLKT OUTPUT ENABLE LOGICAL LEVELS OE VCON Oscillator XOUT 12 13 ^: Internal pull-up *: PLL520-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) SEL XIN XIN GND The PLL520-05/-06/-07/-08/-09 is a family of VCXO ICs specifically designed to pull high frequency fundamental crystals. Their design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. SEL0^ DESCRIPTION GND • • • 1 GND/DRIVSEL* • VDD PLL 520-0x • 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 800MHz (4x multiplier), or 800MHz – 1GHz (PLL520-09 TSSOP only, 8x multiplier). High yield design supports up to 2pF stray capacitance at 200MHz. CMOS (Standard drive PLL520-07 or Selectable Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09). Integrated variable capacitors. Supports 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL520-06 only available in 3x3mm. Note: PLL520-07 only available in TSSOP. VCON • • VDD FEATURES Amplifier w/ integrated varicaps PLL (Phase Locked Loop) PLL by-pass Q Q Part # PLL520-08 PLL520-05 PLL520-06 PLL520-07 PLL520-09 OE State 0 (Default) 1 0 Output enabled Tri-state Tri-state 1 (Default) Output enabled OE input: Logical states defined by PECL levels for PLL520-08 Logical states defined by CMOS levels for PLL520-05/-06/07/-09 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1 PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN DESCRIPTIONS Name TSSOP* Pin number 3x3mm QFN* Pin number Type Description XIN XOUT OE VCON GND 2 3 6 7 8,9, 10, 14 13 14 16 1 2,3,4,8,12 I I I I P DRIVSEL** - 12 I CLKT 11 5 O CLKC 13 7 O Crystal in connector. Crystal out connector. Output enable pin. Frequency control input (0.3V to 3.0V) Ground (except pin 12 on PLL520-06: DRIVSEL see below). PLL520-06 only: Drive Select Input. This pin has an internal pull-up that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL520-06 will be high drive CMOS when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise. True output PECL (PLL520-08) or LVDS (PLL520-09) (N/C for PLL520-07) Complementary output PECL (PLL520-08) or LVDS (PLL520-09) (CMOS out for PLL520-07). SEL0 SEL1 SEL2 SEL3 VDD 16 15 5 4 1, 12 10 9 15 Not available 6,11 I I I I P Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. +3.3V power supply. * Note: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL520-06 only. FREQUENCY SELECTION TABLE SEL3* SEL2 SEL1 SEL0 Selected Multiplier 0* 0 1 1 Fin x 8 (PLL520-09 in TSSOP only) 1* 0 1 1 Fin x 4 1* 1 1 0 Fin x 2 1* 1 1 1 No multiplication Note *: SEL3 is not available (always “1”) in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2 PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR SYMBOL CONDITIONS MIN. MAX. UNITS F XIN C L (xtal) C0 C 0 /C 1 (xtal) RE Parallel Fundamental Mode Die at VCON = 1.65V 100 200 MHz pF pF - 4 3.5 250 30 AT cut AT cut Ω 3. Voltage Controlled Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW SYMBOL T VCXOSTB CONDITIONS From power valid F XIN = 100 – 200MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V VCON = 0 to 3.3V MIN. TYP. MAX. UNITS 10 ms 200* ppm ±100* 4 – 18* 10* 65 60 0V ≤ VCON ≤ 3.3V, -3dB 25 ppm pF % ppm/V kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3 PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current (Loaded Outputs) Operating Voltage I DD CONDITIONS MIN. PECL/LVDS/CMOS V DD 2.97 45 45 45 @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Output Clock Duty Cycle TYP. Short Circuit Current 50 50 50 ±50 MAX. UNITS 100/80/40 mA 3.63 55 55 55 V % mA 5. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter Integrated jitter RMS at 155MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter Integrated jitter RMS at 622MHz MAX. 2.5 18.5 20 2.5 24 27 2.5 0.3 0.4 11 45 49 11 24 27 3 1.6 1.8 UNITS ps ps ps ps ps ps ps ps Measured on Wavecrest SIA 3000 6. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 155.52MHz 622.08MHz -75 -75 -95 -95 -125 -110 -140 -125 -145 -120 dBc/Hz Phase Noise relative to carrier Note: Phase Noise measured at VCON = 0V 7. CMOS Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V MIN. TYP. 30 30 10 10 MAX. UNITS mA mA mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns * Note: High Drive CMOS is available on PLL520-06 through DRIVSEL selector input on pin 12. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4 PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) 8. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change ∆V OD V OH V OL V OS Power-off Leakage I OXD Output Short Circuit Current I OSD CONDITIONS V OD R L = 100 Ω (see figure) MIN. TYP. MAX. UNITS 247 -50 355 454 50 1.6 0.9 1.125 0 ∆V OS V out = V DD or GND V DD = 0V 1.4 1.1 1.2 3 1.375 25 mV mV V V V mV ±1 ±10 uA -5.7 -8 mA 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5 PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) 10. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL CONDITIONS MIN. V OH V OL R L = 50 to (V DD – 2V) (see figure) V DD – 1.025 MAX. UNITS V DD – 1.620 V V 11. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS MIN. @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT MAX. UNITS 0.6 0.5 1.5 1.5 ns ns PECL Output Skew OUT VDD 50Ω TYP. 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6 PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PACKAGE INFORMATION 16 PIN TSSOP ( m m ) Sym bol A A1 B C D E H L e M in. M ax. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e B L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7 PLL520-05/-06/-07/-08/-09 Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-0x O C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE O=TSSOP Q=QFN Order Number Marking Package Option PLL520-05OC PLL520-05OC-R PLL520-05QC PLL520-05QC-R P520-05OC P520-05OC P520-05QC P520-05QC 16-Pin 16-Pin 16-Pin 16-Pin PLL520-06QC PLL520-06QC-R P520-06QC P520-06QC 16-Pin 3x3 QFN (Tube) 16-Pin 3x3 QFN (Tape and Reel) PLL520-07OC PLL520-07OC-R P520-07OC P520-07OC 16-Pin TSSOP (Tube) 16-Pin TSSOP (Tape and Reel) PLL520-08OC PLL520-08OC-R PLL520-08QC PLL520-08QC-R P520-08OC P520-08OC P520-08QC P520-08QC 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PLL520-09OC PLL520-09OC-R PLL520-09QC PLL520-09QC-R P520-09OC P520-09OC P520-09QC P520-09QC 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 8