PLL520-20 Preliminary Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) FEATURES DIE CONFIGURATION 62 mil XIN VDD VDD VDD N/C DNC DNC 23 22 21 20 19 18 17 XOUT 27 DNC 28 DNC 29 OE CTRL 30 VCON 31 Die ID: A1919-19B C502A 4 5 6 GND Reserved X 7 8 GNDBUF 3 GNDBUF 2 GND (0,0) 16 N/C 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS 9 1 GND Y GNDBUF Value OE Size Reverse side 62 x 65 mil GND Q Pad dimensions 80 micron x 80 micron Q Thickness 10 mil Amplifier w/ integrated varicaps PLL520-20 OUTSEL^ DIE SPECIFICATIONS Name VCON Oscillator X- 24 26 BLOCK DIAGRAM X+ 25 GND PLL520-20 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. (1550,1475) GND DESCRIPTIONS VDD 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100MHz – 200MHz (no PLL). Low Injection Power for crystal 50uW. Complementary outputs: CMOS, PECL or LVDS. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in die form. Die thickness is 10 mil. N/C 65 mil • • • • • • • • • OUTPUT SELECTION AND ENABLE Pad #18 OUTSEL1 Pad #25 OUTSEL0 0 0 1 1 0 1 0 OE_SELECT (Pad #9) OE_CTRL (Pad #30) 0 1 (Default) 1 0 1 (Default) 0 (Default) 1 Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1” No connection results to “default” setting through internal pull-up/-down. Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by CMOS levels if OE_SELECT is “0” 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1 Preliminary PLL520-20 Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI V SS -0.5 V DD +0.5 V Output Voltage, dc VO V SS -0.5 V DD +0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature TA 0 70 °C Junction Temperature TJ 125 °C 260 °C 2 kV Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR SYMBOL F XIN C L (xtal) CONDITIONS Parallel Fundamental Mode MIN. TYP. 120 Die at VCON = 1.65V MAX. UNITS 200 MHz 4 C0 pF 3.5 pF C 0 /C 1 (xtal) AT cut 250 - RE AT cut 30 Ω 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range SYMBOL T VCXOSTB CONDITIONS MIN. From power valid XTAL C 0 /C 1 < 250 TYP. MAX. 10 ms 180* 0V ≤ VCON ≤ 3.3V at room temperature VCON = 0 to 3.3V UNITS ppm ±100* ppm 4 – 18* pF Linearity 4* VCXO Tuning Characteristic 65 ppm/V VCON input impedance 60 kΩ VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB 5* 25 % kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2 Preliminary PLL520-20 Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS Supply Current (Loaded Outputs) I DD PECL/LVDS Operating Voltage V DD MIN. 3.13 @ 1.25V (LVDS) @ Vdd – 1.3V (PECL) Output Clock Duty Cycle TYP. 45 45 50 50 MAX. UNITS 100/80/40 mA 3.47 V 55 55 % ±50 Short Circuit Current mA 5. Jitter specifications PARAMETERS Period jitter RMS at 155MHz Period jitter peak-to-peak at 155MHz CONDITIONS MIN. TYP. 2.5 At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles 18.5 2.5 Accumulated jitter peak-to-peak at 155MHz At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. Random Jitter “RJ” measured on Wavecrest SIA 3000 2.5 Integrated jitter RMS at 155MHz Integrated 12 kHz to 20 MHz 0.3 Accumulated jitter RMS at 155MHz MAX. 24 20 27 UNITS ps ps ps 0.4 ps Measured on Wavecrest SIA 3000 6. Phase noise specifications PARAMETERS Phase Noise relative to carrier FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 155.52MHz -75 -95 -125 -140 -145 dBc/Hz Note: Phase Noise measured at VCON = 0V 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 3 Preliminary PLL520-20 Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆V OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 4 Preliminary PLL520-20 Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 10. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns PECL Levels Test Circuit OUT PECL Output Skew OUT VDD 50Ω 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 5 Preliminary PLL520-20 Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) PAD ASSIGNMENT Pad # Name X (µm) Y (µm) 1 GND 248 109 2 GND 361 109 3 GND 473 109 4 GND 587 109 5 GND 702 109 6 N/C 874 109 7 GND 1042 109 8 GNDBUF 1171 109 9 OE_SELECT 1400 125 10 LVDS 1400 259 11 PECL 1400 476 12 VDDBUF 1400 616 13 VDDBUF 1400 716 14 PECLB 1400 871 15 LVDSB 1400 1089 16 CMOS 1400 1227 17 GNDBUF 1389 1365 18 OUTSEL1 1232 1365 19 DNC (Do Not Connect) 1042 1365 20 DNC (Do Not Connect) 854 1365 21 VDD 659 1365 22 VDD 559 1365 23 VDD 459 1365 24 VDD 358 1365 25 OUTSEL0 194 1365 26 XIN 109 1223 27 XOUT 109 1017 28 DNC (Do Not Connect) 109 858 29 DNC (Do Not Connect) 109 646 30 OE_CTRL 109 397 31 VCON 109 181 Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 6 Preliminary PLL520-20 Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals) ORDERING INFORMATION PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL520-20 DC PART NUMBER TEMPERATURE C=COMMERCIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PLL520-20DC PLL520-20DC Die – Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 7