PACE1750A SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip PACE TechnologyTM CMOS 16-Bit Processor with 32 and 48-Bit Floating Point Arithmetic DAIS Instruction Mix Execution Performance Including Floating Point Arithmetic 1.3 MIPS at 20 MHz 1.9 MIPS at 30 MHz 2.6 MIPS at 40 MHz Integer DAIS Mix Performance 3.9 MIPS at 40 MHz Conventional Integer Processing Mix Performance 5.0 MIPS at 40 MHz Instruction Execution at 40 MHz over the Military Temperature Range 0.10 µsec Integer Add/Sub 0.57 µsec Integer Multiply 0.70 µsec Floating Point Add/Sub 1.07 µsec Floating Point Multiply 15, 20, 30, and 40 MHz Operation over the Military Temperature Range Extensive Error and Fault Management and Interrupt Capability 24 User Accessible Registers Single 5V ± 10% Power Supply Power Dissipation over Military Temperature Range < 0.30 watts at 20 MHz < 0.35 watts at 30 MHz < 0.40 watts at 40 MHz TTL Signal Level Compatible Inputs and Outputs Multiprocessor and Co-processor Capability Built-In Function (BIF) for User Defined Instructions Two programmable Timers Available in: – 64-Pin DIP or Gull Wing (50 Mil Pin Centers) – 68-Pin Pin Grid Array (PGA) – 68-Lead Quad Pack (Leaded Chip Carrier) GENERAL DESCRIPTION The PACE1750A is a general purpose, single chip, 16-bit CMOS microprocessor designed for high performance floating point and integer arithmetic, with extensive real time environment support. It offers a variety of data types, including bits, bytes, 16-bit and 32-bit integers, and 32-bit and 48-bit floating point numbers. It provides 13 addressing modes, including direct, indirect, indexed, based, based indexed and immediate long and short, and it can access 2 MWords of segmented memory space (64 KWords segments). levels of prioritized internal and external interrupts, and a faults and exceptions handler controlling internally and externally generated faults. The PACE1750A offers a well-rounded instruction set with 130 instruction types, including a comprehensive integer, floating point, integer-to-floating point and floating point-to-integer set, a variety of stack manipulation instructions, high level language support instructions such as Compare Between Bounds and Loop Control Instructions. It also offers some unique instructions such as vectored l/O, supports executive and user modes, and provides an escape mechanism which allows user-defined instructions using a coprocessor. The PACE1750A uses a single multiplexed 16-bit parallel bus. Status signals are provided to determine whether the processor is in the memory or I/O bus cycle, reading and writing, and whether the bus cycle is for data or instructions. The chip includes 16 general purpose registers, 8 other user-accessible registers, and an array of real time application support resources, such as 2 programmable timers, a complete interrupt controller supporting 16 The microprocessor achieves very high throughput of 2.6 MIPS for a standard real time integer/floating point instruction mix at a 40 MHz clock. It executes integer Add in 0.1 µs, integer Multiply in 0.575 µs, Floating Point Add in 0.7 µs, and Floating Point Multiply in 1.075 µs, for register operands at a 40 MHz clock speed. The basic bus cycle is 4 clocks long. The PACE1750A will extend the cycle by insertion of wait states in the address and data phases (in response to RDYA and RDYD signals, repectively) and will hold the machine in HI-Z if this CPU has not acquired the bus. A typical non-bus cycle is three clocks long. However, variable length cycles are used for such repetitive operations as multiply, divide, scale and normalize, reducing significantly the number of CPU CLOCKS per operation step and resulting in very fast integer and floating point execution times. Document # MICRO-3 Rev. C Revised October 2005 PACE1750A ABSOLUTE MAXIMUM RATINGS1 Supply Voltage Range -0.5V to 7.0V ΘJC), Note 5: Thermal resistance, junction-to-case (Θ Input Voltage Range -0.5V to VCC + 0.5V Cases X and T 8°C/W Cases Y and U 5°C/W Case Z 6°C/W Storage Temperature Range -65°C to + 150°C Input Current Range -30mA to +5mA Voltage Applied to Inputs -0.5V to VCC + 0.5V Current Applied to Outputs3 150 mA RECOMMENDED OPERATING CONDITIONS Maximum Power Dissipation2 1.5W Operating worst case power dissipation (outputs open): Device type 01 0.25W at 15 MHz Device type 02 0.30W at 20 MHz Device type 03 0.35W at 30 MHz Device type 04 0.40W at 40 MHz Lead Temperature Range (soldering 10 seconds) 300°C Supply Voltage Range 4.5V to 5.5V Case Operating Temperature -55°C to +125°C Range NOTE 1: Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. NOTE 2: Must withstand the added power dissipation due to short circuit test e.g., IOS NOTE 3: Duration one second or less. NOTE 4: Device Type Definitions from 5962-87665 SMD: Device Type 01: 15 MHz Device Type 02: 20 MHz Device Type 03: 30 MHz Device Type 04: 40 MHz NOTE 5: Case Definitions from 5962-87665 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array Document # MICRO-3 Rev. C Page 2 of 24 PACE1750A DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit Conditions1 VIH Input HIGH Level Voltage 2.0 VCC + 0.5 V VIL Input LOW Level Voltage2 –0.5 0.8 V VCD Input Clamp Diode Voltage –1.2 V VCC = 4.5V, IIN = –18mA VOH Output HIGH Level Voltage 2.4 V VCC = 4.5V IOH = –8.0mA VCC – 0.2 V VCC = 4.5V IOH = –300µA 0.5 V VCC = 4.5V IOL = 8.0mA 0.2 V VCC = 4.5V IOL = 300µA 10 µA VIN = VCC, VCC = 5.5V VOL Output LOW Level Voltage Input HIGH Level Current, IIH1 except IB0 – IB15, BUS BUSY, BUS LOCK IIH2 Input HIGH Level Current, IB0 – IB15, BUS BUSY, BUS LOCK 50 µA VIN = VCC, VCC = 5.5V IIL1 Input LOW Level Current, except IB0 – IB15, BUS BUSY, BUS LOCK –10 µA VIN = GND, VCC = 5.5V IIL2 Input LOW Level Current, IB0 – IB15, BUS BUSY, BUS LOCK –50 µA VIN = GND, VCC = 5.5V IOZH Output Three-State Current 50 µA VOUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA VOUT = 0.5V, VCC = 5.5V ICCQC Quiescent Power Supply Current (CMOS Input Levels) mA VIN < 0.2V or < VCC – 0.2V, f = 0MHz, Outputs Open, VCC = 5.5V 10 Quiescent Power Supply ICCQT Current (TTL Input Levels) ICCD Dynamic Power Supply Current VIN < 3.4V, f = 0MHz, 50 mA Outputs Open, VCC = 5.5V 15 MHz 40 mA VIN = 0V to VCC, tr = tf = 2.5 ns, 20 MHz 50 mA Outputs Open, 30 MHz 60 mA VCC = 5.5V 40 MHz 70 mA IOS Output Short Circuit Current3 CIN Input Capacitance 10 pF COUT Output Capacitance 15 pF CI/O Bi-directional Capacitance 15 pF –25 mA VOUT = GND, VCC = 5.5V Notes 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. Document # MICRO-3 Rev. C Page 3 of 24 PACE1750A SIGNAL PROPAGATION DELAYS 1,2 15 MHz Symbol Parameter Min 20 MHz Max Min 30 MHz Max Min 40 MHz Max Min Max Unit tC(BR)L BUS REQ 45 33 25 22 ns tC(BR)H BUS REQ 45 33 25 22 ns tBGV(C) BUS GNT setup 5 5 5 5 ns tC(BG)X BUS GNT hold 5 5 5 5 ns tC(BB)L BUS BUSY LOW 35 25 24 20 ns tC(BB)H BUS BUSY HIGH 35 25 20 15 ns tBBV(C) BUS BUSY setup 5 5 5 5 ns tC(BB)X BUS BUSY hold 5 5 5 5 ns tC(BL)L BUS LOCK LOW 50 30 25 21 ns tC(BL)H BUS LOCK HIGH 50 30 25 17 ns tBLV(C) BUS LOCK setup tC(BL)X (IN) BUS LOCK hold 5 5 5 5 ns 5 5 5 5 ns tC(ST)V M/ IO, R/ W Status 45 30 25 20 ns tC(ST)V AS0-AS3, AK 0-AK 3, D/I Status 40 25 20 20 ns tC(ST)X AS0-AS3, AK 0-AK 3, D/I Status, M/ IO, R/ W 0 0 0 0 ns tC(SA)H STRBA HIGH 25 22 17 16 ns tC(SA)L STRBA LOW 25 22 17 16 ns Address hold from STRBA LOW 5 5 5 5 ns tRAV(C) RDYA setup 5 5 5 5 ns tC(RA)X RDYA hold 5 5 5 5 ns tSAL(IBA)X tC(SDW)L tC(SD)H STRBD LOW write 25 22 17 14 ns STRBD HIGH 25 22 17 14 ns 25 22 17 14 ns tFC(SDR)L STRBD LOW read tSDRH(IBD)X STRBD HIGH 0 0 0 0 ns tSDWH(IBD)X STRBD HIGH 45 30 25 17 ns tSDL(SD)H STRBD write 50 40 35 20 ns tRDV(C) RDYD setup 5 5 5 5 ns tC(RD)X RDYD hold 5 5 5 5 ns tC(IBA)V IB 0-IB 15 tFC(IBA)X IB 0-IB 15 tIBDRV(C) IB0-IB15 setup 45 30 25 20 ns 0 0 0 0 ns 5 5 5 5 ns tC(IBD)X IB 0-IB 15 hold (read) 8 7 6 5 ns tC(IBD)X Data valid out (write) 0 0 0 0 ns Document # MICRO-3 Rev. C Page 4 of 24 PACE1750A SIGNAL PROPAGATION DELAYS 1,2 (continued) 15 Mhz Symbol Parameter Min 20 MHz Max Min 30 MHz Max Min 40 MHz Max Min Max Unit tFC(IBD)V IB0-IB15 45 30 25 20 ns tC(SNW) SNEW 45 30 26 22 ns tFC(TGO) TRIGO RST 45 30 26 22 ns tRSTL(DMA ENL) DMA enable 45 40 35 30 ns tC(DME) DMA enable 45 40 35 30 ns tFC(NPU) Normal power up 45 40 35 30 ns Clock to major error unrecoverable 75 60 50 45 ns RESET 65 50 40 30 ns tC(ER) tRSTL(NPU) tREQV(C) Console request 0 0 0 0 ns tC(REQ)X Console request 10 10 10 10 ns tFV(BB)H Level sensitive faults 5 5 5 5 ns tBBH(F)X Level sensitive faults 5 5 5 5 ns tIRV(C) IOL1-2INT user interrupt (0-5) 0 0 0 0 ns tC(IR)X Power down interrupt level sensitive hold 10 10 10 10 ns 30 25 20 15 ns tRSTL (tRSTH) Reset pulse width tC(XX)Z tf(F), t1(1) tr, tf Clock to three-state Edge sensitiive pulse width Clock rise and fall 30 5 22 5 5 17 5 5 13 5 5 ns ns 5 ns Notes 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced. When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle. Document # MICRO-3 Rev. C Page 5 of 24 PACE1750A MINIMUM WRITE BUS CYCLE TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-3 Rev. C Page 6 of 24 PACE1750A MINIMUM READ BUS CYCLE TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-3 Rev. C Page 7 of 24 PACE1750A MINIMUM WRITE BUS CYCLE, FOLLOWED BY A NON-BUS CYCLE, TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-3 Rev. C Page 8 of 24 PACE1750A TRIGO RST DISCRETE TIMING DIAGRAM DMA EN DISCRETE TIMING DIAGRAM NORMAL POWER UP DISCRETE TIMING DIAGRAM XIO OPERATIONS SNEW DISCRETE TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-3 Rev. C Page 9 of 24 PACE1750A EXTERNAL FAULTS AND INTERRUPTS TIMING DIAGRAM Edge-sensitive interrupts and faults (SYSFLT0, SYSFLT1) min. pulse width Level-sensitive interrupts Note: tC(IR)X max = 35 clocks Level-sensitive faults CON REQ Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-3 Rev. C Page 10 of 24 PACE1750A BUS ACQUISITION Note: A CPU contending for the BUS will assert the BUS REQ line, and will acquire it when BUS GNT is assserted and the BUS is not locked (BUS LOCK is high). SWITCHING TIME TEST CIRCUITS Standard Output (Non-Three-State) Three-State Note: All time measurements on active signals relate to the 1.5 volt level. Parameter V0 VMEA tPLZ ≥ 3V 0.5V tPHZ 0V VCC – 0.5V tPXL VCC/2 1.5V tPXH VCC/2 1.5V Document # MICRO-3 Rev. C Page 11 of 24 PACE1750A SIGNAL DESCRIPTIONS CLOCKS AND EXTERNAL REQUESTS Mnemonic Name Description CPU CLK CPU clock A single phase input clock signal (0-40 MHz, 40 percent to 60 percent duty cycle. TIMER CLK Timer clock A 100 KHz input that, after synchronization with CPU CLK, provides the clock for timer A and timer B. If timers are used, the CPU CLK signal frequency must be > 300 KHz. RESET Reset An active LOW input that initializes the device. CON REQ Console request An active LOW input that initiates console operations after completion of the current instruction. INTERRUPT INPUTS Mnemonic Name Description PWRDN INT Power down interrupt An interrupt request input that cannot be masked or disabled. This signal is active on the positive going edge or the high level, according to the interrupt mode bit in the configuration register. USR0INT USR5INT User interrupt Interrupt request input signals that are active on the positive going edge or the high level, according to the interrupt mode bit in the configuration register. IOL1INT IOL2INT I/O level interrupts Active HIGH interrupt request inputs that can be used to expand the number of user interrupts. Mnemonic Name Description MEM PRT ER Memory protect error An active LOW input generated by the MMU or BPU, or both and sampled by the BUS BUSY signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus cycle). MEM PAR ER Memory parity error An active LOW input sampled by the BUS BUSY signal into bit 2 of the fault register. EXT ADR ER External address error An active LOW input sampled by the BUS BUSY signal into the Fault register (bit 5 or 8), depending on the cycle (memory or I/O). SYSFLT0 SYSFLT1 System fault 0, System fault 1, Asynchronous, positive edge-sensitive inputs that set bit 7 (SYSFLT0) or bits 13 and 15 (SYSFLT1) in the Fault register. Mnemonic Name Description UNRCV ER Unrecoverable error An active HIGH output that indicates the occurrence of an error classified as unrecoverable. MAJ ER Major error An active HIGH output that indicates the occurrence of an error classified as major. FAULTS ERROR CONTROL Document # MICRO-3 Rev. C Page 12 of 24 PACE1750A SIGNAL DESCRIPTIONS (Continued) BUS CONTROL Mnemonic Name Description D/I Data or instruction An output signal that indicates whether the current bus cycle access is for Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not assigned to the CPU. This line can be used as an additional memory address bit for systems that require separate data and program memory. R/W Read or write An output signal that indicates direction of data flow with respect to the current bus master. A HIGH indicates a read or input operation and a LOW indicates a write or output operation. The signal is three-state during bus cycles not assigned to the CPU. M/IO Memory or I/O An output signal that indicates whether the current bus cycle is memory (HIGH) or I/O (LOW). This signal is three-state during bus cycles not assigned to the CPU. STRBA Address strobe An active HIGH output that can be used to externally latch the memory or I/O address at the HIGH-to-LOW transition of the strobe. The signal is three-state during bus cycles not assigned to the CPU. RDYA Address ready An active HIGH input that can be used to extend the address phase of a bus cycle. When RDYA is not active, wait states are inserted by the device to accommodate slower memory or I/O devices. STRBD Data strobe An active LOW output that can be used to strobe data in memory and XIO cycles. This signal is three-state during bus cycles not assigned to the CPU. RDYD Data ready An active HIGH input that extends the data phase of a bus cycle. When RDYD is not active, wait states are inserted by the device to accommodate slower memory or I/O devlces. INFORMATION BUS Mnemonic Name Description IB0 - IB15 Information bus A bidirectional time-multiplexed address/data bus that is three-state during bus cycles not assigned to the CPU. IB0 is the most significant bit. Mnemonic Name Description AK0 - AK3 Access key Outputs used to match the access lock in the MMU for memory accesses (a mismatch will cause the MMU to pull the MEM PRT ER signal LOW), and also indicates processor state (PS). Privileged instructions can be executed with PS = 0 only. These signals are three-state during bus cycles not assigned to the CPU. AS0 - AS3 Address state Outputs that select the page register group in the MMU. It is three-state during bus cycles not assigned to the CPU. [These outputs together with D/I can be used to expand the device direct addressing space to 4 MBytes, in a nonprotected mode (no MMU)]. However, using this addressing mode may produce situations not specified in MIL-STD-1750. STATUS BUS Document # MICRO-3 Rev. C Page 13 of 24 PACE1750A SIGNAL DESCRIPTIONS (Continued) BUS ARBITRATION Mnemonic Name Description BUS REQ Bus request An active LOW output that indicates the CPU requires the bus. It becomes inactive when the CPU has acquired the bus and started the bus cycle. BUS GNT Bus grant An active LOW input from an external arbiter that indicates the CPU currently has the highest priority bus request. If the bus is not used and not locked, the CPU may begin a bus cycle, commencing with the next CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), threestating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA, STRBD), and all the other lines that go three-state when this CPU does not have the bus. BUS BUSY Bus busy An active LOW, bidirectional signal used to establish the beginning and end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used for sampling bits into the fault register. It is three-state in bus cycles not assigned to this CPU. However, the CPU monitors the BUS BUSY line for latching non-CPU bus cycle faults into the fault register. BUS LOCK Bus lock An active low, bi-directional signal used to lock the bus for successive bus cycles. During non-locked bus cycles, the BUS LOCK signal mimics the BUS BUSY signal. It is three-state during bus cycles not assigned to the CPU. The following instructions will lock the bus: INCM, DECM, SB, RB, TSB, SRM, STUB and STLB. DISCRETE CONTROL Mnemonic Name Description DMA EN Direct memory Access enable NML PWRUP Normal power up An active HIGH output that indicates the DMA is enabled. It is disabled when the CPU is initialized (reset) and can be enabled or disabled under program control (I/O commands DMAE, DMAD). An active HIGH output that is set when the CPU has successfully completed the built-in self test in the initialization sequence. It can be reset by the I/O command RNS. SNEW Start new An active HIGH output that indicates a new instruction is about to start executing in the next cycle. TRIGO RST Trigger-go reset An active LOW discrete output. This signal can be pulsed low under program control I/O address 400B (Hex) and is automatically pulsed during processor initialization. Document # MICRO-3 Rev. C Page 14 of 24 PACE1750A TERMINAL CONNECTIONS Case Outline: Pin Grid Array (Case Z) Terminal Number Terminal Symbol Terminal Number Terminal Symbol Terminal Number Terminal Symbol B1 VCC L5 DMA EN D11 AS1 B2 IB14 K5 CON REQ D10 AS2 C1 IB13 L6 VCC C11 AS3 C2 IB12 K6 SNEW C10 IOL2INT D1 IB11 L7 BUS LOCK B11 VCC D2 IB10 K7 BUS GNT A10 GND E1 IB9 L8 BUS BUSY B10 IOL1INT E2 IB8 K8 M/IO A9 USR5INT F1 GND L9 D/I B9 USR4INT F2 IB7 K9 R/W A8 USR3INT G1 IB6 L10 GND B8 USR2INT G2 IB5 K11 RDYD A7 USR1INT H1 IB4 K10 RDYA B7 USR0INT H2 IB3 J11 BUS REQ A6 PWRDN INT J1 IB2 J10 STRBD B6 GND J2 IB1 H11 STRBA A5 MAJ ER K1 IB0 H10 CPU CLK B5 SYSFLT1 L2 GND G11 AK0 A4 SYSFLT0 K2 UNRCV ER G10 AK1 B4 EXT ADR ER L3 TIMER CLK F11 AK2 A3 MEM PAR ER K3 NML PWRUP F10 AK3 B3 MEM PRT ER L4 RESET E11 GND A2 IB15 K4 TRIGO RST E10 AS0 Document # MICRO-3 Rev. C Page 15 of 24 PACE1750A TERMINAL CONNECTIONS Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with GullWing Leads (Case Y) Terminal Number Terminal Symbol 1 GND 2 Terminal Symbol Terminal Number 23 IB11 46 AS2 CON REQ 24 IB12 47 AS1 3 DMA EN 25 IB13 48 AS0 4 TRIGO RST 26 IB14 49 GND 5 RESET 27 IB15 50 AK3 6 NML PWRUP 28 MEM PRT ER 51 AK2 7 TIMER CLK 29 MEM PAR ER 52 VCC 8 UNRCV ER 30 EXT ADR ER 53 AK1 9 GND 31 SYSFLT0 54 AK0 10 IB0 32 SYSFLT1 55 CPU CLK 11 IB1 33 MAJ ER 56 STRBA 12 IB2 34 GND 57 STRBD 13 IB3 35 VCC 58 BUS REQ 14 IB4 36 PWRDN INT 59 RDYA 15 IB5 37 USR0INT 60 RDYD 16 IB6 38 USR1INT 61 R/W 17 IB7 39 USR2INT 62 D/I 18 GND 40 USR3INT 63 M/IO 19 IB8 41 USR4INT 64 BUS BUSY 20 IB9 42 USR5INT 65 BUS GNT 21 VCC 43 IOL1INT 66 BUS LOCK 22 IB10 44 IOL2INT 67 SNEW 45 AS3 68 VCC Document # MICRO-3 Rev. C Terminal Number Terminal Symbol Page 16 of 24 PACE1750A TERMINAL CONNECTIONS Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Number Terminal Symbol Terminal Number Terminal Symbol Terminal Number Terminal Symbol 1 GND 23 IB13 44 AS1 2 CON REQ 24 IB14 45 AS0 3 DMA EN 25 IB15 46 GND 4 TRIGO RST 26 MEM PRT ER 47 AK3 5 RESET 27 MEM PAR ER 48 AK2 6 NML PWRUP 28 EXT ADR ER 49 AK1 7 TIMER CLK 29 SYSFLT0 50 AK0 8 UNRCV ER 30 SYSFLT1 51 CPU CLK 9 IB0 31 MAJ ER 52 STRBA 10 IB1 32 GND 53 STRBD 11 IB2 33 PWRDN INT 54 BUS REQ 12 IB3 34 USR0INT 55 RDYA 13 IB4 35 USR1INT 56 RDYD 14 IB5 36 USR2INT 57 R/W 15 IB6 37 USR3INT 58 D/I 16 IB7 38 USR4INT 59 M/IO 17 IB8 39 USR5INT 60 BUS BUSY 18 IB9 40 IOL1INT 61 BUS GNT 19 VCC 41 IOL2INT 62 BUS LOCK 20 IB10 42 AS3 63 SNEW 21 IB11 43 AS2 64 VCC 22 IB12 Note: For the 30 MHz and 40 MHz devices, Pins 19 and 46 are connected as shown. For the 15 MHz and 20 MHz devices, these pins are not internally connected to the die. Document # MICRO-3 Rev. C Page 17 of 24 PACE1750A ORDERING INFORMATION Standardized Military Drawing Part Number Pyramid Semiconductor CAGE Number 5962-8766501TX 5962-8766501UX 5962-8766501XX 5962-8766501YX 5962-8766501ZX 5962-8766502TX 5962-8766502UX 5962-8766502XX 5962-8766502YX 5962-8766502ZX 5962-8766503TX 5962-8766503UX 5962-8766503XX 5962-8766503YX 5962-8766503ZX 5962-8766504TX 5962-8766504UX 5962-8766504XX 5962-8766504YX 5962-8766504ZX 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 3DTT2 Document # MICRO-3 Rev. C Pyramid Semiconductor Part Number P1750A-15GMB P1750A-15QLMB P1750A-15CMB P1750A-15QGMB P1750A-15PGMB P1750A-20GMB P1750A-20QLMB P1750A-20CMB P1750A-20QGMB P1750A-20PGMB P1750A-30GMB P1750A-30QLMB P1750A-30CMB P1750A-30QGMB P1750A-30PGMB P1750A-40GMB P1750A-40QLMB P1750A-40CMB P1750A-40QGMB P1750A-40PGMB Page 18 of 24 PACE1750A CASE OUTLINE X: 64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C) Inches .002 .005 .008 .010 .015 .016 .018 .025 .040 .050 .185 .265 .470 .530 .590 .620 .645 1.550 1.563 mm 0.05 0.12 0.20 0.25 0.38 0.40 0.45 0.63 1.01 1.27 4.70 6.73 11.93 13.46 14.98 15.74 16.38 39.37 39.70 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Document # MICRO-3 Rev. C Page 19 of 24 PACE1750A CASE OUTLINE T: 64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G) Inches .001 .003 .005 .008 .010 .015 .016 .022 .030 .040 .050 .150 .470 .530 .590 .620 .868 1.663 mm 0.03 0.08 0.12 0.20 0.25 0.38 0.41 0.55 0.76 1.01 1.27 3.81 11.93 13.46 14.98 15.74 22.04 42.24 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration. Document # MICRO-3 Rev. C Page 20 of 24 PACE1750A CASE OUTLINE U: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .004 .006 .010 .012 .020 .050 .100 .116 .250 .560 .570 .800 .955 1.090 mm 0.05 0.10 0.15 0.25 0.30 0.51 1.27 2.54 2.95 6.40 14.22 14.48 20.32 24.25 27.69 NOTES: 1) 2) 3) 4) 5) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched may be either notched or square. Document # MICRO-3 Rev. C Page 21 of 24 PACE1750A CASE OUTLINE Y: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .004 .005 .008 .010 .012 .015 .016 .020 .024 .040 .050 .100 .115 .570 .800 .955 1.010 1.090 mm 0.10 0.12 0.20 0.25 0.30 0.38 0.41 0.50 0.60 1.02 1.27 2.54 2.92 14.48 20.32 24.25 25.65 27.68 NOTES: 1) 2) 3) 4) 5) 6) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched my be either notched or square (with radius). Case Y is derived from Case U by forming the leads to the shown gullwing configuration. Document # MICRO-3 Rev. C Page 22 of 24 PACE1750A CASE OUTLINE Z: 68-Pin Pin Grid Array (PGA) (Ordering Code PG) Inches .016 .020 .040 .050 .059 .060 .098 .100 .120 .150 .170 1.010 1.089 1.160 mm 0.41 0.50 1.01 1.27 1.49 1.52 2.49 2.54 3.04 3.81 4.32 25.65 27.66 29.46 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid. Document # MICRO-3 Rev. C Page 23 of 24 PACE1750A REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: MICRO-3 PACE1750A CMOS 16-BIT PROCESSOR REV. ISSUE DATE ORIG. OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-created electronic version C Oct-05 JDB Altered case outline drawing for case X and case T Document # MICRO-3 Rev. C DESCRIPTION OF CHANGE Page 24 of 24