P1750A/SOS SINGLE CHIP, 20MHz to 30MHz, CMOS/SOS SPACE PROCESSOR FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Built-In Self Test 24 User Accessible Registers CMOS/SOS Processor with 32 and 48-Bit Floating Point Arithmetic Single 5V ± 10% Power Supply Integer DAIS Mix Performance 3.0 MIPS at 30 MHz TTL Signal Level compatible Inputs and Outputs Available with Class S type manufacturing, screening, and testing Multiprocessor and Co-processor capability SOS Insulated substrate technology provides absolute latch up immunity and excellent SEU tolerance Total Dose ≥ 100 Krads (Si) 20, 25, and 30 MHz operation over the Military Temperature Range Extensive Error and Fault Management and Interrupt Capability Built-In Function (BIF) for User Defined Instructions Two programmable Timers SOS devices are fully interchangeable with application-proven CMOS P1750A Processors; SMD 5962-87665 Available in: - 68-Lead Quad Pack (Leaded Chip Carrier) with Optional Gull Wing GENERAL DESCRIPTION The PACE1750A is a general purpose, application-proven, single chip, 16-bit CMOS microprocessor designed for high performance floating point and integer arithmetic, with extensive real time environment support. It offers a variety of data types, including bits, bytes, 16-bit and 32bit integers, and 32-bit and 48-bit floating point numbers. It provides 13 addressing modes, including direct, indirect, indexed, based, based indexed and immediate long and short, and it can access 2 MWords of segmented memory space (64 KWords segments without use of a MIL-STD1750A MMU). The PACE1750A offers a well-rounded instruction set with 130 instruction types, including a comprehensive integer, floating point, integer-to-floating point and floating point-to-integer set, a variety of stack manipulation instructions, high level language support instructions such as Compare Between Bounds and Loop Control Instructions. It also offers some unique instructions such as vectored l/O, supports executive and user modes, and provides an escape mechanism which allows user-defined instructions using a coprocessor. The instruction set is fully compliant with MIL-STD-1750A. The chip includes 16 general purpose registers, 8 other user-accessible registers, and an array of real time application support resources, such as 2 programmable timers, a complete interrupt controller supporting 16 levels of prioritized internal and external interrupts, and a faults and exceptions handler controlling internally and externally generated faults. The P1750A uses a single multiplexed 16-bit parallel bus. Status signals are provided to determine whether the processor is in the memory or I/O bus cycle, reading and writing, and whether the bus cycle is for data or instructions. The basic bus cycle is 4 clocks long. The P1750A will extend the cycle by insertion of wait states in the address and data phases (in response to RDYA and RDYD signals, repectively) and will hold the machine in HI-Z if this CPU has not acquired the bus. A typical non-bus cycle is three clocks long. However, variable length cycles are used for such repetitive operations as multiply, divide, scale and normalize, reducing significantly the number of CPU CLOCKS per operation step and resulting in very fast integer and floating point execution times. Document # MICRO-6 REV B Revised August 2005 P1750A/SOS ABSOLUTE MAXIMUM RATINGS1 RECOMMENDED OPERATING CONDITIONS Supply Voltage Range -0.5V to 7.0V Input Voltage Range -0.5V to VCC + 0.5V Supply Voltage Range Storage Temperature Range -65°C to + 150°C Input Current Range -30mA to +5mA Voltage Applied to Inputs -0.5V to VCC + 0.5V Current Applied to Outputs3 150 mA 4.5V to 5.5V Case Operating Temperature -55°C to +125°C Range Maximum Power Dissipation2 1.5W Operating worst case power dissipation (outputs open): 0.5W at 20MHz 0.6W at 25MHz 0.7W at 30MHz Lead Temperature Range (soldering 10 seconds) 300°C Thermal resistance, junction-to-case (θJC): Packages QL and QG 8°C/W NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., IOS 3. Duration one second or less. RADIATION HARDNESS Total Dose - (All specification still within limits) > 1 x 105 Rad (Si) [1] Neutron Hardness 1 x 1015 neutrons/cm2 [2] Single Event Upset > 9 x 10-10 errors per day [3] Radiation Induced Latch Up Absolute immunity [4] NOTES: [1] Tested MIL-STD-883 TM 1019 [2] CMOS/SOS is a majority carrier technology and is therefore unaffected. CMOS/SOS typically withstands neutron radiation to > 1015 (limit of available test equipment). Testing waived, MILSTD-883 TM 5005 [3] Tested at Brookhaven National Laboratory [4] Physically impossible for SOS device to suffer destructive latch up from natural space ionizing radiation. Document # MICRO-6 REV B Page 2 of 20 P1750A/SOS DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit VIH Input HIGH Level Voltage 2.0 VCC + 0.5 V VIL Input LOW Level Voltage2 –0.5 0.8 V VOH Output HIGH Level Voltage VOL Output LOW Level Voltage Conditions1 2.4 V VCC = 4.5V IOH = –8.0mA VCC – 0.2 V VCC = 4.5V IOH = –300µA 0.5 V VCC = 4.5V IOL = 8.0mA 0.2 V VCC = 4.5V IOL = 300µA 300 µA VIN = VCC, VCC = 5.5V IIH2 Input HIGH Level Current, IB0 – IB15, BUS BUSY, BUS LOCK 100 µA VIN = VCC, VCC = 5.5V IIL1 Input LOW Level Current, except IB0 – IB15, BUS BUSY, BUS LOCK –50 µA VIN = GND, VCC = 5.5V IIL2 Input LOW Level Current, IB0 – IB15, BUS BUSY, BUS LOCK –50 µA VIN = GND, VCC = 5.5V IOZH Output Three-State Current 50 µA VOUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA VOUT = 0.5V, VCC = 5.5V ICCQC Quiescent Power Supply Current (CMOS Input Levels) 25 mA VIN < 0.2V or < VCC – 0.2V, f = 0MHz, Outputs Open, VCC = 5.5V ICCQT Quiescent Power Supply Current (TTL Input Levels) 100 mA VIN < 3.4V, f = 0MHz, Outputs Open, VCC = 5.5V ICCD Dynamic Power 20 MHz 90 mA VIN = 0V to VCC, tr = tf = 2.5 ns, Supply Current 25 MHz 100 mA Outputs Open, 30 MHz 125 mA VCC = 5.5V mA VOUT = GND, VCC = 5.5V Input HIGH Level Current, IIH1 except IB0 – IB15, BUS BUSY, BUS LOCK IOS Output Short Circuit Current3 CIN Input Capacitance 10 pF COUT Output Capacitance 15 pF CI/O Bi-directional Capacitance 15 pF –25 Notes 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. Document # MICRO-6 REV B Page 3 of 20 P1750A/SOS SIGNAL PROPAGATION DELAYS 1,2 20 MHz Symbol Parameter Min Max 25 MHz Min Max 30 MHz Min Max Unit tC(BR)L BUS REQ 33 30 27 ns tC(BR)H BUS REQ 33 30 27 ns tBGV(C) BUS GNT setup 5 5 5 ns tC(BG)X BUS GNT hold 5 5 5 ns tC(BB)L BUS BUSY LOW 38 33 24 ns tC(BB)H BUS BUSY HIGH 38 33 24 ns tBBV(C) BUS BUSY setup 5 5 5 ns tC(BB)X BUS BUSY hold 5 5 5 ns tC(BL)L BUS LOCK LOW 38 34 32 ns tC(BL)H BUS LOCK HIGH 38 34 32 ns tBLV(C) BUS LOCK setup tC(BL)X (IN) BUS LOCK hold 5 5 5 ns 5 5 5 ns tC(ST)V M/ IO, R/W Status 32 28 25 ns tC(ST)V AS0-AS3, AK0-AK3, D/I Status 27 23 21 ns tC(ST)X AS0-AS3, AK0-AK3, D/I Status, M/ IO, R/W tC(SA)H STRBA HIGH 24 20 18 ns tC(SA)L STRBA LOW 24 20 18 ns tSAL(IBA)X Address hold from STRBA LOW 0 0 0 ns 5 5 5 ns tRAV(C) RDYA setup 5 5 5 ns tC(RA)X RDYA hold 5 5 5 ns tC(SDW)L tC(SD)H STRBD LOW write 24 20 18 ns STRBD HIGH 24 20 18 ns 24 20 18 ns tFC(SDR)L STRBD LOW read tSDRH(IBD)X STRBD HIGH 0 0 0 ns tSDWH(IBD)X STRBD HIGH 28 28 28 ns tSDL(SD)H STRBD write 32 32 32 ns tRDV(C) RDYD setup 5 5 5 ns tC(RD)X RDYD hold 5 5 5 ns tC(IBA)V IB0-IB15 tFC(IBA)X IB0-IB15 tIBDRV(C) IB0-IB15 setup tC(IBD)X IB0-IB15 hold (read) tC(IBD)X Data valid out (write) Document # MICRO-6 REV B 36 32 28 ns 0 0 0 ns 10 10 10 ns 10 10 10 ns 0 0 0 ns Page 4 of 20 P1750A/SOS SIGNAL PROPAGATION DELAYS 1,2 (continued) 20 MHz Symbol Parameter Min 25 MHz Max Min 30 MHz Max Min Max Unit tFC(IBD)V IB0-IB15 34 34 32 ns tC(SNW) SNEW 34 30 28 ns tFC(TGO) TRIGO RST 34 30 28 ns tRSTL(DMA ENL) DMA enable 44 40 38 ns tC(DME) DMA enable 44 40 38 ns tFC(NPU) Normal power up 44 40 38 ns Clock to major error unrecoverable 60 55 52 ns RESET 50 45 40 ns tC(ER) tRSTL(NPU) tREQV(C) Console request 0 0 0 ns tC(REQ)X Console request 10 10 10 ns tFV(BB)H Level sensitive faults 5 5 5 ns tBBH(F)X Level sensitive faults 5 5 5 ns tIRV(C) IOL1-2INT user interrupt (0-5) setup 0 0 0 ns tC(IR)X Power down interrupt level sensitive hold 15 15 15 ns 25 25 20 ns tRSTL (tRSTH) Reset pulse width tC(XX)Z tf(F), t1(1) tr, tf Clock to three-state Edge sensitiive pulse width Clock rise and fall 24 5 20 5 5 18 5 5 ns ns 5 ns Notes 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced. When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle. 3. Functional test shall consist of the same functional test used when testing the equivalent bulk CMOS, MIL-STD-883 Compliant, Class B SMD 596287665 device. Document # MICRO-6 REV B Page 5 of 20 P1750A/SOS MINIMUM WRITE BUS CYCLE TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-6 REV B Page 6 of 20 P1750A/SOS MINIMUM READ BUS CYCLE TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-6 REV B Page 7 of 20 P1750A/SOS MINIMUM WRITE BUS CYCLE, FOLLOWED BY A NON-BUS CYCLE, TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-6 REV B Page 8 of 20 P1750A/SOS TRIGO RST DISCRETE TIMING DIAGRAM DMA EN DISCRETE TIMING DIAGRAM NORMAL POWER UP DISCRETE TIMING DIAGRAM XIO OPERATIONS SNEW DISCRETE TIMING DIAGRAM Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-6 REV B Page 9 of 20 P1750A/SOS EXTERNAL FAULTS AND INTERRUPTS TIMING DIAGRAM Edge-sensitive interrupts and faults (SYSFLT0, SYSFLT1) min. pulse width Level-sensitive interrupts Note: tC(IR)X max = 35 clocks Level-sensitive faults CON REQ Note: All time measurements on active signals relate to the 1.5 volt level. Document # MICRO-6 REV B Page 10 of 20 P1750A/SOS BUS ACQUISITION Note: A CPU contending for the BUS will assert the BUS REQ line, and will acquire it when BUS GNT is assserted and the BUS is not locked (BUS LOCK is high). SWITCHING TIME TEST CIRCUITS Standard Output (Non-Three-State) Three-State Note: All time measurements on active signals relate to the 1.5 volt level. Parameter V0 VMEA tPLZ ≥ 3V 0.5V tPHZ 0V VCC – 0.5V tPXL VCC/2 1.5V tPXH VCC/2 1.5V Document # MICRO-6 REV B Page 11 of 20 P1750A/SOS SIGNAL DESCRIPTIONS CLOCKS AND EXTERNAL REQUESTS Mnemonic Name Description CPU CLK CPU clock A single phase input clock signal (0-40 MHz, 40 percent to 60 percent duty cycle. TIMER CLK Timer clock A 100 KHz input that, after synchronization with CPU CLK, provides the clock for timer A and timer B. If timers are used, the CPU CLK signal frequency must be > 300 KHz. RESET Reset An active LOW input that initializes the device. CON REQ Console request An active LOW input that initiates console operations after completion of the current instruction. INTERRUPT INPUTS Mnemonic Name Description PWRDN INT Power down interrupt An interrupt request input that cannot be masked or disabled. This signal is active on the positive going edge or the high level, according to the interrupt mode bit in the configuration register. USR0INT USR5INT User interrupt Interrupt request input signals that are active on the positive going edge or the high level, according to the interrupt mode bit in the configuration register. IOL1INT IOL2INT I/O level interrupts Active HIGH interrupt request inputs that can be used to expand the number of user interrupts. Mnemonic Name Description MEM PRT ER Memory protect error An active LOW input generated by the MMU or BPU, or both and sampled by the BUS BUSY signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus cycle). MEM PAR ER Memory parity error An active LOW input sampled by the BUS BUSY signal into bit 2 of the fault register. EXT ADR ER External address error An active LOW input sampled by the BUS BUSY signal into the Fault register (bit 5 or 8), depending on the cycle (memory or I/O). SYSFLT0 SYSFLT1 System fault 0, System fault 1, Asynchronous, positive edge-sensitive inputs that set bit 7 (SYSFLT0) or bits 13 and 15 (SYSFLT1) in the Fault register. Mnemonic Name Description UNRCV ER Unrecoverable error An active HIGH output that indicates the occurrence of an error classified as unrecoverable. MAJ ER Major error An active HIGH output that indicates the occurrence of an error classified as major. FAULTS ERROR CONTROL Document # MICRO-6 REV B Page 12 of 20 P1750A/SOS SIGNAL DESCRIPTIONS (Continued) BUS CONTROL Mnemonic Name Description D/I Data or instruction An output signal that indicates whether the current bus cycle access is for Data (HIGH) or Instruction (LOW). It is three-state during bus cycles not assigned to the CPU. This line can be used as an additional memory address bit for systems that require separate data and program memory. R/W Read or write An output signal that indicates direction of data flow with respect to the current bus master. A HIGH indicates a read or input operation and a LOW indicates a write or output operation. The signal is three-state during bus cycles not assigned to the CPU. M/IO Memory or I/O An output signal that indicates whether the current bus cycle is memory (HIGH) or I/O (LOW). This signal is three-state during bus cycles not assigned to the CPU. STRBA Address strobe An active HIGH output that can be used to externally latch the memory or I/O address at the HIGH-to-LOW transition of the strobe. The signal is three-state during bus cycles not assigned to the CPU. RDYA Address ready An active HIGH input that can be used to extend the address phase of a bus cycle. When RDYA is not active, wait states are inserted by the device to accommodate slower memory or I/O devices. STRBD Data strobe An active LOW output that can be used to strobe data in memory and XIO cycles. This signal is three-state during bus cycles not assigned to the CPU. RDYD Data ready An active HIGH input that extends the data phase of a bus cycle. When RDYD is not active, wait states are inserted by the device to accommodate slower memory or I/O devlces. INFORMATION BUS Mnemonic Name Description IB0 - IB15 Information bus A bidirectional time-multiplexed address/data bus that is three-state during bus cycles not assigned to the CPU. IB0 is the most significant bit. Mnemonic Name Description AK0 - AK3 Access key Outputs used to match the access lock in the MMU for memory accesses (a mismatch will cause the MMU to pull the MEM PRT ER signal LOW), and also indicates processor state (PS). Privileged instructions can be executed with PS = 0 only. These signals are three-state during bus cycles not assigned to the CPU. AS0 - AS3 Address state Outputs that select the page register group in the MMU. It is three-state during bus cycles not assigned to the CPU. [These outputs together with D/I can be used to expand the device direct addressing space to 4 MBytes, in a nonprotected mode (no MMU)]. However, using this addressing mode may produce situations not specified in MIL-STD-1750. STATUS BUS Document # MICRO-6 REV B Page 13 of 20 P1750A/SOS SIGNAL DESCRIPTIONS (Continued) BUS ARBITRATION Mnemonic Name Description BUS REQ Bus request An active LOW output that indicates the CPU requires the bus. It becomes inactive when the CPU has acquired the bus and started the bus cycle. BUS GNT Bus grant An active LOW input from an external arbiter that indicates the CPU currently has the highest priority bus request. If the bus is not used and not locked, the CPU may begin a bus cycle, commencing with the next CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), threestating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA, STRBD), and all the other lines that go three-state when this CPU does not have the bus. BUS BUSY Bus busy An active LOW, bidirectional signal used to establish the beginning and end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used for sampling bits into the fault register. It is three-state in bus cycles not assigned to this CPU. However, the CPU monitors the BUS BUSY line for latching non-CPU bus cycle faults into the fault register. BUS LOCK Bus lock An active low, bi-directional signal used to lock the bus for successive bus cycles. During non-locked bus cycles, the BUS LOCK signal mimics the BUS BUSY signal. It is three-state during bus cycles not assigned to the CPU. The following instructions will lock the bus: INCM, DECM, SB, RB, TSB, SRM, STUB and STLB. DISCRETE CONTROL Mnemonic Name Description DMA EN Direct memory Access enable NML PWRUP Normal power up An active HIGH output that indicates the DMA is enabled. It is disabled when the CPU is initialized (reset) and can be enabled or disabled under program control (I/O commands DMAE, DMAD). An active HIGH output that is set when the CPU has successfully completed the built-in self test in the initialization sequence. It can be reset by the I/O command RNS. SNEW Start new An active HIGH output that indicates a new instruction is about to start executing in the next cycle. TRIGO RST Trigger-go reset An active LOW discrete output. This signal can be pulsed low under program control I/O address 400B (Hex) and is automatically pulsed during processor initialization. Document # MICRO-6 REV B Page 14 of 20 P1750A/SOS TERMINAL CONNECTIONS Case Outlines: 1) Leaded Chip Carrier with unformed leads and 2) Leaded Chip Carrier with Gull-Wing Leads Terminal Number Terminal Symbol 1 GND 2 Terminal Symbol Terminal Number 23 IB11 46 AS2 CON REQ 24 IB12 47 AS1 3 DMA EN 25 IB13 48 AS0 4 TRIGO RST 26 IB14 49 GND 5 RESET 27 IB15 50 AK3 6 NML PWRUP 28 MEM PRT ER 51 AK2 7 TIMER CLK 29 MEM PAR ER 52 VCC 8 UNRCV ER 30 EXT ADR ER 53 AK1 9 GND 31 SYSFLT0 54 AK0 10 IB0 32 SYSFLT1 55 CPU CLK 11 IB1 33 MAJ ER 56 STRBA 12 IB2 34 GND 57 STRBD 13 IB3 35 VCC 58 BUS REQ 14 IB4 36 PWRDN INT 59 RDYA 15 IB5 37 USR0INT 60 RDYD 16 IB6 38 USR1INT 61 R/W 17 IB7 39 USR2INT 62 D/I 18 GND 40 USR3INT 63 M/IO 19 IB8 41 USR4INT 64 BUS BUSY 20 IB9 42 USR5INT 65 BUS GNT 21 VCC 43 IOL1INT 66 BUS LOCK 22 IB10 44 IOL2INT 67 SNEW 45 AS3 68 VCC Document # MICRO-6 REV B Terminal Number Terminal Symbol Page 15 of 20 P1750A/SOS ORDERING INFORMATION Document # MICRO-6 REV B Page 16 of 20 P1750A/SOS CASE OUTLINE 1: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .003 .006 .010 .015 .018 .050 .060 .080 .095 .225 .570 .800 .955 mm 0.05 0.08 0.15 0.25 0.38 0.45 1.27 1.52 2.03 2.41 5.72 14.48 20.32 24.25 NOTES: 1) 2) 3) 4) 5) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched may be either notched or square. Document # MICRO-6 REV B Page 17 of 20 P1750A/SOS CASE OUTLINE 2: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .003 .010 .015 .018 .020 .050 .570 .800 .955 1.230 mm 0.08 0.25 0.38 0.45 0.51 1.27 14.48 20.32 24.25 31.26 NOTES: 1) 2) 3) 4) 5) 6) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched my be either notched or square (with radius). Case 2 is derived from Case 1 by forming the leads to the shown gullwing configuration. Document # MICRO-6 REV B Page 18 of 20 P1750A/SOS LEAD FORM DETAIL Symbol INCHES Min Max A 0.048 A1 0.011 0.031 B 0.016 0.021 C 0.004 0.008 e1 0.090 0.050 BSC D 1.210 1.250 D1 0.945 0.965 D2 0.800 BSC E 1.210 1.250 E1 0.945 0.965 E2 L* 0.800 BSC 0.270 Nominal L0 0.120 0.210 L3 0.040 0.050 L4 0.086 0.109 R1 0.018 0.020 R2 Φ1 0.018 0.020 4° 8° Φ2 A0** -1° 7° 0.141 * Lead length in the straight lead configuration, prior to leadforming (used for all test and in-process WIP operations). ** Measured from the highest of the top of the leads or the top of the lid. Document # MICRO-6 REV B Page 19 of 20 P1750A/SOS REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: MICRO-6 PACE1750A CMOS/SOS 16-BIT PROCESSOR REV. ISSUE DATE ORIG. OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-created electronic version Document # MICRO-6 REV B DESCRIPTION OF CHANGE Page 20 of 20