PACE1753/SOS SINGLE CHIP, MIL-STD-1750A MEMORY MANAGEMENT UNIT (MMU) CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE. Provides the following additional functions: — EDAC, Error Detection and Correction—or parity generation and detection — Correct data register—for diagnostics — First memory failing address register — Illegal address error detection— programmable — Multi-Master arbitration 8-bit extended address laches and drivers on chip. 20, 25 and 30 MHz operation over the Military Temperature Range Single 5V ± 10% Power Supply Available with Class S manufacturing, screening, and testing. SOS Insulated substrate latch-up immunity and excellent SEU tolerance. SOS devices are fully interchangeable with application-proven SMD CMOS P1753 devices. Available in: — 68-Lead Quad Pack (Leaded Chip Carrier) with optional Gull Wing. MEMORY MANAGEMENT UNIT AND BLOCK PROTECT UNIT “COMBO” (PACE1753)—FUNCTIONAL DESCRIPTION The PACE1753 (COMBO) is a support chip for the PACE1750A/AE microprocessor family. It provides the following supporting functions to the system: 1. Memory management and access protection for up to 1M words. 2 Physical memory write protection for up to 1M words memory in pages of 1K words each. Separate protection is provided for the CPU and for DMA in systems which include DMA. 3. Detection of illegal l/O accesses (as defined by MILSTD-1750A) or access to an unimplemented block of memory. In each case an error flag is generated to the processor. 4 Detection of double errors on the data bus and correction of single errors. An error signal is generated to the processor when a multiple error is detected. 5. RDYA generation. Up to three wait states can be inserted in the address phase of the bus by generating a not-ready, RDYA low signal. The number of wait states required can be programmed in an internal register in the COMBO. 6. Bus arbitration for up to 4 masters. Arbitration is done on a fixed priority basis (i.e. by interconnection of hardware). (In 68 pin package only). Document # MICRO-8 REV B Revised August 2005 PACE1753/SOS ABSOLUTE MAXIMUM RATINGS1 RECOMMENDED OPERATING CONDITIONS Supply Voltage Range 0.5V to +7.0V Input Voltage Range 0.5V to VCC + 0.5V Supply Voltage Range 4.5V to +5.5V Storage Temperature Range –65°C to +150°C –55°C to +125°C Input Current Range –30mA to +5mA Case Operating Temperature Range Current applied to any output3 150mA Maximum Power Dissipation2 1.5W Lead Temperature Range (soldering 10 seconds) 300°C Thermal resistance (θJC): QL and QG packages 8°C/W Operating Maximum Power Dissipation (Outputs Open) Device Type 20MHz Device Type 30MHz Device Type 40MHz 0.5W 0.6W 0.7W Notes 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., IOS. 3. Duration 1 second or less. Document # MICRO-8 REV B Page 2 of 17 PACE1753/SOS DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit Conditions1 VIH Input HIGH Voltage 2.0 VCC + 0.5 V VIL Input LOW Voltage2 –0.5 0.8 V VCD Input Clamp Diode Voltage –1.2 V VCC = 4.5V, IIN = –18mA VOH Output HIGH Voltage 2.4 V VCC = 4.5V, IOH = –8.0mA VCC – 0.2 V VIN = 0.8V, 2.0V IOH = –300µA 0.65 V VCC = 4.5V, IOL = 8.0mA 0.2 V VIN = 0.8V, 2.0V IOL = 300µA 0.65 V VCC = 4.5V, IOL = 20.0mA 0.2 V VIN = 0.8V, 2.0V IOL = 300µA 300 µA VIN = VCC, VCC = 5.5V 100 µA –50 µA VOL VOL IIH IIH IIL Output LOW Voltage,4 except EXT ADR0 – EXT ADR7 Output LOW Voltage,4 EXT ADR0 – EXT ADR7 Input HIGH Current, except IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Input HIGH Current, IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 Input LOW Current, except IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 VIN = VCC, VCC = 5.5V VIN = GND, VCC = 5.5V IIL Input LOW Current, IB0 – IB15, EDC0 – EDC5, EXT ADR0 – EXT ADR7 –50 µA VIN = GND, VCC = 5.5V IOZH Output Three-State Current 50 µA VOUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA VOUT = 0.5V, VCC = 5.5V ICCQC Quiescent Power Supply Current (CMOS Input Levels, Active) 60 mA VIN < 0.2V or < VCC – 0.2V f = 0MHz, Outputs Open, VCC = 5.5V ICCQT Quiescent Power Supply Current (TTL Input Levels, Active) 110 mA VIN = 3.4V, f = 0MHz, All Inputs, Outputs Open, VCC = 5.5V Dynamic Power Supply 90 mA Current 100 mA 125 mA VCC = 0V to VCC, tr = tf = 2.5 ns, Outputs Open, VCC = 5.5V mA VOUT = GND, VCC = 5.5V ICCD Current3 –25 F = 20MHz F = 30MHz F = 40MHz IOS Output Short Circuit CIN Input Capacitance 10 pF Inputs Only COUT Output/Bi-directional Capacitance 15 pF Outputs Only (Including I/O Buffers) Notes 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. 4. Test may be performed by setting/forcing the parameter limit (voltage) and measuring the appropriate current parameter. Document # MICRO-8 REV B Page 3 of 17 PACE1753/SOS AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V) 20 MHz Symbol TD/I (EXT ADR)V Parameter MMU Cache Hit Min Max 25MHz Min Max 30 MHz Min Max Unit 27 23 21 ns TSTRBD (EXT ADR ERR)L External Address Error 37 33 30 ns TC (IBD CORR) Error Correction Read Cycle 32 28 26 ns IBDV (SING ERR)H Error Correction Read Cycle 37 33 31 ns TC (SING ERR)L Error Correction Read Cycle 27 23 21 ns TIBDV (EDC GEN)V EDAC or Parity Write Cycle 32 28 26 ns TSTRBD (EX RDY)L MMU Cache Miss 27 23 21 ns TC (EX RDY)H MMU Cache Miss 27 23 21 ns TC (WR PROT)L MMU Cache Miss 36 32 30 ns TSTRBDH (WR PROT)H MMU Cache Miss 27 23 21 ns TC (GNT1)H Arbiter LOW to HIGH Priority 34 30 28 ns TC (GNT0)L Arbiter LOW to HIGH Priority 34 30 28 ns TC (GNT0)H Arbiter HIGH to LOW Priority 34 30 28 ns TC (GNT1)L Arbiter HIGH to LOW Priority 34 30 28 ns TC (RDYA) Address Ready 32 28 26 ns TFC (IB OUT)V Clock to IB Out Valid (I/O Read) 40 38 36 ns TIBDIN (MEM PAR ERR) Parity Mode 36 32 30 ns TC (MEM PRT ERR) Memory Protect Error 64 60 58 ns TSTRBD (WR PROT) Write Protect Cache Hit 27 23 21 ns TC (WR PROT)L Write Protect Cache Miss 37 33 31 ns TSTRBDH (WR PROT)H Write Protect Cache Miss 27 23 21 ns TD/I (PROT FLAG) Cache Hit (BPU Protection Error) 52 48 46 ns TD/I (PROT FLAG) Cache Hit (MMU Key-Lock Error) 42 38 36 ns TC (PROT FLAG) Cache Miss (BPU Protection Error) 67 63 61 ns TC (PROT FLAG) Cache Hit (MMU Key-Lock Error) 52 48 46 ns TC (EXT ADR) Clock to EXT ADR Valid (Miss) 38 34 32 ns Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. VIL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. 4. Pulse width of WR PROT/PROT FLAG shall be ≥ 80% of STRBD pulse width. 5. Functional tests shall consist of the same functional tests used when testing the equivalent bulk CMOS, MIL-STD-883 compliant, Class B SMD 5962-89505 device. Document # MICRO-8 REV B Page 4 of 17 PACE1753/SOS TERMINAL CONNECTIONS - PACKAGES QL AND QG Case Outlines Terminal Number U and Y Terminal Symbol Terminal Number Terminal Symbol Terminal Number Terminal Symbol 1 GND 24 IB12 47 AS1 2 EDC0 25 IB13 48 AS0 3 EDC1 26 IB14 49 BUS REQ 4 EDC2 27 IB15 50 AK3 5 RESET 28 MEM PRT ERR 51 AK2 6 EDC3 29 MEM PAR ERR 52 BUS GNT 1 7 EDC4 30 EXT ADR ERR 53 AK1 8 EDC5 31 RAM DIS 54 AK0 9 BUS GNT2 32 SING ERR 55 CLK 10 IB0 33 DMA ACK 56 STRBA 11 IB1 34 GND 57 STRBD 12 IB2 35 VCC 58 BUS REQ 0 13 IB3 36 EXT ADR0 59 EX RDY 14 IB4 37 EXT ADR1 60 WR PROT/PROT FLAG 15 IB5 38 EXT ADR2 61 R/W 16 lB6 39 EXT ADR3 62 D/I 17 IB7 40 EXT ADR4 63 M/IO 18 BUS REQ 3 41 EXT ADR5 64 RDYA 19 IB8 42 EXT ADR6 65 BUS GNT 0 20 IB9 43 EXT ADR7 66 BUS LOCK 21 BUS GNT 3 44 GND 67 BUS REQ 1 22 IB10 45 AS3 68 VCC 23 IB11 46 AS2 Document # MICRO-8 REV B 2 Page 5 of 17 PACE1753/SOS MMU Cache Hit External Address Error Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-8 REV B Page 6 of 17 PACE1753/SOS Error Correction (Write Cycle) Memory Protect Error Error Correction (Read Cycle) Ready Address Memory Parity Error Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-8 REV B Page 7 of 17 PACE1753/SOS MMU Cache Miss Cycle (WA = 0) MMU Cache Miss Cycle (WA > 0) * The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT FLAG. (See BPU Description), T = 1 Clock Period. Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-8 REV B Page 8 of 17 PACE1753/SOS Low Priority to High Priority Transition Bus Arbitrator High Priority to Low Priority Transition Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-8 REV B Page 9 of 17 PACE1753/SOS SWITCHING WAVEFORMS AND TEST CIRCUIT (Continued) IB Bus Output (0:15) Standard Output (Non Three-State) Three-State Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-8 REV B Parameter VO VMEA TPLZ ≥ 3V 0.5V TPHZ 0V VCC – 0.5V TPXL VCC/2 1.5V TPXH VCC/2 1.5V Page 10 of 17 PACE1753/SOS PIN FUNCTIONS Symbol Name Description BUS REQ0 BUS REQ3 Bus Request1 Active LOW inputs that indicate a requirement for the bus from 4 masters on the bus. The master assigned to pin BUS-REQ0 has highest priority; the master assigned to pin BUS-REQ3 has lowest priority. BUS LOCK Bus Lock1 An active LOW input that indicates that the one master assigned the bus is using the bus. A new master will receive a bus grant only after this signal becomes inactive. BUS GNT0 BUS GNT3 Bus Grant1 Active LOW outputs indicating which master was granted the bus. It remains active during BUS LOCK unless a higher master request occurs, which resets it. However, the higher master will be granted the bus only after the present master’s BUS LOCK releases the bus. M/IO Memory or I/O An input signal that indicates whether the current bus cycle is a memory (HIGH) or l/O (LOW) cycle. D/I Data or Instruction An input signal that indicates whether the current bus cycle access is for data (HIGH) or instruction (LOW). R/W Read or Write An input signal that indicates the direction of data flow on the bus. A HIGH indicates a memory read or input operation into the master and a LOW indicates a memory write or output operation from the master. STRBA Address Strobe An active HIGH input used to latch the address at the HIGH-toLOW transition of the strobe. STRBD Data Strobe An active LOW input used to strobe data in memory and I/O cycles. CPU-CLK CPU Clock A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) RESET Reset An active LOW input that initializes the device. AK0 - AK3 Access Key Active HIGH inputs used to match the access lock in the MMU page for memory accesses. A mismatch will cause the MEM PRT ERR signal to become active. AS0 - AS3 Address State Active HIGH inputs that select the page register group in the MMU. In the DMA physical demultiplexed mode, AS(0:1) will receive the 9th and 10th most significant bits of the physical address for use in the BPU function. EXT ADR0 EXT ADR7 Extended Addresses Bus A bi-directional active HIGH bus. In CPU cycles, it is an output bus which is used to select one of 256 pages, 4K words each, expanding the direct addressing space to 1M word. In DMA cycles, indicated by DMA-ACK being active, it is also an output bus except when programmed for the physical demultiplexed DMA mode. In this case it becomes an input to receive the 8 most significant bits of the DMA physical address for use in the BPU function. IB0 - IB15 Information Bus An active HIGH bi-directional time multiplexed address/data bus. IB0 is the most significant bit. EDC0 - EDC5 Detection/Correction Bus An active HIGH bi-directional bus used for detection of errors on the data bus (IB0 - IB15) and correction of single errors. When working in parity mode EDC0 is the parity bit. EDC0 - EDC5 are undefined in this case. Document # MICRO-8 REV B Page 11 of 17 PACE1753/SOS PIN FUNCTIONS (Continued) Symbol Name Description MEM PRT ERR Memory Protect Error An active LOW output generated by the MMU or BPU blocks to signal to the CPU a protected memory violation. The error is generated in one of the following conditions: a mismatch in the access keys in the MMU page, an access to an execution protected page during instruction cycles, an access to a write-protected page during data cycles, or an access to a page write-protected by the BPU. MEM PAR ERR Memory Parity Error An active LOW output which signals to the CPU an error on the data bus during a memory cycle. Two detection modes can be selected by programming the control register: EDAC mode (6 Hamming code parity bits) or single bit parity mode (even or odd parity). The signal is inactive when none of the above modes are selected (default after Reset). EXT ADR ERR External Address Error An active LOW output which signals to the CPU an unimplemented memory or illegal I/O access. SING ERR Single Error An active HIGH output to signal detection of a single error on the data bus in memory cycles. It is high impedance when the EDAC function is disabled by the program (default state after Reset). RAM DIS RAM-Disable An active HIGH input from the P1754 device which enables the corrected data on the data bus when the EDAC function is enabled. An internal one clock delay is generated before the data is output on the bus to allow external memory to disconnect itself from the bus. EX RDY Data Ready An active HIGH output that indicates that no wait states are requested. It becomes inactive for one clock (inserting one wait state) whenever a memory page different than the current one is accessed (causing a miss). RDYA Address Ready An active HIGH output that indicates that no wait states are requested when STRBA is active. Wait states are inserted when this signal becomes inactive during STRBA. Up to three wait states can be inserted by programming an internal register. Three wait states are inserted after Reset (default). WR PROT/ PROT FLAG Write Protected/ Protection Flag Either an active LOW output (following STRBD timing) during legal memory write cycles, when no protection error occurs, or an active HIGH level indicating a protection error in a write cycle. Each mode can be selected by programming the control register. Default mode after Reset is write-protected. DMA ACK DMA Acknowledge An active HIGH input from the DMA controller which indicates a DMA cycle. Used to select the DMA table in the BPU memory for protection. For example, this could allow the DMA channel to update the program which could be write-protected from the processor. In the physical DMA mode, it will cause the Extended Address Lines (EXT ADR0-7) to become inputs, providing BPU protection of the DMA transfers. Note: 1. Used for Bus Arbitration; only available on 68-lead devices. Document # MICRO-8 REV B Page 12 of 17 PACE1753/SOS Standardized Military Drawing Part Number Pyramid Semiconductor CAGE Number Pyramid Semiconductor Part Number 5962-8950501UX 3DTT2 P1753-20QLMB 5962-8950501YX 3DTT2 P1753-20QGMB 5962-8950501ZX 3DTT2 P1753-20PGMB 5962-8950502UX 3DTT2 P1753-30QLMB 5962-8950502YX 3DTT2 P1753-30QGMB 5962-8950502ZX 3DTT2 P1753-30PGMB 5962-8950503UX 3DTT2 P1753-40QLMB 5962-8950503YX 3DTT2 P1753-40QGMB 5962-8950503ZX 3DTT2 P1753-40PGMB 5962-8950504TX 3DTT2 P1753-20GMB 5962-8950504XX 3DTT2 P1753-20CMB 5962-8950505TX 3DTT2 P1753-30GMB 5962-8950505XX 3DTT2 P1753-30CMB 5962-8950506TX 3DTT2 P1753-40GMB 5962-8950506XX 3DTT2 P1753-40CMB ORDERING INFORMATION Document # MICRO-8 REV B Page 13 of 17 PACE1753/SOS CASE OUTLINE 1: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .003 .006 .010 .015 .018 .050 .060 .080 .095 .225 .570 .800 .955 mm 0.05 0.08 0.15 0.25 0.38 0.45 1.27 1.52 2.03 2.41 5.72 14.48 20.32 24.25 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched may be either notched or square. Document # MICRO-8 REV B Page 14 of 17 PACE1753/SOS CASE OUTLINE 2: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .003 .010 .015 .018 .020 .050 .570 .800 .955 1.230 mm 0.08 0.25 0.38 0.45 0.51 1.27 14.48 20.32 24.25 31.26 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched my be either notched or square (with radius). 6) Case 2 is derived from Case 1 by forming the leads to the shown gullwing configuration. Document # MICRO-8 REV B Page 15 of 17 PACE1753/SOS LEAD FORM DETAIL Symbol INCHES Min Max A 0.048 A1 0.011 0.031 B 0.016 0.021 C 0.004 0.008 e1 0.090 0.050 BSC D 1.210 1.250 D1 0.945 0.965 D2 0.800 BSC E 1.210 1.250 E1 0.945 0.965 E2 L* 0.800 BSC 0.270 Nominal L0 0.120 0.210 L3 0.040 0.050 L4 0.086 0.109 R1 0.018 0.020 R2 Φ1 0.018 0.020 4° 8° Φ2 A0** -1° 7° 0.141 * Lead length in the straight lead configuration, prior to leadforming (used for all test and in-process WIP operations). ** Measured from the highest of the top of the leads or the top of the lid. Document # MICRO-8 REV B Page 16 of 17 PACE1753/SOS REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: MICRO-8 PACE1753/SOS CMOS MMU/COMBO REV. ISSUE DATE ORIG. OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-created electronic version Document # MICRO-8 REV B DESCRIPTION OF CHANGE Page 17 of 17