PD - 95130
Advanced Process Technology
Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
Description
IRF540NSPbF
IRF540NLPbF
l
HEXFET® Power MOSFET
l
D
RDS(on) = 44mΩ
G
Advanced HEXFET ® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable
device for use in a wide variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0W in a typical surface mount application.
The through-hole version (IRF540NL) is available for lowprofile applications.
VDSS = 100V
ID = 33A
S
D2 Pak
IRF540NSPbF
TO-262
IRF540NLPbF
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 srew
Max.
Units
33
23
110
130
0.87
± 20
16
13
7.0
-55 to + 175
A
W
W/°C
V
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount)**
Typ.
Max.
Units
–––
–––
1.15
40
°C/W
1
3/18/04
IRF540NS/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
∆V(BR)DSS/∆TJ
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
EAS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Single Pulse Avalanche Energy
IGSS
Min. Typ. Max. Units
Conditions
100 ––– –––
V
VGS = 0V, ID = 250µA
––– 0.12 ––– V/°C Reference to 25°C, I D = 1mA
––– ––– 44
mΩ VGS = 10V, ID = 16A
2.0
––– 4.0
V
VDS = VGS, ID = 250µA
21
––– –––
S
VDS = 50V, ID = 16A
––– ––– 25
VDS = 100V, VGS = 0V
µA
––– ––– 250
VDS = 80V, VGS = 0V, TJ = 150°C
––– ––– 100
VGS = 20V
nA
––– ––– -100
VGS = -20V
––– ––– 71
ID = 16A
––– ––– 14
nC
VDS = 80V
––– –––
21
VGS = 10V, See Fig. 6 and 13
–––
11 –––
VDD = 50V
–––
35 –––
ID = 16A
ns
–––
39 –––
RG = 5.1Ω
–––
35 –––
VGS = 10V, See Fig. 10
D
Between lead,
4.5 –––
–––
6mm (0.25in.)
nH
G
from package
–––
7.5 –––
and center of die contact
S
––– 1960 –––
VGS = 0V
––– 250 –––
VDS = 25V
–––
40 –––
pF
ƒ = 1.0MHz, See Fig. 5
––– 700
185 mJ IAS = 16A, L = 1.5mH
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
33
––– –––
showing the
A
G
integral reverse
––– ––– 110
S
p-n junction diode.
––– ––– 1.2
V
TJ = 25°C, IS = 16A, VGS = 0V
––– 115 170
ns
TJ = 25°C, IF = 16A
––– 505 760
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Starting TJ = 25°C, L =1.5mH
RG = 25Ω, IAS = 16A. (See Figure 12)
ISD ≤ 16A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
This is a typical value at device destruction and represents
operation outside rated limits.
This is a calculated value limited to TJ = 175°C .
Uses IRF540N data and test conditions.
**When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniques refer to application
note #AN-994
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IRF540NS/LPbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
100
4.5V
10
20µs PULSE WIDTH
TJ = 25 °C
1
0.1
1
10
4.5V
10
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
3.5
TJ = 25 ° C
TJ = 175 ° C
V DS = 50V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
1000
VGS , Gate-to-Source Voltage (V)
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
4.0
20µs PULSE WIDTH
TJ = 175 °C
1
0.1
100
VDS , Drain-to-Source Voltage (V)
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
9.0
ID = 33A
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF540NS/LPbF
3000
VGS , Gate-to-Source Voltage (V)
2500
C, Capacitance (pF)
20
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Ciss
2000
1500
1000
Coss
500
ID = 16A
VDS = 80V
VDS = 50V
VDS = 20V
16
12
8
4
Crss
0
1
10
0
100
FOR TEST CIRCUIT
SEE FIGURE 13
0
60
80
1000
ID, Drain-to-Source Current (A)
1000
ISD , Reverse Drain Current (A)
40
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100
TJ = 175 ° C
10
TJ = 25 ° C
1
0.1
0.2
20
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
V GS = 0 V
0.6
1.0
1.4
VSD ,Source-to-Drain Voltage (V)
1.8
100µsec
10
1msec
1
T A = 25°C
10msec
T J = 175°C
Single Pulse
0.1
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
Fig 8. Maximum Safe Operating Area
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IRF540NS/LPbF
35
RD
VDS
ID , Drain Current (A)
30
VGS
D.U.T.
RG
25
20
+
-VDD
V GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
10
Fig 10a. Switching Time Test Circuit
VDS
5
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
P DM
0.10
0.1
0.05
0.02
0.01
0.01
0.00001
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
L
VDS
D.U.T
RG
20V
DRIVER
+
V
- DD
IAS
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
IRF540NS/LPbF
400
ID
6.5A
11.3A
BOTTOM 16A
TOP
300
200
100
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
175
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
VGS
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRF540NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For N-channel HEXFET® power MOSFETs
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7
IRF540NS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H
L OT CODE 80 2 4
AS S E M B L E D ON W W 0 2, 20 00
IN T H E AS S E M B L Y L IN E "L "
IN T E R N AT IO N AL
R E C T IF IE R
L OGO
N ote: "P " in as s em bly lin e
po s itio n in dicates "L ead-F r ee"
P AR T N U M B E R
F 5 30 S
AS S E M B L Y
L O T CO D E
D AT E C O D E
Y E AR 0 = 2 0 0 0
W E E K 02
L IN E L
OR
IN T E R N AT IO N AL
R E C T IF IE R
L OGO
AS S E M B L Y
L OT COD E
8
P AR T N U M B E R
F 530S
D AT E CO D E
P = D E S IG N AT E S L E AD -F R E E
P R O D U C T (O P T IO N AL )
Y E AR 0 = 2 0 0 0
W E E K 02
A = AS S E M B L Y S IT E CO D E
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IRF540NS/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
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PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
9
IRF540NS/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/04
10
www.irf.com
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/