IRF IRF3710LPBF

PD - 95108
IRF3710SPbF
IRF3710LPbF
l
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Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Lead-Free
HEXFET® Power MOSFET
D
VDSS = 100V
RDS(on) = 23mΩ
G
ID = 57A
S
Description
Advanced HEXFET® Power MOSFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs are well known for,
provides the designer with an extremely efficient and reliable device for use in
a wide variety of applications.
The D2Pak is a surface mount power package capable of accommodating die
sizes up to HEX-4. It provides the highest power capability and the lowest
possible on-resistance in any existing surface mount package. The D 2Pak is
suitable for high current applications because of its low internal connection
resistance and can dissipate up to 2.0W in a typical surface mount application.
The through-hole version (IRF3710L) is available for low-profile applications.
D2Pak
IRF3710SPbF
TO-262
IRF3710LPbF
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V‡
Continuous Drain Current, VGS @ 10V‡
Pulsed Drain Current ‡
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ‡
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
57
40
180
200
1.3
± 20
28
20
5.8
-55 to + 175
Units
A
W
W/°C
V
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB Mounted,steady-state)**
Typ.
Max.
Units
–––
–––
0.75
40
°C/W
1
9/16/04
IRF3710S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
100
–––
–––
2.0
32
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
EAS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Single Pulse Avalanche Energy‚‡
–––
–––
–––
–––
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Typ.
–––
0.13
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
12
58
45
47
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA‡
23
mΩ VGS = 10V, ID =28A „
4.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, ID = 28A„‡
25
VDS = 100V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
130
ID = 28A
26
nC
VDS = 80V
43
VGS = 10V, See Fig. 6 and 13‡
–––
VDD = 50V
–––
ID = 28A
ns
–––
RG = 2.5Ω
–––
VGS = 10V, See Fig. 10 „‡
Between lead,
4.5 –––
6mm (0.25in.)
nH
G
from package
7.5 –––
and center of die contact
3130 –––
VGS = 0V
410 –––
VDS = 25V
72 –––
pF
ƒ = 1.0MHz, See Fig. 5‡
1060…280† mJ IAS = 28A, L = 0.70mH
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
57
––– –––
showing the
A
G
integral reverse
––– ––– 230
S
p-n junction diode.
––– ––– 1.2
V
TJ = 25°C, IS = 28A, VGS = 0V „
––– 140 220
ns
TJ = 25°C, IF = 28A
––– 670 1010 nC
di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
‚ Starting TJ = 25°C, L = 0.70mH, RG = 25Ω,
IAS = 28A, VGS=10V. (See Figure 12).
ƒ ISD ≤ 28A, di/dt ≤ 380A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
… This is a typical value at device destruction and represents
operation outside rated limits.
† This is a calculated value limited to TJ = 175°C .
‡ Uses IRF3710 data and test conditions.
**When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniques refer to application
note #AN-994.
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IRF3710S/LPbF
1000
1000
VGS
16V
10V
7.0V
6.0V
5.0V
4.5V
4.0V
BOTTOM 3.5V
100
VGS
16V
10V
7.0V
6.0V
5.0V
4.5V
4.0V
BOTTOM 3.5V
TOP
10
3.5V
1
20µs PULSE WIDTH
Tj = 25°C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
0.1
10
3.5V
1
20µs PULSE WIDTH
Tj = 175°C
0.1
0.1
1
10
100
0.1
1
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
Fig 2. Typical Output Characteristics
1000.00
3.0
I D = 57A
2.5
R DS(on) , Drain-to-Source On Resistance
100.00
T J = 175°C
10.00
T J = 25°C
1.00
VDS = 15V
20µs PULSE WIDTH
0.10
3.0
4.0
5.0
6.0
7.0
8.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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9.0
2.0
(Normalized)
ID, Drain-to-Source Current (Α )
10
VDS, Drain-to-Source Voltage (V)
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF3710S/LPbF
100000
Ciss
1000
Coss
Crss
100
ID = 28A
10
7
5
2
0
1
10
0
100
20
60
80
100
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
ID, Drain-to-Source Current (A)
1000.00
ISD, Reverse Drain Current (A)
40
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
100.00
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
TJ = 175°C
10.00
T J = 25°C
1.00
100µsec
10
1msec
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.10
0.1
0.0
0.5
1.0
1.5
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS = 80V
VDS = 50V
VDS = 20V
10
VGS , Gate-to-Source Voltage (V)
Coss = Cds + Cgd
10000
C, Capacitance(pF)
12
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
2.0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF3710S/LPbF
60
RD
VDS
VGS
50
D.U.T.
RG
+
-VDD
I D , Drain Current (A)
40
V GS
30
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
20
Fig 10a. Switching Time Test Circuit
VDS
10
90%
0
25
50
75
100
TC , Case Temperature
125
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
1
(Z thJC)
D = 0.50
Thermal Response
0.20
0.1
0.10
P DM
0.05
0.02
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
0.01
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+TC
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3710S/LPbF
550
ID
15V
TOP
D.U.T
RG
20V
VGS
IAS
440
DRIVER
+
V
- DD
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
L
VDS
11A
20A
28A
BOTTOM
330
220
110
0
25
50
75
100
125
150
175
( °C)
Starting T , Junction
Temperature
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
VGS
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRF3710S/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
‚
-
-
„
+

RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For N-channel HEXFET® power MOSFETs
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7
IRF3710S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H
L O T CO D E 8 0 2 4
AS S E M B L E D O N W W 0 2 , 2 0 0 0
IN T H E AS S E M B L Y L IN E "L "
IN T E R N AT IO N AL
R E CT IF IE R
L O GO
N ote: "P " in as s em bly lin e
po s i tion in dicates "L ead-F r ee"
P AR T N U M B E R
F 53 0 S
AS S E M B L Y
L O T CO D E
D AT E CO D E
Y E AR 0 = 2 0 0 0
W E E K 02
L IN E L
OR
IN T E R N AT IO N AL
R E C T IF IE R
L OG O
AS S E M B L Y
L OT CO D E
8
P AR T N U M B E R
F 530 S
D AT E C O D E
P = D E S IGN AT E S L E AD -F R E E
P R O D U C T (O P T IO N AL )
Y E AR 0 = 2 0 0 0
WE E K 02
A = AS S E M B L Y S IT E C O D E
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IRF3710S/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
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PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
9
IRF3710S/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/04
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/