AD ADV7619KSVZ

Dual Port, Xpressview,
3 GHz HDMI Receiver
ADV7619
Data Sheet
FEATURES
Advanced audio mute feature
Dedicated, flexible audio output port
Super Audio CD® (SACD) with DSD output interface
HBR audio
Dolby® TrueHD
DTS-HD Master Audio™
General
Interrupt controller with 2 interrupt outputs
Standard identification (STDI) circuit
Highly flexible, 48-bit pixel output interface
36-bit output for resolutions up to 1080p Deep Color
2 × 24-bit pass-through outputs for HDMI formats
greater than 2.25 GHz
Internal EDID RAM
Any-to-any, 3 × 3 color space conversion (CSC) matrix
128-lead TQFP_EP, 14 mm × 14 mm package
High-Definition Multimedia Interface (HDMI®) 1.4a features
supported
All mandatory and additional 3D video formats supported
Extended colorimetry, including sYCC601, Adobe® RGB,
Adobe YCC601, xvYCC extended gamut color
CEC 1.4-compatible
HDMI 3 GHz receiver
297 MHz maximum TMDS clock frequency
Supports 4k × 2k resolution
Xpressview fast switching of HDMI ports
Up to 48-bit Deep Color with 36-/30-/24-bit support
High-bandwidth Digital Content Protection (HDCP) 1.4
support with internal HDCP keys
HDCP repeater support: up to 127 KSVs supported
Integrated CEC controller
Programmable HDMI equalizer
5 V detect and Hot Plug assert for each HDMI port
Audio support
Audio support including high bit rate (HBR) and
Direct Stream Digital (DSD)
S/PDIF (IEC 60958-compatible) digital audio support
Supports up to four I2S outputs
APPLICATIONS
Projectors
Video conferencing
HDTV
AVR, HTiB
Soundbar
Video switch
FUNCTIONAL BLOCK DIAGRAM
ADV7619
HDCP
KEYS
HS/VS
36
TMDS
DDC
HDMI2
TMDS
FIELD/DE
CLK
HS
VS/FIELD
DE
CLK
36-/48-BIT
OUTPUT BUS
DATA
DEEP
COLOR
HDMI Rx
I2S
S/PDIF
DDC
DSD
HBR
MCLK
SCLK
LRCLK
OUTPUT MUX
HDMI1
COMPONENT
PROCESSOR
OUTPUT MUX
48
AUDIO
OUTPUT
MCLK
SCLK
09580-001
FAST
SWITCH
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADV7619
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Supply Recommendations ................................................. 13
Applications ....................................................................................... 1
Power-Up Sequence ................................................................... 13
Functional Block Diagram .............................................................. 1
Power-Down Sequence .............................................................. 13
Revision History ............................................................................... 2
Current Rating Requirements for Power Supply Design ...... 13
General Description ......................................................................... 3
Functional Overview...................................................................... 14
Detailed Functional Block Diagram .......................................... 3
HDMI Receiver........................................................................... 14
Specifications..................................................................................... 4
Component Processor (CP) ...................................................... 14
Electrical Characteristics ............................................................. 4
Other Features ............................................................................ 14
Data and I C Timing Characteristics ......................................... 6
Pixel Input/Output Formatting .................................................... 15
Absolute Maximum Ratings............................................................ 8
Pixel Data Output Mode Features ............................................ 15
Package Thermal Performance ................................................... 8
Outline Dimensions ....................................................................... 22
ESD Caution .................................................................................. 8
Ordering Guide .......................................................................... 22
2
Pin Configuration and Function Descriptions ............................. 9
REVISION HISTORY
5/12—Rev. A to Rev. B
9/11—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to General Description Section and Figure 2 ............... 3
Change to Table 1 ............................................................................. 4
Changes to Table 3 ............................................................................ 6
Changes to Figure 5; Deleted Figure 6, Renumbered
Sequentially ....................................................................................... 7
Changes to Figure 7 .......................................................................... 9
Changes to Table 5 .......................................................................... 11
Changes to HDMI Receiver Section and Other Features
Section .............................................................................................. 14
Deleted Time-Division Multiplexed (TDM) Mode Section
and Figure 9 ..................................................................................... 15
Changes to General Description Section ......................................3
Changes to Data Output Transition Time Typ Values, Table 3 ...6
Changes to Pin 113 Description ................................................... 12
Changes to Pixel Input/Output Formatting Section .................. 16
Added Endnote 1 to Table 7 .......................................................... 17
Added Endnote 1 to Table 12 ........................................................ 22
Changes to Ordering Guide .......................................................... 23
7/11—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADV7619
GENERAL DESCRIPTION
The HDMI receiver has advanced audio functionality, such as
a mute controller, that prevents audible extraneous noise in the
audio output.
The ADV7619 is a high quality, two input, one output (2:1)
multiplexed High-Definition Multimedia Interface (HDMI®)
receiver. The ADV7619 is offered in professional (no HDCP
keys) and commercial versions. The operating temperature
range is 0°C to 70°C.
The ADV7619 contains one main component processor (CP),
which processes video signals from the HDMI receiver up to
1080p 36-bit Deep Color. It provides features such as contrast,
brightness and saturation adjustments, STDI detection block,
free-run, and synchronization alignment controls.
The ADV7619 incorporates a dual input HDMI-capable
receiver that supports all mandatory 3D TV formats defined in
the HDMI 1.4a specification, HDTV formats up to 1080p 36-bit
Deep Color/2160p 8-bit, and display resolutions up to 4k × 2k
(3840 × 2160 at 30 Hz). It integrates an HDMI CEC controller
that supports the capability discovery and control (CDC) feature.
For video formats with pixel clocks higher than 170 MHz, the
video signals received on the HDMI receiver are output directly
to the pixel port output. To accommodate the higher bandwidth
required for these higher resolutions, the output on the pixel bus
consists of two 24-bit buses running at up to 150 MHz: one bus
contains the even pixels, and the other bus contains the odd
pixels. When these two buses are combined, they allow the
transfer of video data with pixel clocks up to 300 MHz. In this
mode, both 4:4:4 RGB 8-bit and 4:2:2 12-bit are supported.
The ADV7619 incorporates Xpressview™ fast switching on both
input HDMI ports. Using the Analog Devices, Inc., hardwarebased HDCP engine to minimize software overhead, Xpressview
technology allows fast switching between both HDMI input ports
in less than 1 sec.
Each HDMI port has dedicated 5 V detect and Hot Plug™ assert
pins. The HDMI receiver also includes an integrated programmable equalizer that ensures robust operation of the interface
with long cables.
Fabricated in an advanced CMOS process, the ADV7619
is provided in a 14 mm × 14 mm, 128-lead, surface-mount,
RoHS-compliant TQFP_EP package and is specified over the
0°C to 70°C temperature range.
The ADV7619 offers a flexible audio output port for audio data
extraction from the HDMI stream. HDMI audio formats, including SACD via DSD and HBR, are supported by the ADV7619.
CS
CEC
CEC
CONTROLLER
RXA_5V
RXB_5V
HPA_A/INT2*
HPA_B
5V DETECT
AND HDP
CONTROLLER
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
EDID
REPEATER
CONTROLLER
RXA_C±
RXB_C±
RXA_0±
RXA_1±
RXA_2±
RXB_0±
RXB_1±
RXB_2±
PLLs
EQUALIZER
EQUALIZER
CONTROL
INTERFACE
I2C
BACK-END
COLOR
SPACE
CONVERSION
CONTROL AND DATA
HDCP
KEYS
HDCP
ENGINE
SAMPLER
INTERRUPT
CONTROLLER
(INT1, INT2)
HDMI
PROCESSOR
COMPONENT
PROCESSOR
A
B
C
DATA
PREPROCESSOR
AND COLOR
SPACE
CONVERSION
PACKET
PROCESSOR
PACKET/
INFOFRAME
MEMORY
SAMPLER
MUTE
AUDIO
PROCESSOR
AUDIO OUTPUT FORMATTER
SCL
SDA
300MHz VIDEO PATH
ADV7619
*INT2 CAN BE MADE AVAILABLE ON ONE OF THESE PINS: HPA_A/INT2, MCLK/INT2, OR SCLK/INT2.
Figure 2.
Rev. B | Page 3 of 24
P0 TO P11
P12 TO P23
P24 TO P35
P36 TO P47
LLC
HS
VS/FIELD/ALSB
DE
INT1
INT2*
AP1
AP2
AP3
AP4
AP5
SCLK/INT2*
MCLK/INT2*
AP0
09580-002
DPLL
Xpressview
FAST SWITCHING
XTALP
XTALN
VIDEO OUTPUT FORMATTER
DETAILED FUNCTIONAL BLOCK DIAGRAM
ADV7619
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V,
operating temperature range, unless otherwise noted.
Table 1.
Parameter
DIGITAL INPUTS 1
Input High Voltage
Symbol
Test Conditions/Comments
Min
VIH
1.2
2
Input Low Voltage
VIL
Input Current
IIN
XTALN and XTALP pins
Other digital inputs
XTALN and XTALP pins
Other digital inputs
RESET and CS pins
Other digital inputs
Input Capacitance
DIGITAL INPUTS (5 V TOLERANT)1
CIN
Input High Voltage
Input Low Voltage
Input Current
DIGITAL OUTPUTS1
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
VIH
VIL
IIN
Output Capacitance
POWER REQUIREMENTS
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Terminator Power Supply
Comparator Power Supply
CURRENT CONSUMPTION
Digital Core Power Supply
COUT
1
2
±45
±10
Max
Unit
0.4
0.8
±60
10
V
V
V
V
µA
µA
pF
0.8
+70
V
V
µA
DDCA_SCL, DDCA_SDA,
DDCB_SCL, and DDCB_SDA pins
VOH
VOL
ILEAK
2.6
−70
2.4
VS/FIELD/ALSB pin
HPA_A/INT2 and HPA_B pins
Other digital outputs
DVDD
DVDDIO
PVDD
TVDD
CVDD
IDVDD
Digital I/O Power Supply
IDVDDIO
PLL Power Supply
IPVDD
Terminator Power Supply
ITVDD
Comparator Power Supply
ICVDD
POWER-DOWN CURRENT 2
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Terminator Power Supply
Comparator Power Supply
POWER-UP TIME
Typ
±35
IDVDD_PD
IDVDDIO_PD
IPVDD_PD
ITVDD_PD
ICVDD_PD
tPWRUP
Data guaranteed by characterization.
Data recorded during lab characterization.
Rev. B | Page 4 of 24
1.89
3.46
1.89
3.46
1.89
V
V
V
V
V
±10
1.71
3.14
1.71
3.14
1.71
See Table 2
Test Condition 1
Test Condition 2
Test Condition 1
Test Condition 2
Test Condition 1
Test Condition 2
Test Condition 1
Test Condition 2
Test Condition 1
Test Condition 2
See Table 2, Test Condition 3
20
V
V
µA
µA
µA
pF
0.4
±60
±70
1.8
3.3
1.8
3.3
1.8
268
186
9
10
20
31
92
92
187
166
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1.07
0.034
0.691
0.857
0.053
25
mA
mA
mA
mA
mA
ms
Data Sheet
ADV7619
Table 2. Test Conditions for Current Requirements
Parameter
TEST CONDITION 1
Number of HDMI Inputs (Xpressview Mode)
Xpressview
Video Format (Each HDMI Input)
HDCP Decryption
Video Pattern (Each HDMI Input)
Temperature
Power Supply Voltages
TEST CONDITION 2
Number of HDMI Inputs (Xpressview Mode)
Xpressview
Video Format (Each HDMI Input)
HDCP Decryption
Video Pattern (Each HDMI Input)
Temperature
Power Supply Voltages
TEST CONDITION 3 (POWER-DOWN)
Number of HDMI Inputs (Xpressview Mode)
Xpressview
Video Format (Each HDMI Input)
HDCP Decryption
Video Pattern (Each HDMI Input)
Temperature
Power Supply Voltages
Other Test Parameters
1
Value Used
Two inputs
On
4k × 2k
Off
SMPTE
20°C
Nominal
Two inputs
On
1080p60, 36 bits
Off
SMPTE
20°C
Nominal
N/A
N/A
N/A
N/A
N/A
20°C
Nominal
Power-Down Mode 0 (IO map, Register 0x0C = 0x62)
Ring oscillator powered down (HDMI map, Register 0x48 = 0x01)
DDC pads powered off (HDMI map, Register 0x73 = 0x03) 1
For information about these registers, see the Hardware User Guide for the ADV7619 (UG-237).
Rev. B | Page 5 of 24
ADV7619
Data Sheet
DATA AND I2C TIMING CHARACTERISTICS
Table 3.
Parameter
CLOCK AND CRYSTAL
Crystal Frequency, XTAL
Crystal Frequency Stability
LLC Frequency Range
I2C PORTS
SCL Frequency
SCL Minimum Pulse Width High1
SCL Minimum Pulse Width Low1
Start Condition Hold Time1
Start Condition Setup Time1
SDA Setup Time1
SCL and SDA Rise Time1
SCL and SDA Fall Time1
Stop Condition Setup Time1
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark-Space Ratio1
DATA AND CONTROL OUTPUTS1, 2
Data Output Transition Time
Symbol
Typ
13.5
Max
Unit
±50
170
MHz
ppm
MHz
400
t1
t2
t3
t4
t5
t6
t7
t8
0.6
kHz
ns
μs
ns
ns
ns
ns
ns
μs
5
ms
600
1.3
600
600
100
300
300
t9:t10
I2Sx Data Transition Time
2
Min
28.63636
I2S PORT, MASTER MODE1
SCLK Mark-Space Ratio
LRCLK Data Transition Time
1
Test Conditions/Comments
45:55
t11
t12
End of valid data to negative LLC edge
Negative LLC edge to start of valid data
t15:t16
t17
t18
t19
t20
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
55:45
1.0
0.1
ns
ns
45:55
55:45
10
10
5
5
Data guaranteed by characterization.
DLL bypassed on clock path.
Timing Diagrams
t3
t5
t3
SDA
t6
t1
t7
t4
2
Figure 3. I C Timing
Rev. B | Page 6 of 24
t8
09580-003
SCL
t2
% duty cycle
% duty cycle
ns
ns
ns
ns
Data Sheet
ADV7619
t9
t10
LLC
t11
09580-004
t12
P0 TO P47, HS,
VS/FIELD/ALSB, DE
Figure 4. Pixel Port and Control SDR Output Timing
t15
SCLK
t16
t17
LRCLK
t18
t19
MSB
MSB – 1
t20
I2Sx
I2S MODE
t19
MSB
MSB – 1
t20
I2Sx
RIGHT-JUSTIFIED
MODE
t19
MSB
NOTES
1. THE LRCLK SIGNAL IS AVAILABLE ON THE AP5 PIN.
2. I2Sx SIGNALS (WHERE x = 0, 1, 2, OR 3) ARE AVAILABLE
ON THE FOLLOWING PINS: AP1, AP2, AP3, AND AP4.
Figure 5. I2S Timing
Rev. B | Page 7 of 24
LSB
t20
09580-005
I2Sx
LEFT-JUSTIFIED
MODE
ADV7619
Data Sheet
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL PERFORMANCE
Table 4.
Parameter
DVDD to GND
PVDD to GND
DVDDIO to GND
CVDD to GND
TVDD to GND
Digital Inputs to GND
5 V Tolerant Digital Inputs
to GND1
Digital Outputs to GND
XTALP, XTALN
SCL, SDA Data Pins to
DVDDIO
Maximum Junction
Temperature (TJ MAX)
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
1
Rating
2.2 V
2.2 V
4.0 V
2.2 V
4.0 V
GND − 0.3 V to DVDDIO + 0.3 V
5.3 V
To reduce power consumption when using the ADV7619, the
user is advised to turn off the unused sections of the part.
GND − 0.3 V to DVDDIO + 0.3 V
−0.3 V to PVDD + 0.3 V
DVDDIO − 0.3 V to DVDDIO + 3.6 V
The maximum junction temperature (TJ MAX) of 125°C must not
be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on the device under
test (DUT):
125°C
Due to PCB metal variation and, therefore, variation in PCB
heat conductivity, the value of θJA may differ for various PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this solution eliminates the variance associated with
the θJA value.
TJ = TS + (ΨJT × WTOTAL)
−60°C to +150°C
260°
where:
TS is the package surface temperature (°C).
ΨJT = 0.22°C/W for the 128-lead TQFP_EP.
The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,
DDCA_SDA, DDCB_SCL, and DDCB_SDA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
WTOTAL = ((PVDD × IPVDD) + (0.2 × TVDD × ITVDD) +
(CVDD × ICVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO))
where 0.2 is 20% of the TVDD power that is dissipated on the
part itself.
ESD CAUTION
Rev. B | Page 8 of 24
Data Sheet
ADV7619
AP0
NC
NC
NC
100
99
98
97
GND
1
CVDD
2
RXA_C–
3
94
HS
RXA_C+
4
93
DE
DVDDIO
PIN 1
96
NC
95
VS/FIELD/ALSB
TVDD
5
92
RXA_0–
6
91
P0
RXA_0+
7
90
P1
P2
TVDD
8
89
RXA_1–
9
88
P3
RXA_1+
10
87
P4
TVDD
11
86
P5
RXA_2–
12
85
P6
RXA_2+
13
84
P7
CVDD
14
83
P8
GND
15
TEST1
16
ADV7619
TOP VIEW
(Not to Scale)
82
P9
81
P10
80
P11
DVDD
17
TEST2
18
79
DVDD
CVDD
19
78
P12
DVDDIO
RXB_C–
20
77
RXB_C+
21
76
P13
TVDD
22
75
P14
P15
RXB_0–
23
74
RXB_0+
24
73
P16
TVDD
25
72
P17
RXB_1–
26
71
P18
RXB_1+
27
70
P19
P20
TVDD
28
69
RXB_2–
29
68
P21
RXB_2+
30
67
P22
62
63
64
DVDD
DVDD
P25
61
60
P26
P24
59
P27
LLC
57
58
P28
55
54
P31
56
53
DVDD
Rev. B | Page 9 of 24
P29
52
DVDDIO
Figure 6. Pin Configuration
P30
50
51
P32
45
P38
P33
44
P39
49
43
P40
P34
42
P41
48
41
P42
P35
40
P43
DVDDIO
47
39
P44
46
38
P45
P36
37
P46
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. CONNECT THE EXPOSED PAD (PIN 0) ON THE BOTTOM
OF THE PACKAGE TO GROUND.
P37
35
36
P47
DVDDIO
33
P23
65
34
66
32
NC
31
GND
DVDD
CVDD
09580-008
AP2
AP1
102
101
AP4
AP3
104
105
103
AP5
SCLK/INT2
106
DVDD
SDA
109
MCLK/INT2
SCL
110
107
INT1
111
108
CS
RESET
PVDD
114
112
XTALP
115
113
DVDD
XTALN
117
116
DDCB_SCL
DDCB_SDA
CEC
HPA_B
120
118
RXB_5V
122
121
119
DDCA_SDA
DDCA_SCL
HPA_A/INT2
126
125
123
RXA_5V
127
124
NC
NC
128
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7619
Data Sheet
Table 5. Pin Function Descriptions
Pin No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Mnemonic
GND
GND
CVDD
RXA_C−
RXA_C+
TVDD
RXA_0−
RXA_0+
TVDD
RXA_1−
RXA_1+
TVDD
RXA_2−
RXA_2+
CVDD
GND
TEST1
DVDD
TEST2
CVDD
RXB_C−
RXB_C+
TVDD
RXB_0−
RXB_0+
TVDD
RXB_1−
RXB_1+
TVDD
RXB_2−
RXB_2+
CVDD
GND
NC
DVDD
P47
P46
P45
P44
P43
DVDDIO
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
Type
Ground
Ground
Power
HDMI input
HDMI input
Power
HDMI input
HDMI input
Power
HDMI input
HDMI input
Power
HDMI input
HDMI input
Power
Ground
Test
Power
Test
Power
HDMI input
HDMI input
Power
HDMI input
HDMI input
Power
HDMI input
HDMI input
Power
HDMI input
HDMI input
Power
Ground
No connect
Power
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Power
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Description
Ground. Connect the exposed pad (Pin 0) on the bottom of the package to ground.
Ground.
HDMI Analog Block Supply Voltage (1.8 V).
Digital Input Clock Complement of Port A in the HDMI Interface.
Digital Input Clock True of Port A in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
Digital Input Channel 0 True of Port A in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
Digital Input Channel 1 Complement of Port A in the HDMI Interface.
Digital Input Channel 1 True of Port A in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
Digital Input Channel 2 True of Port A in the HDMI Interface.
HDMI Analog Block Supply Voltage (1.8 V).
Ground.
This pin must be left floating.
Digital Core Supply Voltage (1.8 V).
This pin must be left floating.
HDMI Analog Block Supply Voltage (1.8 V).
Digital Input Clock Complement of Port B in the HDMI Interface.
Digital Input Clock True of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
Digital Input Channel 0 Complement of Port B in the HDMI Interface.
Digital Input Channel 0 True of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
Digital Input Channel 1 Complement of Port B in the HDMI Interface.
Digital Input Channel 1 True of Port B in the HDMI Interface.
Terminator Supply Voltage (3.3 V).
Digital Input Channel 2 Complement of Port B in the HDMI Interface.
Digital Input Channel 2 True of Port B in the HDMI Interface.
HDMI Analog Block Supply Voltage (1.8 V).
Ground.
No Connect. Do not connect to this pin.
Digital Core Supply Voltage (1.8 V).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Rev. B | Page 10 of 24
Data Sheet
ADV7619
Pin No.
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Mnemonic
DVDDIO
DVDD
P31
P30
P29
P28
P27
P26
P25
P24
LLC
DVDD
DVDD
DVDDIO
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
DVDDIO
P12
DVDD
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
DVDDIO
DE
HS
VS/FIELD/ALSB
Type
Power
Power
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Power
Power
Power
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Power
Digital video output
Power
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Digital video output
Power
Miscellaneous digital
Digital video output
Digital video output
96
97
98
99
100
NC
NC
NC
NC
AP0
No connect
No connect
No connect
No connect
Miscellaneous
101
AP1
Miscellaneous
Description
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Pixel Output Clock for the Pixel Data. The range is from 13.5 MHz to 170 MHz.
Digital Core Supply Voltage (1.8 V).
Digital Core Supply Voltage (1.8 V).
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port.
Digital Core Supply Voltage (1.8 V).
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V).
Data Enable. The DE signal indicates active pixel data.
Horizontal Synchronization Output Signal.
VS is a vertical synchronization output signal. FIELD is a field synchronization output
signal in all interlaced video modes. ALSB allows selection of the I2C address.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit
rate (HBR), or Direct Stream Digital® (DSD®).
Audio Output Pin/TDM I2S Output. This pin can be configured to output S/PDIF digital
audio, high bit rate (HBR), Direct Stream Digital (DSD).
Rev. B | Page 11 of 24
ADV7619
Data Sheet
Pin No.
102
Mnemonic
AP2
Type
Miscellaneous
103
AP3
Miscellaneous
104
AP4
Miscellaneous
105
SCLK/INT2
Miscellaneous digital
106
AP5
Miscellaneous
107
MCLK/INT2
Miscellaneous digital
108
109
110
111
DVDD
SDA
SCL
INT1
Power
Miscellaneous digital
Miscellaneous digital
Miscellaneous digital
112
RESET
Miscellaneous digital
113
CS
Miscellaneous digital
114
115
PVDD
XTALP
Power
Miscellaneous
116
117
118
119
120
121
122
123
124
125
XTALN
DVDD
CEC
DDCB_SCL
DDCB_SDA
HPA_B
RXB_5V
DDCA_SCL
DDCA_SDA
HPA_A/INT2
Miscellaneous
Power
Digital input/output
HDMI input
HDMI input
Miscellaneous digital
HDMI input
HDMI input
HDMI input
Miscellaneous digital
126
127
128
RXA_5V
NC
NC
HDMI input
No connect
No connect
Description
Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit
rate (HBR), Direct Stream Digital (DSD), or I2S.
Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit
rate (HBR), Direct Stream Digital (DSD), or I2S.
Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit
rate (HBR), Direct Stream Digital (DSD), or I2S.
Serial Clock/Interrupt 2. This dual-function pin can be configured to output the audio
serial clock or an Interrupt 2 signal.
Audio Output Pin. This pin can be configured to output S/PDIF digital audio, high bit
rate (HBR), or Direct Stream Digital (DSD). Pin AP5 is typically used to provide the
LRCLK for I2S modes.
Master Clock/Interrupt 2. This dual-function pin can be configured to output the audio
master clock or an Interrupt 2 signal.
Digital Core Supply Voltage (1.8 V).
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
I2C Port Serial Clock Input. SCL is the clock line for the control port.
Interrupt. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are user configurable.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7619 circuitry.
Chip Select. This pin has an internal pull-down. Pulling this line up causes I2C state
machine to ignore I2C transmission.
PLL Supply Voltage (1.8 V).
Input Pin for 28.63636 MHz Crystal or External 1.8 V, 28.63636 MHz Clock Oscillator
Source to Clock the ADV7619.
Crystal Input. Input pin for 28.63636 MHz crystal.
Digital Core Supply Voltage (1.8 V).
Consumer Electronics Control Channel.
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.
Hot Plug Assert Signal Output for HDMI Port B.
5 V Detect Pin for Port B in the HDMI Interface.
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
Hot Plug Assert/Interrupt 2. This dual-function pin can be configured to output the
Hot Plug assert signal for HDMI Port A or an Interrupt 2 signal.
5 V Detect Pin for Port A in the HDMI Interface.
No Connect. Do not connect to this pin.
No Connect. Do not connect to this pin.
Rev. B | Page 12 of 24
Data Sheet
ADV7619
POWER SUPPLY RECOMMENDATIONS
POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
The recommended power-up sequence for the ADV7619 is to
power up the 3.3 V supplies first, followed by the 1.8 V supplies.
RESET should be held low while the supplies are powered up.
The ADV7619 supplies can be deasserted simultaneously as long
as a higher rated supply does not go below a lower rated supply.
Alternatively, the ADV7619 can be powered up by asserting all
supplies simultaneously. In this case, care must be taken while
the supplies are being established to ensure that a lower rated
supply does not go above a higher rated supply level.
3.3V SUPPLIES
3.3V SUPPLIES
POWER-UP
1.8V SUPPLIES
POWER-UP
Table 6. Current Rating Requirements for Power Supply Design
Parameter
IDVDD
IDVDDIO
IPVDD
ITVDD
ICVDD
1.8V SUPPLIES
1.8V
Table 6 shows the current rating requirements for power supply
design.
09580-007
POWER SUPPLY (V)
3.3V
CURRENT RATING REQUIREMENTS FOR POWER
SUPPLY DESIGN
Figure 7. Recommended Power-Up Sequence
Rev. B | Page 13 of 24
Current Rating (mA)
400
300
50
120
250
ADV7619
Data Sheet
FUNCTIONAL OVERVIEW
HDMI RECEIVER
•
The HDMI receiver supports all mandatory and many optional
3D video formats defined in the HDMI 1.4a specification, HDTV
formats up to 2160p, and all display resolutions up to 4k × 2k
(3840 × 2160 at 30 Hz).
COMPONENT PROCESSOR (CP)
With the inclusion of HDCP, displays can now receive encrypted
video content. The HDMI interface of the ADV7619 allows for
authentication of a video receiver, decryption of encoded data at
the receiver, and renewability of that authentication during transmission, as specified by the HDCP 1.4 specification.
The HDMI-compatible receiver on the ADV7619 allows active
equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI
cabling, especially at longer cable lengths and higher frequencies.
The HDMI-compatible receiver is capable of equalizing for cable
lengths up to 30 meters to achieve robust receiver performance.
The ADV7619 also supports TERC4 error detection, which is
used for detection of corrupted HDMI packets following a cable
disconnect.
The HDMI receiver offers advanced audio functionality. The
receiver contains an audio mute controller that can detect a variety
of conditions that may result in audible extraneous noise in the
audio output. Upon detection of these conditions, the audio signal
can be ramped down or muted to prevent audio clicks or pops.
The HDMI receiver supports the reception of all types of audio
data described in the HDMI specifications, including
•
•
•
•
LPCM (uncompressed audio)
IEC 61937 (compressed audio)
DSD audio (1-bit audio)
HBR audio (high bit rate compressed audio)
•
•
•
•
•
•
The ADV7619 has two any-to-any, 3 × 3 color space conversion
(CSC) matrices. The first CSC block is placed in front of the CP
section. The second CSC block is placed at the back of the CP
section. Each CSC enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standards of color space can be implemented using the color space converters.
The CP block is available only for video signals with resolution
up to 1080p Deep Color (pixel rates up to 170 MHz). For resolutions higher than 1080p, the video signal bypasses the CP block
and is routed directly to the pixel bus output as two 24-bit (4:4:4)
buses running at up to 150 MHz.
CP features include
•
•
•
•
•
•
•
Support for 525i, 625i, 525p, 625p, 720p, 1080i, 1080p,
and many other HDTV formats
Manual adjustments including gain (contrast), offset
(brightness), hue, and saturation
Free-run output mode that provides stable timing when
no video input is present
170 MHz conversion rate, which supports RGB input
resolutions up to 1600 × 1200 at 60 Hz
Standard identification enabled by STDI block
RGB that can be color space converted to YCrCb and
decimated to a 4:2:2 format for video-centric, back-end
IC interfacing
Data enable (DE) output signal supplied for direct
connection to HDMI/DVI transmitter
OTHER FEATURES
Xpressview fast switching can be implemented with full HDCP
authentication available on the background port. Synchronization measurement and status information are available for all
HDMI inputs. HDMI receiver features include
•
•
•
•
•
•
CEC controller
2:1 multiplexed HDMI receiver
3D format support
297 MHz HDMI receiver
Support for 4k × 2k resolutions
Integrated equalizer for cable lengths up to 30 meters
High-bandwidth Digital Content Protection (HDCP 1.4)
(on background ports, also)
Internal HDCP keys
36-/30-bit Deep Color support (resolutions up to 1080p)
Audio sample, HBR, DSD packet support
Repeater support
Internal EDID RAM
Hot Plug assert output pin for each HDMI port
The ADV7619 has HS, VS, FIELD, and DE output signals with
programmable position, polarity, and width.
The ADV7619 has two programmable interrupt request output
pins: INT1 and INT2 (INT2 is accessible via one of the following
pins: MCLK/INT2, SCLK/INT2, or HPA_A/INT2). The ADV7619
also features a low power power-down mode.
The main I2C address can be set to 0x98 or 0x9A. On power-up or
after a reset, the I2C address is set to 0x98 by default. The address
can be changed to 0x9A by pulling up the VS/FIELD/ALSB pin
and issuing the I2C command SAMPLE_ALSB. For more information, see the Register Access and Serial Ports Description
section in the UG-237.
The ADV7619 is provided in a 128-lead, 14 mm × 14 mm,
RoHS-compliant TQFP_EP package and is specified over the
0°C to 70°C temperature range.
Rev. B | Page 14 of 24
Data Sheet
ADV7619
PIXEL INPUT/OUTPUT FORMATTING
The output section of the ADV7619 is highly flexible. The pixel
output bus can support up to 36-bit 4:4:4 YCrCb or 36-bit 4:4:4
RGB. For resolutions higher than 1080p, the pixel output bus
supports two 24-bit 4:4:4 RGB/YCrCb.
Part supports SDR (single data rate) and double data rate
(DDR) outputs. SDR is supported up to 170 MHz LLC
frequency (UXGA, 1080p60 for any OP_FORMAT_SEL or
up to 300 MHz HDMI signals output on two 24-bit parallel
video sub buses OP_FORMAT_SEL = 0x94, 0x95, 0x96, or
0x54; refer to Table 12). DDR can be supported with LLC clock
frequency up to 50 MHz (video modes with original pixel clock
lower than 100 MHz, such as 1080i60). In SDR mode, 16-/20-/
24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In DDR
mode, the pixel output port can be configured for 4:2:2 YCrCb
or 4:4:4 RGB for data rates up to 27 MHz.
PIXEL DATA OUTPUT MODE FEATURES
For resolutions up to 1080p Deep Color, the output pixel port
features include the following:
•
•
•
•
•
SDR 8-/10-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD output signals
SDR 16-/20-/24-bit 4:2:2 YCrCb with embedded time codes
and/or HS and VS/FIELD pin timing
SDR 24-/30-/36-bit 4:4:4 YCrCb/RGB with embedded time
codes and/or HS and VS/FIELD pin timing
DDR 8-/10-/12-bit 4:2:2 YCrCb for data rates up to 27 MHz
DDR 12-/24-/30-/36-bit 4:4:4 RGB for data rates up to
27 MHz
Bus rotation is supported.
For resolutions greater than 1080p Deep Color (direct passthrough of video signal), the output pixel port features include
the following:
Table 7 through Table 12 provide the different output formats
that are supported. All output modes are controlled via I2C.
•
•
For resolutions higher than 1080p, the video signals are routed
directly to the pixel bus output as two 24-bit (4:4:4) buses running
at up to 150 MHz. In this mode, the output data format is the
same as the input format.
Rev. B | Page 15 of 24
8-bit 4:4:4 RGB/YCrCb for resolutions up to 2160p
12-bit 4:2:2 RGB/YCrCb for resolutions up to 2160p
ADV7619
Data Sheet
Table 7. SDR 4:2:2 Output Modes (8-/10-/12-Bit) 1
Pixel Output
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
1
0x00
8-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0x01
10-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
SDR 4:2:2—OP_FORMAT_SEL[7:0] =
0x02
0x06
12-Bit SDR
12-Bit SDR
ITU-R BT.656
ITU-R BT.656
Mode 0
Mode 1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y1, Cb1, Cr1
High-Z
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y11, Cb11, Cr11
Y11, Cb11, Cr11
Y10, Cb10, Cr10
Y10, Cb10, Cr10
Y9, Cb9, Cr9
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y2, Cb2, Cr2
Y1, Cb1, Cr1
High-Z
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Modes require additional writes to IO map Register 0x19 (Bits[7:6] should be set to 2'b11) and IO map Register 0x33 (Bit[6] should be set to 1).
Rev. B | Page 16 of 24
0x0A
12-Bit SDR
ITU-R BT.656
Mode 2
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y11, Cb11, Cr11
Y10, Cb10, Cr10
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Data Sheet
ADV7619
Table 8. SDR 4:2:2 Output Modes (16-/20-/24-Bit)
Pixel Output
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
0x80
16-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
High-Z
High-Z
High-Z
High-Z
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
0x81
20-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
High-Z
High-Z
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
High-Z
High-Z
SDR 4:2:2—OP_FORMAT_SEL[7:0] =
0x82
0x86
24-Bit SDR
24-Bit SDR
ITU-R BT.656
ITU-R BT.656
Mode 0
Mode 1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Cb1, Cr1
High-Z
Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
Y1
High-Z
Y0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y11
Y11
Y10
Y10
Y9
Y9
Y8
Y8
Y7
Y7
Y6
Y6
Y5
Y5
Y4
Y4
Y3
Y3
Y2
Y2
Y1
High-Z
Y0
High-Z
Cb11, Cr11
Cb11, Cr11
Cb10, Cr10
Cb10, Cr10
Cb9, Cr9
Cb9, Cr9
Cb8, Cr8
Cb8, Cr8
Cb7, Cr7
Cb7, Cr7
Cb6, Cr6
Cb6, Cr6
Cb5, Cr5
Cb5, Cr5
Cb4, Cr4
Cb4, Cr4
Cb3, Cr3
Cb3, Cr3
Cb2, Cr2
Cb2, Cr2
Cb1, Cr1
High-Z
Cb0, Cr0
High-Z
Rev. B | Page 17 of 24
0x8A
24-Bit SDR
ITU-R BT.656
Mode 2
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y3
Y2
Y1
Y0
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
High-Z
High-Z
High-Z
High-Z
Cb11, Cr11
Cb10, Cr10
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
High-Z
High-Z
High-Z
High-Z
ADV7619
Data Sheet
Table 9. SDR 4:4:4 Output Modes
Pixel Output
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
0x40
24-Bit SDR
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
R7
R6
R5
R4
R3
R2
R1
R0
High-Z
High-Z
High-Z
High-Z
G7
G6
G5
G4
G3
G2
G1
G0
High-Z
High-Z
High-Z
High-Z
B7
B6
B5
B4
B3
B2
B1
B0
High-Z
High-Z
High-Z
High-Z
SDR 4:4:4—OP_FORMAT_SEL[7:0] =
0x41
0x42
30-Bit SDR
36-Bit SDR
Mode 0
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
R9
R11
R8
R10
R7
R9
R6
R8
R5
R7
R4
R6
R3
R5
R2
R4
R1
R3
R0
R2
High-Z
R1
High-Z
R0
G9
G11
G8
G10
G7
G9
G6
G8
G5
G7
G4
G6
G3
G5
G2
G4
G1
G3
G0
G2
High-Z
G1
High-Z
G0
B9
B11
B8
B10
B7
B9
B6
B8
B5
B7
B4
B6
B3
B5
B2
B4
B1
B3
B0
B2
High-Z
B1
High-Z
B0
Rev. B | Page 18 of 24
0x46
36-Bit SDR
Mode 1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B11
B10
B9
B8
G11
G10
B7
B6
B5
B4
B3
B2
B1
B0
R11
R10
G9
G8
Data Sheet
ADV7619
Table 10. DDR 4:2:2 Output Modes
Pixel Output
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
0x20
8-Bit DDR
ITU-R BT.656, Mode 0
Clock Rise
Clock Fall
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Cb7, Cr7
Y7
Cb6, Cr6
Y6
Cb5, Cr5
Y5
Cb4, Cr4
Y4
Cb3, Cr3
Y3
Cb2, Cr2
Y2
Cb1, Cr1
Y1
Cb0, Cr0
Y0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DDR 4:2:2 Mode (Clock/2)—OP_FORMAT_SEL[7:0] =
0x21
0x22
10-Bit DDR
12-Bit DDR
ITU-R BT.656, Mode 0
ITU-R BT.656, Mode 0
Clock Rise
Clock Fall
Clock Rise
Clock Fall
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Cb9, Cr9
Y9
Cb11, Cr11
Y11
Cb8, Cr8
Y8
Cb10, Cr10
Y10
Cb7, Cr7
Y7
Cb9, Cr9
Y9
Cb6, Cr6
Y6
Cb8, Cr8
Y8
Cb5, Cr5
Y5
Cb7, Cr7
Y7
Cb4, Cr4
Y4
Cb6, Cr6
Y6
Cb3, Cr3
Y3
Cb5, Cr5
Y5
Cb2, Cr2
Y2
Cb4, Cr4
Y4
Cb1, Cr1
Y1
Cb3, Cr3
Y3
Cb0, Cr0
Y0
Cb2, Cr2
Y2
High-Z
High-Z
Cb1, Cr1
Y1
High-Z
High-Z
Cb0, Cr0
Y0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Rev. B | Page 19 of 24
ADV7619
Data Sheet
Table 11. DDR 4:4:4 Output Modes
Pixel Output
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
1
0x60
24-Bit DDR, Mode 0
Clock Rise1
Clock Fall1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
R7-0
R7-1
R6-0
R6-1
R5-0
R5-1
R4-0
R4-1
R3-0
R3-1
R2-0
R2-1
R1-0
R1-1
R0-0
R0-1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
G7-0
G7-1
G6-0
G6-1
G5-0
G5-1
G4-0
G4-1
G3-0
G3-1
G2-0
G2-1
G1-0
G1-1
G0-0
G0-1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
B7-0
B7-1
B6-0
B6-1
B5-0
B5-1
B4-0
B4-1
B3-0
B3-1
B2-0
B2-1
B1-0
B1-1
B0-0
B0-1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DDR 4:4:4 Mode (Clock/2)—OP_FORMAT_SEL[7:0] =
0x61
0x62
30-Bit DDR, Mode 0
36-Bit DDR, Mode 0
Clock Rise1
Clock Fall1
Clock Rise1
Clock Fall1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
R9-0
R9-1
R11-0
R11-1
R8-0
R8-1
R10-0
R10-1
R7-0
R7-1
R9-0
R9-1
R6-0
R6-1
R8-0
R8-1
R5-0
R5-1
R7-0
R7-1
R4-0
R4-1
R6-0
R6-1
R3-0
R3-1
R5-0
R5-1
R2-0
R2-1
R4-0
R4-1
R1-0
R1-1
R3-0
R3-1
R0-0
R0-1
R2-0
R2-1
High-Z
High-Z
R1-0
R1-1
High-Z
High-Z
R0-0
R0-1
G9-0
G9-1
G11-0
G11-1
G8-0
G8-1
G10-0
G10-1
G7-0
G7-1
G9-0
G9-1
G6-0
G6-1
G8-0
G8-1
G5-0
G5-1
G7-0
G7-1
G4-0
G4-1
G6-0
G6-1
G3-0
G3-1
G5-0
G5-1
G2-0
G2-1
G4-0
G4-1
G1-0
G1-1
G3-0
G3-1
G0-0
G0-1
G2-0
G2-1
High-Z
High-Z
G1-0
G1-1
High-Z
High-Z
G0-0
G0-1
B9-0
B9-1
B11-0
B11-1
B8-0
B8-1
B10-0
B10-1
B7-0
B7-1
B9-0
B9-1
B6-0
B6-1
B8-0
B8-1
B5-0
B5-1
B7-0
B7-1
B4-0
B4-1
B6-0
B6-1
B3-0
B3-1
B5-0
B5-1
B2-0
B2-1
B4-0
B4-1
B1-0
B1-1
B3-0
B3-1
B0-0
B0-1
B2-0
B2-1
High-Z
High-Z
B1-0
B1-1
High-Z
High-Z
B0-0
B0-1
xx-0 and xxx-0 correspond to data clocked at the rising edge; xx-1 and xxx-1 correspond to data clocked at the falling edge.
Rev. B | Page 20 of 24
Data Sheet
ADV7619
Table 12. Special SDR 4:2:2 and 4:4:4 Output Modes for Video with Pixel Clock Frequencies Above 170 MHz1
Pixel Output
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
2 × SDR 4:2:2 Interleaved—OP_FORMAT_SEL[7:0] =
0x94
0x95
0x96
2 × 24-Bit
2 × 20-Bit
2 × 16-Bit
Mode 02
Mode 02
Mode 02
Y7-0
Y9-0
Y11-0
Y6-0
Y8-0
Y10-0
Y5-0
Y7-0
Y9-0
Y4-0
Y6-0
Y8-0
Y3-0
Y5-0
Y7-0
Y2-0
Y4-0
Y6-0
Y1-0
Y3-0
Y5-0
Y0-0
Y2-0
Y4-0
High-Z
Y1-0
Y3-0
High-Z
Y0-0
Y2-0
High-Z
High-Z
Y1-0
High-Z
High-Z
Y0-0
Cb7-0
Cb9-0
Cb11-0
Cb6-0
Cb8-0
Cb10-0
Cb5-0
Cb7-0
Cb9-0
Cb4-0
Cb6-0
Cb8-0
Cb3-0
Cb5-0
Cb7-0
Cb2-0
Cb4-0
Cb6-0
Cb1-0
Cb3-0
Cb5-0
Cb0-0
Cb2-0
Cb4-0
High-Z
Cb1-0
Cb3-0
High-Z
Cb0-0
Cb2-0
High-Z
High-Z
Cb1-0
High-Z
High-Z
Cb0-0
Y7-1
Y9-1
Y11-1
Y6-1
Y8-1
Y10-1
Y5-1
Y7-1
Y9-1
Y4-1
Y6-1
Y8-1
Y3-1
Y5-1
Y7-1
Y2-1
Y4-1
Y6-1
Y1-1
Y3-1
Y5-1
Y0-1
Y2-1
Y4-1
High-Z
Y1-1
Y3-1
High-Z
Y0-1
Y2-1
High-Z
High-Z
Y1-1
High-Z
High-Z
Y0-1
Cr7-0
Cr9-0
Cr11-0
Cr6-0
Cr8-0
Cr10-0
Cr5-0
Cr7-0
Cr9-0
Cr4-0
Cr6-0
Cr8-0
Cr3-0
Cr5-0
Cr7-0
Cr2-0
Cr4-0
Cr6-0
Cr1-0
Cr3-0
Cr5-0
Cr0-0
Cr2-0
Cr4-0
High-Z
Cr1-0
Cr3-0
High-Z
Cr0-0
Cr2-0
High-Z
High-Z
Cr1-0
High-Z
High-Z
Cr0-0
1
2 × SDR 4:4:4 Interleaved—OP_FORMAT_SEL[7:0] =
0x54
2 × 24-Bit
Mode 02
G7-0
G6-0
G5-0
G4-0
G3-0
G2-0
G1-0
G0-0
B7-0
B6-0
B5-0
B4-0
B3-0
B2-0
B1-0
B0-0
R7-0
R6-0
R5-0
R4-0
R3-0
R2-0
R1-0
R0-0
G7-1
G6-1
G5-1
G4-1
G3-1
G2-1
G1-1
G0-1
B7-1
B6-1
B5-1
B4-1
B3-1
B2-1
B1-1
B0-1
R7-1
R6-1
R5-1
R4-1
R3-1
R2-1
R1-1
R0-1
These modes require additional writes. (write 80 to DPLL map Register 0xC3, write 03 to DPLL map Register 0xCF, and write A0 to IO map Register 0xDD). Refer to
Hardware User Guide UG-237.
2
xx-0 and xxx-0 correspond to odd samples; xx-1 and xxx-1 correspond to even samples.
Rev. B | Page 21 of 24
ADV7619
Data Sheet
OUTLINE DIMENSIONS
1.00 REF
14.20
14.00 SQ
13.80
128
1
12.40 REF
97
96
97
96
128
1
PIN 1
SEATING
PLANE
EXPOSED
PAD
0.15
0.10
0.05
BOTTOM VIEW
TOP VIEW
1.05
1.00
0.95
0.20
0.15
0.09
(PINS DOWN)
VIEW A
0.08
COPLANARITY
(PINS UP)
65
64
32
33
0.40
BSC
LEAD PITCH
7°
0°
6.35
REF
32
65
64
0.23
0.18
0.13
33
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AEE-HD
Figure 8. 128-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-128-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADV7619KSVZ
ADV7619KSVZ-P
EVAL-ADV7619EB1Z
EVAL-ADV7619-7511-P
EVAL-ADV7619-7511
1
2
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
128-Lead TQFP_EP
128-Lead TQFP_EP
Evaluation Board with HDCP key
Evaluation Board without HDCP keys
Evaluation Board with HDCP keys
Z = RoHS Compliant Part.
EVAL-ADV7619-7511 and EVAL-ADV7619-7511-P are RoHS Compliant Parts.
Rev. B | Page 22 of 24
Package Option
SV-128-1
SV-128-1
10-06-2011-A
0.75
0.60
0.45
16.20
16.00 SQ
15.80
1.20
MAX
Data Sheet
ADV7619
NOTES
Rev. B | Page 23 of 24
ADV7619
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries.
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09580-0-5/12(B)
Rev. B | Page 24 of 24