PYRAMID P4C1024L70SI

P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Common Data I/O
Access Times
—55/70 (Commercial or Industrial)
Fully TTL Compatible Inputs and Outputs
Single 5 Volts ±10% Power Supply
Automatic Power Down
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
Three-State Outputs
Advanced CMOS Technology
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory
locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE1 or OE is HIGH or WE or CE2 is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, and a 600 mil PDIP.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (P600, C10), SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document # SRAM125 REV C
Revised September 2006
1
P4C1024L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Supply Voltage
Commercial (0°C to 70°C)
4.5V ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C)
4.5 ≤ VCC ≤ 5.5V
MAXIMUM RATINGS(1)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
Min
Max
Unit
Supply Voltage with Respect to GND
-0.5
7.0
V
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
TA
Operating Ambient Temperature
-55
125
°C
STG
Storage Temperature
-65
150
°C
IOUT
Output Current into Low Outputs
25
mA
ILAT
Latch-up Current
VCC
VTERM
Parameter
>200
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
Test Conditions
Symbol
Parameter
VOH
Output High Voltage
(I/O0 - I/O7)
IOH = –1mA, VCC = 4.5V
VOL
Output Low Voltage
(I/O0 - I/O7)
IOL = 2.1mA
VIH
Input High Voltage
VIL
Input Low Voltage
ILI
Input Leakage Current
GND ≤ VIN ≤ VCC
ILO
Output Leakage Current
GND ≤ VOUT ≤ VCC
CE1 ≥ VIH or CE2 ≤ VIL
ISB
VCC Current
TTL Standby Current
(TTL Input Levels)
VCC = 5.5V, IOUT = 0 mA
CE1 = VIH or CE2 = VIL
ISB1
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC = 5.5V, IOUT = 0 mA
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V
Document # SRAM125 REV C
Min
Max
2.4
Ind'l.
Com'l.
Ind'l.
Com'l.
Unit
V
0.4
V
2.2
VCC + 0.3
V
-0.5
0.8
V
-5
-2
+5
+2
µA
-5
-2
+5
+2
µA
3
mA
100
µA
Page 2 of 10
P4C1024L
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
Symbol
Parameter
Test Conditions
Max
Unit
CIN
Input Capacitance
VIN = 0V
7
pF
COUT
Output Capacitance
VOUT = 0V
9
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Parameter
Dynamic Operating Current
*
**
Temperature
Range
-55
-70
-55
-70
Commercial
70
70
15
15
mA
Industrial
85
85
25
25
mA
Unit
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching
inputs are 0V and 3V.
**As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
tRC
Read Cycle Time
tAA
Address Access Time
tAC
tOH
Chip Enable Access
Time
Output Hold from
Address Change
-70
-55
Min
Max
55
Min
Max
Unit
ns
70
55
70
ns
55
70
ns
5
5
ns
10
10
ns
tLZ
Chip Enable to
Output in Low Z
tHZ
Chip Disable to
Output in High Z
20
25
ns
tOE
Output Enable Low
to Data Valid
30
35
ns
tOLZ
Output Enable Low to
Low Z
tOHZ
Output Enable High
to High Z
tPU
Chip Enable to Power
Up Time
tPD
Chip Disable to
Power Down Time
Document # SRAM125 REV C
5
5
20
0
ns
25
0
55
ns
ns
70
ns
Page 3 of 10
P4C1024L
OE CONTROLLED)(1)
READ CYCLE NO. 1 (OE
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
CE CONTROLLED)
READ CYCLE NO. 3 (CE
Notes:
1. WE is HIGH for READ cycle.
2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE1 transition LOW or CE2 transition HIGH.
Document # SRAM125 REV C
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Page 4 of 10
P4C1024L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-70
-55
Symbol
Parameter
tWC
Write Cycle Time
55
70
ns
tCW
Chip Enable Time
to End of Write
50
60
ns
tAW
Address Valid to
End of Write
50
60
ns
tAS
Address Set-up
Time
0
0
ns
tWP
Write Pulse Width
40
50
ns
tAH
Address Hold
Time
0
0
ns
tDW
Data Valid to End
of Write
25
30
ns
tDH
Data Hold Time
0
0
ns
tWZ
Write Enable to
Output in High Z
tOW
Output Active from
End of Write
Min
Max
Min
25
5
Max
30
5
Unit
ns
ns
WE CONTROLLED)(6)
WRITE CYCLE NO. 1 (WE
Notes:
6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM125 REV C
Page 5 of 10
P4C1024L
CE CONTROLLED)(6)
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE
TRUTH TABLE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
I/O
Power
Standby
3ns
Standby
H
X
X
X
High Z
1.5V
1.5V
Standby
X
L
X
X
Standby
DOUT Disabled
L
H
H
H
High Z
High Z
See Fig. 1 and 2
Read
L
H
H
DOUT
Write
L
H
L
X
L
DIN
Active
Active
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
CE1 CE2 OE WE
Mode
Figure 1. Output Load
Active
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the P4C1024L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC
and ground planes directly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required between VCC and ground.
Document # SRAM125 REV C
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Page 6 of 10
P4C1024L
DATA RETENTION
Symbol
VDR
ICCDR (1)
tCDR
tR
Test Conditions
Min
Max
Unit
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
2.0
5.5
V
VDR = 2.0V
30
µA
VDR = 3.0V
50
µA
Parameter
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
See Retention Waveform
Operating Recovery Time
0
ns
5
ms
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
CE1 CONTROLLED)
LOW VCC DATA RETENTION WAVEFORM 1 (CE
LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)
DATA RETENTION MODE
VCC
4.5V
VDR
tCDR
CE2
VIL
Document # SRAM125 REV C
2.2V
4.5V
tR
CE2 ≤ -0.2V
VIL
Page 7 of 10
P4C1024L
ORDERING INFORMATION
SELECTION GUIDE
The P4C1024L is available in the following temperature, speed and package options.
Temperature
Range
Commercial
Package
-55
-70
Plastic DIP (600 mil)
-55PC
-70PC
Plastic SOP (445 mil)
-55SC
-70SC
TSOP
-55TC
-70TC
-55CWC
-70CWC
Plastic DIP (600 mil)
-55PI
-70PI
Plastic SOP (445 mil)
-55SI
-70SI
TSOP
-55TI
-70TI
-55CWI
-70CWI
Ceramic DIP (600 mil)
Industrial
Speed
Ceramic DIP (600 mil)
TSOP PIN CONFIGURATION
Document # SRAM125 REV C
Page 8 of 10
P4C1024L
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
Pkg #
# Pins
Symbol
A
A1
b2
C
D
e
E
H
h
L
α
P600
PLASTIC DUAL IN-LINE PACKAGE
32 (600 mil)
Min
Max
0.170
0.210
0.015
0.014
0.023
0.045
0.070
0.009
0.014
1.600
1.400
0.530
0.300
0.600
0.380
0.100 BSC
0.600 BSC
0.120
0.150
0°
15°
S12
SOIC/SOP SMALL OUTLINE IC PACKAGE
32 (445 Mil)
Min
Max
0.118
0.004
0.014
0.020
0.006
0.012
0.790
0.820
0.050 BSC
0.435
0.455
0.546
0.566
0.010
0.029
0.023
0.039
0°
8°
Document # SRAM125 REV C
Page 9 of 10
P4C1024L
Pkg #
# Pins
Symbol
A
A2
b
D
E
e
HD
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
T3
TSOP THIN SMALL OUTLINE PACKAGE (8 x 20 mm)
32
Min
Max
0.048
0.037
0.042
0.006
0.011
0.720
0.729
0.307
0.323
0.050 BSC
0.779
0.796
C10
SIDEBRAZED DUAL IN-LINE PACKAGES
32 (600 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.680
0.510
0.620
0.600 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
Document # SRAM125 REV C
Page 10 of 10
P4C1024L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM125
P4C1024L LOW POWER 128K x 8 CMOS STATIC RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
B
Feb-06
JDB
Added TSOP package
C
Sep-06
JDB
Added Ceramic DIP package
Document # SRAM125 REV C
DESCRIPTION OF CHANGE
Page 11 of 10