PYRAMID P4C1026

P4C1026
ULTRA HIGH SPEED 256K x 4
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
TTL/CMOS Compatible Outputs
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 20/25/35 ns (Military)
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil SOJ
– 28-Pin 400 mil SOJ
– 28-Pin 400 mil Ceramic DIP
– 32-Pin Ceramic LCC
Low Power
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
Three-State Outputs
DESCRIPTION
The P4C1026 is a 1 Meg ultra high speed static RAM
organized as 256K x 4. The CMOS memory requires no clock
or refreshing and has equal access and cycle times. Inputs
and outputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With battery
backup, data integrity is maintained for supply voltages down
to 2.0V.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
The P4C1026 is available in a 28-pin 300 mil and 400 mil SOJ
packages, as well as Ceramic DIP and LCC packages,
providing excellent board level densities.
SOJ (J5, J7), DIP (C7)
LCC(L13)
Document # SRAM127 REV E
1
Revised April 2007
P4C1026
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
GND
VCC
Commercial
–40°C to +85°C
0°C to +70°C
0V
0V
5.0V ± 10%
5.0V ± 10%
Military
-55°C to +125°C
0V
5.0V ± 10%
Grade(2)
Industrial
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions Typ. Unit
VIN = 0V
7
pF
VOUT = 0V
10
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
Test Conditions
P4C1026
Min
Max
Unit
VIH
Input High Voltage
2.2
VCC +0.5
V
VIL
Input Low Voltage
–0.5(3)
0.8
V
VHC
CMOS Input High Voltage
VLC
CMOS Input Low Voltage
VCD
Input Clamp Diode Voltage VCC = Min., IIN = –18 mA
VOL
VOH
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
VCC –0.2 VCC +0.5
–0.5
IOL = +8 mA, VCC = Min.
IOH = –4 mA, VCC = Min.
VCC = Max.
ILI
Input Leakage Current
ILO
Output Leakage Current
ISB
CE ≥ VIH
Standby Power Supply
Current (TTL Input Levels) VCC = Max ., f = Max., Outputs Open
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
Document # SRAM127 REV E
(3)
VIN = GND to VCC
VCC = Max., CE = VIH
VOUT = GND to VCC
CE ≥ VHC
VCC = Max., f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
V
0.2
V
–1.2
V
0.4
V
2.4
V
–5
+5
µA
–5
+5
µA
___
35
mA
___
10
mA
Page 2 of 10
P4C1026
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
ICC
Dynamic Operating Current*
Temperature
Range
Commercial
Industrial
Unit
–15
–20
–25
–35
80
75
75
75
mA
90
80
80
80
mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to
Data Retention Time
tR†
Operation Recovery Time
Test Conditions
Min
Typ.*
VCC =
2.0V
3.0V
Max
VCC =
2.0V 3.0V
2.0
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V or
VIN ≤ 0.2V
Unit
V
10
15
250
500
µA
0
ns
tRC§
ns
*TA = +125°C
tRC = Read Cycle Time
§
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM127 REV E
Page 3 of10
P4C1026
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-15
Min
-25
-20
Max
Min Max
Min
20
25
-35
Max
Min
Max
Unit
t RC
Read Cycle Time
tAA
Address Access Time
15
20
25
35
ns
tAC
Chip Enable Access Time
15
20
25
35
t OH
Output Hold from Address Change
2
2
2
2
ns
ns
tLZ
Chip Enable to Output in Low Z
2
3
3
3
ns
t HZ
Chip Disable to Output in High Z
tPU
Chip Enable to Power Up Time
tPD
Chip Disable to Power Down Time
15
8
0
15
25
ns
ns
0
0
20
ns
11
10
9
0
35
35
ns
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
Document # SRAM127 REV E
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 4 of 10
P4C1026
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-15
-20
-25
-35
Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
13
20
25
35
ns
tCW
Chip Enable Time to End of Write
12
15
18
25
ns
tAW
Address Valid to End of Write
12
15
18
25
ns
tAS
Address Set-up Time
0
0
0
0
ns
tWP
Write Pulse Width
12
15
18
25
ns
t AH
Address Hold Time from End of Write
0
0
0
0
ns
tDW
Data Valid to End of Write
7
8
10
15
ns
t DH
Data Hold Time
0
0
0
0
ns
tWZ
Write Enable to Output in High Z
tDW
Output Active from End of Write
6
2
8
2
10
2
15
3
ns
ns
WE CONTROLLED)(10,11)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM127 REV E
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of10
P4C1026
CE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Mode
CE
OE
WE
I/O
Power
Input Rise and Fall Times
3ns
Standby
H
X
X
High Z
Standby
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
DOUT
Disabled
L
H
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
Output Load
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1258, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
Document # SRAM127 REV E
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Page 6 of 10
P4C1026
ORDERING INFORMATION
SELECTION GUIDE
The P4C1026 is available in the following temperature, speed and package options.
Temperature
Range
Commercial
Industrial
Military
Temperature
Military
Processeed*
Package
Speed
1513 10
15
20
25
35
Plastic SOJ, 300 mil
-15J3C
-20J3C
-25J3C
-35J3C
Plastic SOJ, 400 mil
-15J4C
-20J4C
-25J4C
-35J4C
Plastic SOJ, 300 mil
-15J3I
-20J3I
-25J3I
-35J3I
Plastic SOJ, 400 mil
-15J4I
-20J4I
-25J4I
-35J4I
Ceramic DIP, 400 mil
N/A
-20CM
-25CM
-35CM
28-Pin Ceramic LCC
N/A
-20L28M
-25L28M
-35L28M
32-Pin Ceramic LCC
N/A
-20L32M
-25L32M
-35L32M
Ceramic DIP, 400 mil
N/A
-20CMB
-25CMB
-35CMB
28-Pin Ceramic LCC
N/A
-20L28MB
-25L28MB
-35L28MB
32-Pin Ceramic LCC
N/A
-20L32MB
-25L32MB
-35L32MB
* Military temperature range with MIL-STD-883, Class B compliance
N/A = Not Available
Document # SRAM127 REV E
Page 7 of10
P4C1026
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
J5
SOJ SMALL OUTLINE IC PACKAGE
28 (300 mil)
Min
Max
0.120
0.148
0.078
0.014
0.020
0.007
0.011
0.700
0.730
0.050 BSC
0.335 BSC
0.292
0.300
0.267 BSC
0.025
-
J7
SOJ SMALL OUTLINE IC PACKAGE
28 (400 mil)
Min
Max
0.128
0.148
0.082
0.013
0.019
0.007
0.013
0.720
0.730
0.050 BSC
0.435
0.445
0.395
0.405
0.360
0.380
0.025
-
Document # SRAM127 REV E
Page 8 of 10
P4C1026
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
e
h
j
L
L1
L2
ND
NE
C7
SIDEBRAZED DUAL IN-LINE PACKAGE
28 (400 mil)
Min
Max
0.115
0.255
0.016
0.020
0.045
0.065
0.008
0.018
1.384
1.416
0.387
0.403
0.400 BSC
0.100 TYP
0.125
0.200
0.015
0.070
0.005
—
0.005
—
L13
RECTANGULAR LEADLESS CHIP CARRIER
32
Min
Max
0.070
0.093
0.054
0.066
0.025
0.031
0.442
0.458
0.300 BSC
0.150 BSC
—
0.458
0.742
0.758
0.400 BSC
0.200 BSC
0.050 TYP
0.045
0.055
0.045
0.055
0.090 REF
7
9
Document # SRAM127 REV E
Page 9 of10
P4C1026
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM127
P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
Oct-05
JDB
New Data Sheet
A
Aug-06
JDB
Updated SOJ package information
B
Oct-06
JDB
Added Ceramic DIP, LCC packages and military processing
C
Dec-06
JDB
Added L13 package, removed L12 package
D
Mar-07
JDB
Minor typographic corrections
E
Apr-07
JDB
Corrected LCC pin configuration
Document # SRAM127 REV E
DESCRIPTION OF CHANGE
Page 10 of 10