PYRAMID P4C1049

P4C1049/P4C1049L
HIGH SPEED 512K x 8
STATIC CMOS RAM
FEATURES
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—36-Pin SOJ (400 mil)
—36-Pin FLATPACK
—36-Pin LCC (452 mil x 920 mil)
High Speed (Equal Access and Cycle Times)
— 15/20/25 ns (Commercial)
— 20/25/35 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
Common Data I/O
Three-State Outputs
DESCRIPTION
The P4C1049 device provides asynchronous operation
with matching access and cycle times. Memory locations are specified on address pins A0 to A18. Reading is
accomplished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either CE or OE is HIGH or WE is
LOW.
The P4C1049 is a 4 Megabit high-speed CMOS
static RAM organized as 512Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 15 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P4C1049
is a member of a family of PACE RAM™ products offering fast access times.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
SOLDER-SEAL
FLATPACK (FS-4)
SOJ (J9)
LCC (L11)
1519B
Document # SRAM128 REV OR
1
Revised October 2005
P4C1049
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
V CC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
V TERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
Symbol
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Ambient
Temperature
Parameter
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
VCC
Symbol
Parameter
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
Input Capacitance
–55°C to +125°C
–40°C to +85°C
Industrial
Commercial
0°C to +70°C
Unit
TBIAS
GND
Military
Value
COUT
Conditions Typ. Unit
VIN = 0V
8
pF
Output Capacitance VOUT = 0V
8
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
V HC
CMOS Input High Voltage
VLC
CMOS Input Low Voltage
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
VOH
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
ILI
Input Leakage Current
P4C1049L
Unit
Min
Max
VCC +0.3 V
2.2
0.8
0.8
–0.3(3)
–0.3(3)
VCC –0.2 VCC +0.3 VCC –0.2 VCC +0.3
–0.3
VCC = Max.
(3)
0.2
–0.3
(3)
0.4
–10
0.4
V
V
+10
–5
+5
n/a
Ind./Com’l.
–5
+5
Mil.
–10
+10
–5
+5
Ind./Com’l.
–5
+5
n/a
n/a
Mil.
___
45
___
40
Standby Power Supply
VCC= Max,
Ind./Com’l.
Current (TTL Input Levels) f = Max., Outputs Open
___
40
___
n/a
Mil.
___
15
___
10
Ind./Com’l.
___
___
n/a
Output Leakage Current
CE = VIH,
V
V
n/a
VIN = GND to VCC
V
0.2
2.4
2.4
Mil.
VCC = Max.,
ILO
P4C1049
Min
Max
V
+0.3
2.2
CC
Test Conditions
µA
µA
VOUT = GND to VCC
CE ≥ VIH
ISB
CE ≥ VHC
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
VCC= Max,
10
mA
mA
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
N/A = Not Applicable
Document # SRAM128 REV OR
Page 2 of 12
P4C1049
DATA RETENTION CHARACTERISTICS (P4C1049L Military Temperature Only)
Symbol
Parameter
V DR
VCC for Data Retention
ICCDR
Data Retention Current
t CDR
Chip Deselect to
Data Retention Time
tR †
Operation Recovery Time
Test Conditons
Min
Typ.*
VCC = 3.0V
Max
VCC = 3.0V
V
3.0
2
CE ≥ VCC –0.2V,
3
mA
0
ns
tRC§
ns
VIN ≥ VCC –0.2V
or VIN ≤ 0.2V
Unit
*TA = +25°C
§tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Parameter
Dynamic Operating Current*
Temperature
Range
–15
–20
Commercial
220
Industrial
Military
Unit
185
–25
180
–35
N/A
–45
N/A
–55
N/A
–70
N/A
N/A
190
185
175
N/A
N/A
N/A
mA
N/A
200
195
185
175
170
165
mA
mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
Document # SRAM128 REV OR
Page 3 of 12
P4C1049
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-15
-20
-25
-35
-45
-55
-70
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
t RC
Read Cycle Time
tAA
Address Access Time
15
20
25
35
45
55
70
ns
t AC
Chip Enable Access Time
15
20
25
35
45
55
70
ns
t OH
Output Hold from Address
Change
3
3
3
3
3
3
3
ns
tLZ
Chip Enable to Output in
Low Z
3
3
3
3
3
3
3
ns
t HZ
Chip Disable to Output in
High Z
8
9
11
15
20
25
30
ns
tOE
Output Enable Low to Data
Valid
7
9
10
15
20
25
30
ns
tOLZ
Output Enable Low to Low Z
t OHZ
Output Enable High to High Z
t PU
Chip Enable to Power Up
Time
Chip Disable to Power Down
Time
t PD
20
15
0
0
0
0
15
20
25
0
0
0
0
35
45
ns
0
30
25
20
ns
70
0
0
15
10
55
45
0
0
9
7
35
25
ns
0
55
ns
70
ns
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE
Document # SRAM128 REV OR
Page 4 of 12
P4C1049
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
CE CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –2.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
Document # SRAM128 REV OR
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of 12
P4C1049
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-15
-20
-25
-45
-35
-55
-70
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
15
20
25
35
45
55
70
ns
tCW
Chip Enable Time to End of
Write
12
14
18
22
30
35
40
ns
tAW
Address Valid to End of
Write
12
14
16
20
25
35
40
ns
tAS
Address Set-up Time
0
0
0
0
0
0
0
ns
tWP
Write Pulse Width
12
14
16
22
25
30
35
ns
tAH
Address Hold Time
0
0
0
0
0
0
0
ns
tDW
Data Valid to End of Write
9
11
13
15
20
25
30
ns
t DH
Date Hold Time
0
0
0
0
0
0
0
ns
tWZ
Write Enable to Output in
High Z
tOW
Output Active from End of
Write
8
3
10
3
11
3
15
5
18
5
25
5
30
5
ns
ns
WE CONTROLLED)(10,11)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
Document # SRAM128 REV OR
Page 6 of 12
P4C1049
CE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
Document # SRAM128 REV OR
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 7 of 12
P4C1049
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
Output Timing Reference Level
Output Load
Mode
CE O E W E
I/O
Power
1.5V
Standby
Standby
H
X
X
X
X
X
High Z
High Z
Standby
Standby
1.5V
DOUT Disabled
L
H
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1049, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground. To avoid
Document # SRAM128 REV OR
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Page 8 of 12
P4C1049
ORDERING INFORMATION
Document # SRAM128 REV OR
Page 9 of 12
P4C1049
Pkg #
# Pins
Symbol
A
b
c
D
E
E1
E2
E3
e
L
Q
S
M
N
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
FS-4
SOLDER SEAL FLATPACK
36
Min
Max
0.089
0.125
0.015
0.019
0.003
0.007
0.910
0.930
0.505
0.515
0.530
0.385
0.395
0.055
0.065
0.050 BSC
0.300
0.350
0.015
0.038
0.045
0.0015
36
J9
SOJ SMALL OUTLINE IC PACKAGE
36
Min
Max
0.130
0.145
0.082
0.015
0.020
0.007
0.013
0.920
0.930
0.050 BSC
0.435
0.445
0.395
0.405
0.370 BSC
0.045
0.055
Document # SRAM128 REV OR
Page 10 of 12
P4C1049
Pkg #
# Pins
Symbol
A
A1
B
D
D1
E
e
L
L2
P
R
L11
RECTANGULAR LEADLESS CHIP CARRIER
36
Min
Max
0.080
0.100
0.054
0.066
0.022
0.028
0.910
0.930
0.840
0.860
0.445
0.460
.050 BSC
.100 TYP
0.115
0.135
0.006
.009 TYP
Document # SRAM128 REV OR
Page 11 of 12
P4C1049
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM128
P4C1049 / P4C1049L HIGH SPEED 512K x 8 STATIC CMOS RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
Oct-05
JDB
Document # SRAM128 REV OR
DESCRIPTION OF CHANGE
New Data Sheet
Page 12 of 12