Revised January 2005 MM74HCU04 Hex Inverter General Description Features The MM74HCU04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. ■ Typical propagation delay: 7 ns The MM74HCU04 is an unbuffered inverter. It has high noise immunity and the ability to drive 15 LS-TTL loads. The 74HCU logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. ■ Low input current: 1 µA maximum ■ Fanout of 15 LS-TTL loads ■ Quiescent power consumption: 10 µA maximum at room temperature Ordering Code: Order Number Package Package Description Number MM74HCU04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HCU04MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HCU04SJ MM74HCU04MTC M14D MTC14 Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCU04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HCU04N_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Schematic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 2005 Fairchild Semiconductor Corporation DS005296 www.fairchildsemi.com MM74HCU04 Hex Inverter September 1983 MM74HCU04 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA DC VCC or GND Current, per pin (ICC) ±50 mA 600 mW S.O. Package only 500 mW Units 6 V DC Input or Output Voltage 0 VCC V −40 +85 °C Operating Temperature Range (TA) Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Power Dissipation (PD) (Note 3) Max 2 (VIN, VOUT ) −65°C to +150°C Storage Temperature Range (TSTG) Min Supply Voltage (VCC) Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. Lead Temperature (TL) 260°C (Soldering 10 seconds) DC Electrical Characteristics Symbol VIH VIL VOH Parameter Conditions (Note 4) TA = 25°C VCC Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.7 1.7 1.7 V Input Voltage 4.5V 3.6 3.6 3.6 V 6.0V 4.8 4.8 4.8 V Maximum LOW Level 2.0V 0.3 0.3 0.3 V Input Voltage 4.5V 0.8 0.8 0.8 V 6.0V 1.1 1.1 1.1 V Minimum HIGH Level VIN = VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.8 1.8 1.8 V 4.5V 4.5 4.0 4.0 4.0 V 6.0V 6.0 5.5 5.5 5.5 V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = GND VOL Maximum LOW Level VIN = VIH Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.2 0.2 0.2 V 4.5V 0 0.5 0.5 0.5 V 6.0V 0 0.5 0.5 0.5 V |IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Maximum Quiescent VIN = VCC or GND 6.0V 2.0 20 40 µA Supply Current IOUT = 0 µA VIN = VCC IIN Maximum Input Current ICC Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol tPHL, tPLH Parameter Conditions Typ Maximum Propagation 7 Guaranteed Limit 13 Units ns Delay AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPHL, tPLH tTLH, tTHL CPD Parameter Conditions VCC TA=25°C Typ TA=−40 to 85°C TA=−55 to 125°C Guaranteed Limits Units Maximum Propagation 2.0V 49 82 103 120 Delay 4.5V 9.9 16 21 24 ns 6.0V 8.4 14 18 20 ns Maximum Output Rise 2.0V 30 75 95 110 ns and Fall Time 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns Power Dissipation (per gate) 90 ns pF Capacitance (Note 5) CIN Maximum Input 8 15 15 15 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Typical Applications FIGURE 1. Crystal Oscillator FIGURE 2. Stable RC Oscillator FIGURE 3. Schmitt Trigger 3 www.fairchildsemi.com MM74HCU04 AC Electrical Characteristics MM74HCU04 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 MM74HCU04 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com MM74HCU04 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 MM74HCU04 Hex Inverter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com