Revised January 2005 MM74HC125/MM74HC126 3-STATE Quad Buffers General Description Features The MM74HC125 and MM74HC126 are general purpose 3-STATE high speed non-inverting buffers utilizing advanced silicon-gate CMOS technology. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to 15 low power Schottky inputs. ■ Typical propagation delay: 13 ns ■ Wide operating voltage range: 2–6V ■ Low input current: 1 µA maximum ■ Low quiescent current: 80 µA maximum (74HC) ■ Fanout of 15 LS-TTL loads The MM74HC125 require the 3-STATE control input C to be taken high to put the output into the high impedance condition, whereas the MM74HC126 require the control input to be low to put the output into high impedance. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Ordering Code: Order Number Package Package Description Number MM74HC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC125SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC125MTC MTC14 MM74HC125MTCX-NL 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC125N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC126M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC126MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC126SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC126MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC126MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC126N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.) Pb-Free package per JEDEC J-STD-020B. © 2005 Fairchild Semiconductor Corporation DS005308 www.fairchildsemi.com MM74HC125/MM74HC126 3-STATE Quad Buffers September 1983 MM74HC125/MM74HC126 Connection Diagrams Pin Assignments for DIP, SOIC, SOP and TSSOP Top View (MM74HC125) Top View (MM74HC126) Truth Tables Inputs Output Inputs Output A C Y A C Y H L H H H H L L L L H L X H Z X L Z www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC ) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±35 mA Min Max Units Power Dissipation (PD) 600 mW S.O. Package only 500 mW VIL VOH °C VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. 260°C DC Electrical Characteristics VIH −40 +85 Note 2: Unless otherwise specified all voltages are referenced to ground. (Soldering 10 seconds) Parameter V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) Symbol V VCC Input Rise or Fall Times (tr, tf) −65°C to +150°C (Note 3) 6 0 Operating Temperature Range (TA) ±70 mA (ICC) 2 DC Input or Output Voltage (VIN, VOUT) DC VCC or GND Current, per pin Storage Temperature Range (TSTG) Supply Voltage (VCC) (Note 4) Conditions TA = 25°C VCC Typ TA = −40 to 85°C TA = −40 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 V V 6.0V 4.2 4.2 4.2 V V Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL 2.0V 2.0 1.9 1.9 1.9 V Output Voltage |IOUT| ≤ 20 µA 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V V VIN = VIH or VIL VOL |IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V Maximum LOW Level VIN = VIH or VIL 2.0V 0 0.1 0.1 0.1 V Output Voltage |IOUT| ≤ 20 µA 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V VIN = VIH or VIL IOZ Maximum 3-STATE Output Leakage Current |IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VIH or VIL 6.0V ±0.5 ±5 ±10 µA VOUT = VCC or GND Cn = Disabled IIN Maximum Input Current VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA Supply Current IOUT = 0 µA Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC125/MM74HC126 Absolute Maximum Ratings(Note 1) MM74HC125/MM74HC126 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 45 pF, tr = tf = 6 ns Typ Guaranteed Limit Units 13 18 ns RL = 1 kΩ 13 25 ns Maximum RL = 1 kΩ 17 25 ns Output Disable Time from HIGH Level CL = 5 pF Maximum RL = 1 kΩ 18 25 ns Maximum RL = 1 kΩ 13 25 ns Output Disable Time from LOW Level CL = 5 pF Symbol tPHL, tPLH Parameter Conditions Maximum Propagation Delay Time tPZH Maximum Output Enable Time to HIGH Level tPHZ tPZL Output Enable Time to LOW Level tPLZ AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −40 to 125°C Guaranteed Limits Units tPHL, tPLH Maximum Propagation 2.0V 40 100 125 150 ns Delay Time 4.5V 14 20 25 30 ns 6.0V 12 17 21 25 ns 2.0V 35 130 163 195 ns 4.5V 14 26 33 39 ns 6.0V 12 22 28 39 ns 2.0V 25 125 156 188 ns 4.5V 14 25 31 38 ns 6.0V 12 21 26 31 ns 2.0V 25 125 156 188 ns 4.5V 14 25 31 38 ns tPLH, tPHL Maximum Propagation CL = 150 pF Delay Time tPZH, tPZL Maximum Output RL = 1 kΩ Enable Time tPHZ, tPLZ Maximum Output RL = 1 kΩ Disable Time tPZL, tPZH Maximum Output Enable Time tTLH, tTHL Maximum Output 6.0V 12 21 26 31 ns CL = 150 pF 2.0V 35 140 175 210 ns RL = 1 kΩ 4.5V 15 28 35 42 ns 6.0V 13 24 30 36 ns 2.0V 30 60 75 90 ns 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns CL = 50 pF Rise and Fall Time CIN Input Capacitance 5 10 10 10 pF COUT Output Capacitance Outputs 15 20 20 20 pF CPD Power Dissipation Capacitance (Note 5) (per gate) Enabled 45 pF Disabled 6 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC. www.fairchildsemi.com 4 MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrowy Package Number M14A 5 www.fairchildsemi.com MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 MM74HC125/MM74HC126 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com MM74HC125/MM74HC126 3-STATE Quad Buffers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8