MAXIM MAXQ1103-ENS

ABRIDGED DATA SHEET
19-5091; Rev 4; 3/11
KIT
ATION
EVALU
E
L
B
A
IL
AVA
High-Performance Secure RISC Microcontroller
Features
♦ High-Performance 32-Bit MAXQ30 RISC Core
♦ DC to 25MHz Operation, Approaching 1MIPS per MHz
♦ Dual 1.8V Core/3.3V I/O Enables Low Power/
Flexible Interfacing
♦ 5V Tolerant I/O
♦ Up to 32 General-Purpose I/O Pins
♦ 34 Instructions, Most Single Cycle
♦ Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
♦ Virtually Unlimited Software Stack
♦ 16-Bit Instruction Word, 32-Bit Internal Data Bus
♦ 16 x 32-Bit Accumulators
♦ Security Features
3DES-Encrypted External Memory Bus
Prevents Eavesdropping
Tamper Sensors Rapidly “Zeroize” Internal Keys
and User Data When:
Out-of-Range Temperature/Voltage Detected
User-Defined Self-Destruct Inputs (SDIx) Activated
Internal Cryptographic Hardware Includes:
DES Engine Supporting Single DES and 2/3-Key
3DES Operations
Public-Key Cryptographic Accelerator for
ECDSA (160-, 192-, and 256-Key Strength)
Public-Key Cryptographic Accelerator for
DSA and RSA (1024- and 2048-Key Strength)
Hardware Hash Engine Supports SHA-1,
SHA-224, and SHA-256
Unresettable True-Time Clock Self-Imposes
Expiration Dates and Date/Timestamping
♦ Memory Features
Secure Memory Protection Unit and 4KB
Instruction Cache
512KB of Internal Flash Program Memory
3KB Internal Program Memory SRAM
32KB Internal Data SRAM, Including 1KB BatteryBacked NV SRAM
Linear Address Space Directly Accesses Up to
8MB of External Program/Data Memory
♦ Peripheral Features
USB Device Controller with Four Endpoint Buffers
ISO 7816 UART with FIFO with Two Physically
Separate Communication Buses
♦ Power Management Features
♦ In-System Programming Through Debug Port or
Serial Port
♦ Ultra-Low Battery Leakage to Support NV RAM
and Security Sensors (150nA)
Applications
Electronic Commerce
PCI Terminals
PIN Pads
ATM Keyboards
EMV® Banking
Secure Access Control
Secure Data Storage
Pay-per-Play
Certificate Authentication
Electronic Signature
Generator
Ordering Information
PART
TEMP
RANGE
PINTAMPER
PACKAGE RESPONSIVE
MAXQ1103-ENS+ -40°C to +85°C 144 TQFP
Yes
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
EMV is a registered trademark of EMVCo, LLC.
See the Detailed Features section for complete list of features.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, contact the factory.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAXQ1103
General Description
The MAXQ1103 microcontroller is a low-power, 32-bit
RISC device that combines high-performance, singlecycle processing, sophisticated tamper-detection technology, and cryptographic hardware. Advanced
security features are designed to meet the stringent
requirements of regulations such as ITSEC E3 High,
FIPS 140-2 Level 3, and the Common Criteria
Certifications. The MAXQ1103 is targeted at electronic
commerce, banking, and data security systems that
require the highest levels of secure access control,
secure data storage, digital signature, or certificate
authentication. A secure memory protection unit protects critical internal and external memory against tampering with triple-DES (3DES) encryption. Activation of a
tamper sensor causes a rapid zeroization of critical
data. An internal physical shield layer increases the
complexity and cost of a physical attack against the die.
A 32-bit MAXQ30 core powers the cryptographically
secure MAXQ1103. Applications are supported with
512KB of high-performance internal flash memory for
code/data storage and 32KB SRAM. Up to 8MB of
additional external program and data memory is supported through a dedicated word-wide memory bus
with programmable wait states. Additional peripherals
such as serial I/O, 16-bit timers, hardware math accelerator, ISO 7816 UART, and a USB controller increase
system utility while reducing component count.
System security is enhanced by the addition of highspeed cryptographic hardware accelerators for
ECDSA, DSA, RSA, Secure Hash Algorithm, and triplekey 3DES. The embedded hash engine supports multiple hash functions recommended by the National
Institute of Standards and Technology (NIST). The true
hardware random-number generator (RNG) supports
FIPS 186-2 with an available software library.
ABRIDGED DATA SHEET
High-Performance Secure RISC Microcontroller
RANDOM-NUMBER
GENERATOR (RNG)
CRC-16/32
GENERATOR
DES/3DES
USER ENGINE
MULTIPLYACCUMULATE UNIT
SHA
MAXQ1103
INTERNAL
55MHz OSC
2048-BIT MODULO
ARITHMETIC
ACCELERATOR
16K x 16
ROM
RESET
PROG
SDI[1:7]
SDBE
USART 0
TIMER 2
JTAG
256K x 16
FLASH
512 x 16
SRAM
INTERNAL PROGRAM
MEMORY
INTERNAL DATA MEMORY
HIGH/LOW
TEMPERATURE SENSORS
RESET AND
DESTRUCT
RESET
EXTERNAL CODE
INTEGRITY CHECKER
WATCHDOG
INSTRUCTION
CACHE
2K x 16
MAXQ30
PIPELINED
RISC CORE
TIMER 1
TIMER 3
HFXIN
HFXOUT
PORT 2
16K x 16
SRAM
1.5K x 16
SRAM
EDGE INTERRUPTS
POWERSUPPLY
MONITORING
USART 1
MMU
DES/3DES
PROGRAM MEMORY
DECRYPTOR
PLL (4X/2X)
DATA MEMORY
ENCRYPTOR/
DECRYPTOR
DES KEYS
TIMER 0
ISO 7816
UART AND
FIFO
CLOCK
GENERATION
INTERNAL
20MHz OSC
PORT 1
VDDIO (+3.3V)
VDD (+1.8V)
VBAT (+3V)
GND
VDDO
VRST
PF
USB
PORT 3
REAL-TIME
CLOCK
PORT 0
32KIN
32KOUT
GND2
AD[19:0]
PES2
ED[31:0]
PES1
DCS2
DCS2N
DCS1
DCS1N
PCS2
PCS2N
PCS1N
B3
PCS1
B2
B1
B0
R/W
EXTERNAL PROGRAM AND DATA MEMORY INTERFACE
BATTERY BACKED
Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to
www.maxim-ic.com/MAXQ1103 and click on Request Full Data Sheet.
______________________________________________________________________________________
15
MAXQ1103
Functional Diagram