MAXIM MAX17035ETG+

19-4817; Rev 0; 7/09
TION KIT
EVALUA
LE
IL
AVA AB
High-Frequency,
Low-Cost SMBus Chargers
Features
S Low-Cost SMBus Charger
S High Switching Frequency (1.2MHz, 0.85MHz,
0.5MHz)
S Internal Boost Switches
S SMBus-Programmable Charge Voltage, Input
Current Limit, Charge Current, Relearn Voltage,
and Digital IINP Readback
S Single-Point Compensation
S Automatic Selection of System Power Source
Adapter n-channel MOSFETs Driven by an Internal Dedicated Charge Pump
Adapter Soft-Start
S ±0.4% Accurate Charge Voltage
S ±2.5% Accurate Input Current Limiting
S ±3% Accurate Charge Current
S Monitor Outputs for
AC Adapter Current (±2% Accuracy)
Battery Discharge Current (±2% Accuracy)
AC Adapter Presence
S AC Adapter Overvoltage Protection
S 11-Bit Battery Voltage Setting
S 6-Bit, Charge-Current Setting/Input Current Setting
S Improved IINP Accuracy at Low Input Current
The MAX17035/MAX17435/MAX17535 are available in
a small, 4mm x 4mm x 0.75mm 24-pin, lead-free QFN
package. An evaluation kit is available.
Applications
Notebook Computers
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX17035ETG+*
-40NC to +85NC
24 TQFN-EP**
MAX17435ETG+
-40NC to +85NC
24 TQFN-EP**
-40NC
MAX17535ETG+*
to +85NC
24 TQFN-EP**
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
**EP = Exposed pad.
Pin Configuration
PDAs and Mobile Communicators
2- to-4 Li+ Cell Battery-Powered Devices
IINP
CC
CSSP
TOP VIEW
18
17
16
BATT
The MAX17035 operates with a switching frequency of
1.2MHz. The MAX17435 switches at 850kHz, and the
MAX17535 switches at 500kHz.
CSSN
The MAX17035/MAX17435/MAX17535 provide a digital
output that indicates the presence of the adapter, an
analog output that indicates the adapter or battery
current, depending upon the presence or absence of
the adapter, and a digital output that indicates when the
adapter current exceeds a user-defined threshold.
PDSL
The MAX17035/MAX17435/MAX17535 provide up to 7A
of charge current to 2, 3, or 4 lithium-ion (Li+) cells in
series. The charge current, and input current-limit sense
amplifiers have low offset errors and can use 10mI
sense resistors. The MAX17035/MAX17435/MAX17535
fixed-inductor ripple architecture significantly reduces
component size and circuit cost.
15
14
13
ACIN 19
12 CSIP
ITHR 20
11 CSIN
VAA 21
10 ACOK
MAX17035
MAX17435
MAX17535
VCC 22
GND 23
1
2
3
4
5
6
SCL
SDA
DCIN
LDO
DLO
ADAPTLIM
EN 24
9
DH
8
LX
7
BST
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX17035/MAX17435/MAX17535
General Description
The MAX17035/MAX17435/MAX17535 integrated multichemistry battery chargers IC simplify construction
of accurate and efficient chargers. The MAX17035/
MAX17435/MAX17535 provide SMBusK-programmable
charge current, charge voltage, input current limit, relearn
voltage, and digital readback of the IINP voltage. The
MAX17035/ MAX17435/MAX17535 utilize a charge pump
to control the adapter selection n-channel MOSFETs
when the adapter is present. When the adapter is absent,
the charge pump is shut down and a p-channel MOSFET
selects the battery.
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
ABSOLUTE MAXIMUM RATINGS
DCIN, CSSP, BATT, CSIP to GND.......................... -0.3V to +28V
CSIP to CSIN, CSSP to CSSN............................... -0.3V to +0.3V
VCC, SCL, SDA, VAA, EN, ACIN, ITHR,
ADAPTLIM, ACOK to GND................................... -0.3V to +6V
PDSL to GND.......................................................... -0.3V to +37V
GND to PGND ...................................................... -0.3V to +0.3V
DHI to LX...................................................-0.3V to (VBST + 0.3V)
BST to LX.................................................................. -0.3V to +6V
BST to GND............................................................ -0.3V to +34V
DLO to PGND........................................... -0.3V to (VLDO + 0.3V)
LX to GND ................................................................ -6V to +28V
CC, IINP to GND....................................... -0.3V to (VLDO + 0.3V)
LDO Short Circuit to GND.......................................... Momentary
Continuous Power Dissipation (TA = +70NC)
24-Pin, 4mm x 4mm Thin QFN
(derate 20.8mW/NC above +70NC).............................1666mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s)..................................+300NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Charging enabled,
VADAPTER = 19V,
VBATTERY = 16.8V
3
6
mA
Charging disabled
1.5
2.2
mA
INPUT SUPPLIES
Adapter Present Quiescent
Current (Note 1)
IDCIN + ICSSP +
ICSSN + IVCC
VBATT = 16.8V
BATT + CSIP + CSIN +
LX Input Current
DCIN Input Current
IDCIN
VCC Supply Current
ICC
Adapter absent or
charger shut down
(Note 1)
FA
VBATT = 2V to 19V, adapter present (Note 1)
200
650
Charger disabled
0.7
1.0
mA
Charger added
1.5
2.5
mA
26
V
DCIN Input-Voltage Range
for Charger
DCIN Undervoltage-Lockout
Trip Point for Charger
1.5
8
VDCIN falling
7
VDCIN rising
DCIN Input-Voltage Range
7.2
7.7
8
7.9
24
V
V
CHARGE-VOLTAGE REGULATION
ChargingVoltage() = 0x41A0
Battery Full-Charge Voltage
and Accuracy
ChargingVoltage() = 0x3130
ChargingVoltage() = 0x20D0
ChargingVoltage() = 0x1060
Battery Undervoltage-Lockout
Trip Point for Trickle Charge
16.733
16.8
-0.4
12.516
12.592
-0.6
8.333
8.4
-0.8
4.15
4.192
-1.0
3
3.5
2 _______________________________________________________________________________________
16.867
V
+0.4
%
12.668
V
+0.6
%
8.467
V
+0.8
%
4.234
V
+1.0
%
4
V
High-Frequency,
Low-Cost SMBus Chargers
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
78.22
80.64
83.06
mV
RS2 = 10mI, Figure 1;
ChargingCurrent()= 0x1f80
7.822
8.064
8.306
A
+3
%
RS2 = 10mI, Figure 1;
ChargingCurrent()= 0x0f80
3.829
CHARGE-CURRENT REGULATION
CSIP-to-CSIN Full-Scale
Current-Sense Voltage
Charge Current and Accuracy
RS2 = 10mI, Figure 1;
ChargingCurrent()= 0x0080
Based on ChargeCurrent() = 128mA and
8.064A
Charge-Current Gain Error
-3
3.968
-3.5
64
128
4.107
A
+3.5
%
192
mA
-50
+50
%
-2
+2
%
113.3
mV
+2.5
%
65.92
mV
INPUT CURRENT REGULATION
RS1 = 10mW, Figure 1, InputCurrent() = full
scale
Input Current-Limit Threshold
RS1 = 10mW, Figure 1, InputCurrent() = 0C80
RS1 = 10mW, Figure 1, InputCurrent() = 0780
CSSP/CSSN Input-Voltage Range
106.7
110
-2.5
62.08
64
-3
36.86
38.4
-4
8
IINP Voltage Gain
VCSSP - VCSSN = 110mV
IINP Accuracy
%
39.94
mV
+4
%
26
V
20.3
V/V
0
4.2
V
-5
+5
19.7
IINP Output-Voltage Range
+3
19.85
VCSSP - VCSSN = 55mV
-4
+4
VCSSP - VCSSN = 5mV
-10
+10
%
IINP Gain Error
Based on VCSSP - VCSSN = 110mV and
VCSSP - VCSSN = 55mV
-1.5
+1.5
%
IINP Offset Error
Based on VCSSP - VCSSN = 110mV and
VCSSP - VCSSN = 55mV
-350
+350
FV
IREF = 50FA
4.082
4.096
4.115
V
3.1
3.9
V
REFERENCE
REF Output Voltage
REF
REF Undervoltage-Lockout
Threshold
REF falling
LINEAR REGULATOR
LDO Output Voltage
LDO
IREF = 50FA
LDO Load Regulation
0 < ILDO < 40mA
LDO Undervoltage-Lockout
Threshold
LDO falling
5.25
3.2
5.4
5.6
V
127
250
mV
4.1
5.0
V
_______________________________________________________________________________________ 3
MAX17035/MAX17435/MAX17535
ELECTRICAL CHARACTERISTICS (continued)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
ACOK
ACOK Sink Current
ACOK Leakage Current
ACIN
CONDITIONS
VACOK = 0.4V, ACIN = 2.5V
MIN
MAX
1
1.465
ACIN Threshold Hysteresis
1.485
1.53
20
ACIN Falling Delay
UNITS
mA
1
VACOK = 5.5V, ACIN = 0.5V, TA = +25NC
ACIN Threshold
ACIN Input-Bias Current
TYP
FA
V
mV
10
Fs
TA = +25NC
-1
+1
ITHR Leakage Current
VITHR = 0V to LDO, TA = +25NC
-1
+1
ADAPTLIM Sink Current
VITHR > VIINP
1
ADAPTLIM Leakage Current
VITHR < VIINP, TA = +25NC
ITHR Threshold
Calculated = VITHR - VIINP
FA
ITHR/ADAPTLIM
FA
mA
-12
1
FA
+12
mV
0.8
V
LOGIC LEVELS
SDA/SCL Input Low Voltage
SDA/SCL Input High Voltage
SDA/SCL Input-Bias Current
2.1
V
TA = +25NC
-1
+1
VDCIN = 19V, VBATT = 10V, MAX17035
29
35
41
VDCIN = 19V, VBATT = 10V, MAX17435
47
52
57
VDCIN = 19V, VBATT = 10V, MAX17535
80
87
94
FA
SWITCHING REGULATOR
DHI Off-Time K Factor
ns/V
Sense Voltage for Minimum
Discontinuous Mode
Ripple Current
VCSIP - VCSIN
5
mV
Zero-Crossing Comparator
Threshold
VCSIP - VCSIN
5
mV
Cycle-by-Cycle Current-Limit
Sense Voltage
VCSIP - VCSIN
DHI Resistance High
120
125
130
mV
IDHI = 10mA
1.5
3
I
DHI Resistance Low
IDHI = -10mA
0.8
1.6
I
DLO Resistance High
IDLO = 10mA
3
6
I
DLO Resistance Low
IDLO = -10mA
3
6
I
ADAPTER DETECTION
Adapter Absence Detect
Threshold
VDCIN - VBATT, VDCIN falling
50
120
200
mV
Adapter Detect Threshold
VDCIN - VBATT, VDCIN rising
340
430
600
mV
CHARGE-PUMP MOSFET DRIVER
PDSL Gate-Driver Source Current
PDSL Gate-Driver Output Voltage
High
VPDSL - VDCIN = 3V, VDCIN = 19V
VDCIN = 19V, open load
40
64
FA
VDCIN
+ 5.3
VDCIN
+8
V
4 _______________________________________________________________________________________
High-Frequency,
Low-Cost SMBus Chargers
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2
2.1
UNITS
ADAPTER OVERVOLTAGE PROTECTION
ACOVP Threshold
Rising
2.04
ACOVP Threshold Hysteresis
V
30
mV
144
mV
16
ms
0.6
s
ADAPTER OVERCURRENT PROTECTION
ACOCP Threshold
With respect to VCSSP - VCSSN
ACOCP Blanking Time
When ACOCP comparator is high and at the
time the blanking time expires
ACOCP Waiting Time
PDSL SWITCH CONTROL
PDSL Turn-Off Resistance
2.5
4
kI
100
kHz
SMBus TIMING SPECIFICATIONS
SMBus Frequency
fSMB
10
Bus Free Time
tBUF
4.7
Fs
START Condition Hold Time
from SCL
tHD:STA
4
Fs
START Condition Setup Time
from SCL
tSU:STA
4.7
Fs
STOP Condition Setup Time
from SCL
tSU:STO
4
Fs
Holdup Time from SCL
tHD:DAT
300
ns
Setup Time from SCL
tSU:DAT
250
ns
SCL Low Period
tLOW
4.7
Fs
SCL High Period
tHIGH
4
Fs
Maximum Charging Period
Without a Charge_Voltage() or
ChargeCurrent() Command
140
175
210
s
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Charging enabled,
VADAPTER = 19V,
VBATTERY = 16.8V
6
mA
Charging disabled
2.2
mA
INPUT SUPPLIES
Adapter Present Quiescent
Current
IDCIN + ICSSP +
ICSSN (Note 1)
_______________________________________________________________________________________ 5
MAX17035/MAX17435/MAX17535
ELECTRICAL CHARACTERISTICS (continued)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
IDCIN
DCIN Standby Supply Current
VCC Supply Current
ICC
MAX
1.5
VBATT = 2V to 19V, adapter present (Note 1)
650
UNITS
FA
Charger disabled
1
DCIN = 5V to 26V
300
FA
Charger enabled
2.5
mA
26
V
DCIN Input-Voltage Range
for Charger
DCIN Undervoltage-Lockout
Trip Point for Charger
MIN
Adapter absent or charger
shut down (Note 1)
VBATT = 16.8V
BATT + CSIP + CSIN + LX Input
Current
DCIN Input Current
CONDITIONS
8
VDCIN falling
7
VDCIN rising
DCIN Input-Voltage Range
7.9
8
24
mA
V
V
CHARGE-VOLTAGE REGULATION
16.73
16.87
V
-0.416
+0.416
%
12.516
12.668
V
-0.6
+0.6
%
8.333
8.467
V
-0.8
+0.8
%
4.15
4.234
V
-1.0
+1.0
%
3
4
V
78.22
83.06
mV
RS2 = 10mI, Figure 1;
ChargingCurrent() = 0x1f80
7.822
8.306
A
-3
+3
%
RS2 = 10mI, Figure 1;
ChargingCurrent()= 0x0f80
3.829
4.107
A
-3.5
+3.5
%
ChargingVoltage() = 0x41A0
Battery Full-Charge Voltage
and Accuracy
ChargingVoltage() = 0x3130
ChargingVoltage() = 0x20D0
ChargingVoltage() = 0x1060
Battery Undervoltage-Lockout
Trip Point for Trickle Charge
CHARGE-CURRENT REGULATION
CSIP-to-CSIN Full-Scale
Current-Sense Voltage
Charge Current and Accuracy
RS2 = 10mI, Figure 1;
ChargingCurrent() = 0x0080
Charge-Current Gain Error
Based on ChargeCurrent() = 128mA and
8.064A
64
192
mA
-50
+50
%
-2
+2
%
6 _______________________________________________________________________________________
High-Frequency,
Low-Cost SMBus Chargers
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
RS1 = 10mI, Figure 1;
InputCurrent() = full scale
106.7
113.3
mV
-2.5
+2.5
%
RS1 = 10mI, Figure 1;
InputCurrent()= 0C80
62.08
65.92
mV
-3
+3
%
RS1 = 10mI, Figure 1;
InputCurrent()= 0780
36.86
39.94
mV
-4
+4
%
8
26
V
19.7
20.3
%
0
4
V
-5
+5
INPUT CURRENT REGULATION
Input Current-Limit Threshold
CSSP/CSSN Input Voltage Range
IINP Voltage Gain
IINP Output-Voltage Range
VCSSP - VCSSN = 110mV
IINP Accuracy
VCSSP - VCSSN = 55mV
-4
+4
VCSSP - VCSSN = 5mV
-10
+10
%
IINP Gain Error
Based on VCSSP - VCSSN = 100mV
and VCSSP - VCSSN = 20mV
-1
+1
%
IINP Offset Error
Based on VCSSP - VCSSN = 100mV
and VCSSP - VCSSN = 5mV
-500
+500
FV
IREF = 50FA
4.075
4.115
V
3.9
V
REFERENCE
REF Output Voltage
REF
REF UndervoltageLockout Threshold
REF falling
LINEAR REGULATOR
LDO Output Voltage
LDO
IREF = 50FA
LDO Load Regulation
0 < ILDO < 40mA
LDO Undervoltage-Lockout
Threshold
LDO falling
ACOK
ACOK Sink Current
ACIN
VACOK = 0.4V, ACIN = 2.5V
ACIN Threshold
5.25
3.2
5.6
V
250
mV
5.0
V
1
1.465
mA
1.53
V
ACIN Threshold Hysteresis
30
50
mV
ACIN Input-Bias Current
-1
+1
FA
1
FA
ITHR/ADAPTLIM
ITHR Leakage Current
VITHR = 0 to 5.4V
ADAPTLIM Sink Current
VITHR > VIINP
ADAPTLIM Leakage Current
VITHR < VIINP
ITHR Threshold
Calculated = VITHR - VIINP
1
-12
mA
1
FA
+12
mV
_______________________________________________________________________________________ 7
MAX17035/MAX17435/MAX17535
ELECTRICAL CHARACTERISTICS (continued)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
0.8
V
LOGIC LEVELS
SDA/SCL Input Low Voltage
SDA/SCL Input High Voltage
2.1
V
SDA/SCL Input-Bias Current
-1
FA
SWITCHING REGULATOR
VDCIN = 19V, VBATT = 10V, MAX17035
29
41
VDCIN = 19V, VBATT = 10V, MAX17435
47
57
VDCIN = 19V, VBATT = 10V, MAX 17535
80
94
Cycle-by-Cycle Current-Limit
Sense Voltage
VCSIP - VCSIN
120
130
mV
DHI Resistance High
IDHI = 10mA
3
I
DHI Resistance Low
IDHI = -10mA
1.6
I
DLO Resistance High
IDLO = 10mA
6
I
DLO Resistance Low
IDLO = -10mA
6
I
DHI Off-Time K Factor
ns/V
ADAPTER DETECTION
Adapter Absence Detect
Threshold
Adapter Detect Threshold
CHARGE-PUMP MOSFET DRIVER
PDSL Gate-Driver
Output-Voltage High
VDCIN - VBATT, VDCIN falling
50
200
mV
VDCIN - VBATT, VDCIN rising
340
570
mV
VDCIN = 19V
VDCIN
+ 5.3
V
ADAPTER OVERVOLTAGE PROTECTION
ACOVP Threshold
Rising
2.04
2.1
V
4
kI
100
kHz
PDSL SWITCH CONTROL
PDSL Turn-Off Resistance
SMBus TIMING SPECIFICATIONS
SMBus Frequency
fSMB
10
Bus Free Time
tBUF
4.7
Fs
START Condition Hold Time
from SCL
tHD:STA
4
Fs
START Condition Setup Time
from SCL
tSU:STA
4.7
Fs
STOP Condition Setup Time
from SCL
tSU:STO
4
Fs
8 _______________________________________________________________________________________
High-Frequency,
Low-Cost SMBus Chargers
(Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Hold Time from SCL
tHD:DAT
300
ns
Setup Time from SCL
tSU:DAT
250
ns
SCL Low Period
tLOW
4.7
Fs
SCL High Period
tHIGH
4
Fs
Maximum Charging Period
Without a Charge_Voltage() or
ChargeCurrent() Command
140
210
s
Note 1: Adapter Present conditions are tested at VDCIN = 19V and VBATT = 16.8V. Adapter Absent conditions are tested at VDCIN
= 16V, VBATT = 16.8V.
Note 2: Specifications to -40°C are guaranteed by design and not production tested.
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 19V, VCC = VDD = 5V, EN = VCC, TA = +25NC, unless otherwise specified.)
INPUT CURRENT-LIMIT ERROR
vs. INPUT CURRENT-LIMIT SETTING
10
8
6
4
2
0
VBATT = 8.4V
-1.0
-2.0
-2.5
VBATT = 12.6V
-3.0
0
2
4
6
INPUT CURRENT-LIMIT SETTING (A)
8
15
10
VADAPTER = 20V
VADAPTER = 0V, VBATT = 15V
5
VBATT = 16.8V
0
INPUT CURRENT LIMIT = 3.584A
-5
-4.0
-4
25
20
-1.5
-3.5
-2
MAX17035 toc03
-0.5
30
IINP ERROR (%)
12
0
MAX17035 toc02
14
INPUT CURRENT-LIMIT ERROR (%)
MAX17035 toc01
INPUT CURRENT-LIMIT ERROR (%)
16
IINP ERROR vs. SYSTEM CURRENT
(DC SWEEP)
INPUT CURRENT-LIMIT ERROR
vs. SYSTEM CURRENT
0
1
2
SYSTEM CURRENT (A)
3
4
0
20
40
60
VCSSP - VCSSN (mV)
_______________________________________________________________________________________ 9
MAX17035/MAX17435/MAX17535
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 19V, VCC = VDD = 5V, EN = VCC, TA = +25NC, unless otherwise specified.)
CHARGER-CURRENT ERROR
vs. BATTERY VOLTAGE
2.0
1.5
1.0
VBATT = 16.8V
0.5
0
0
1
2.0
2
3
ICHARGER = 5A
1.5
ICHARGER = 3A
1.0
ICHARGER = 4A
0.5
7
6
5
4
3
2
1
0
-0.5
4
3
SYSTEM CURRENT (A)
8
13
2
18
CHARGER VOLTAGE ERROR
vs. CHARGER CURRENT
0.10
0.05
0
-0.05
0.2
-0.10
MAX17035 toc09
MAX17035 toc08
MAX17035 toc07
0.15
BATTERY REMOVAL
(VBATT = 3V )
0.3
CHARGER VOLTAGE ERROR (%)
0.20
6
4
INPUT CURRENT-LIMIT SETTING (A)
BATTERY VOLTAGE (V)
CHARGE VOLTAGE
ACCURACY AT 3.854A
0.1
0
VBATT = 16.8V
-0.1
VBATT = 8.4V
PDSL
5V/div
VBATT
5V/div
DCIN
5V/div
VBATT = 12.6V
-0.2
-0.3
IL
1A/div
-0.4
-0.5
-0.6
-0.7
-0.15
0
5
10
15
0
20
2
4
6
CHARGE VOLTAGE (V)
CHARGER CURRENT (A)
SYSTEM LOAD TRANSIENT
(0A
3A
0A )
CHARGE-OUTPUT SHORT CIRCUIT
MAX17035 toc10
100Fs/div
EFFICIENCY vs. CHARGE CURRENT
(2, 3, AND 4 CELLS)
MAX17035 toc11
100
IL
1A/div
4 CELL
95
3 CELL
VBATT
5V/div
CC
1V/div
ISYSLD
1A/div
IL
2A/div
EFFICIENCY (%)
90
VBATT
200mV/div
MAX17035 toc12
ERROR (%)
8
0
VBATT = 8.4V
VBATT = 12.6V
-5.0
2.5
9
MAX17035 toc06
2.5
3.0
CHARGER-CURRENT ERROR (%)
3.0
CHARGER-CURRENT ERROR
vs. SMBS SETTING
MAX17035 toc05
INPUT CURRENT LIMIT = 3.584A
CHARGER-CURRENT ERROR (%)
3.5
MAX17035 toc04
IINP ERROR vs. SYSTEM CURRENT
IINP ERROR (%)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
85
2 CELL
80
75
70
65
60
0A
1ms/div
20Fs/div
55
50
0
1
2
3
4
CHARGE CURRENT (A)
10 �������������������������������������������������������������������������������������
5
6
High-Frequency,
Low-Cost SMBus Chargers
(Circuit of Figure 1, VIN = 19V, VCC = VDD = 5V, EN = VCC, TA = +25NC, unless otherwise specified.)
VAA DEVIATION, SWITCHING
AND NOT SWITCHING
5.42
5.40
MAX17035 toc14
0.5
0
SWITCHING
-0.5
-1.0
5.36
4.110
4.105
VAA VOLTAGE (V)
1.0
5.44
5.38
NOT SWITCHING
4.100
4.095
4.090
4.085
-1.5
4.080
-2.0
5.34
0
10
20
30
40
0
50
5
10
15
20
25
LDO CURRENT (mA)
DCIN (V)
FREQUENCY
vs. VBATT AT 4A ICHG
POWER-SOURCE SELECTOR SCHEME
WITH BATTERY PRESENT
(ADAPTER REMOVAL)
900
800
30
-40
-20
0
20
40
700
500
400
80
100
POWER-SOURCE SELECTOR SCHEME
WITH BATTERY PRESENT
(ADAPTER INSERTION)
MAX17035 toc18
PDSL
5V/div
PDSL
5V/div
VADAPTER
5V/div
VSYSLD
5V/div
VBATT
5V/div
600
60
TEMPERATURE (NC)
MAX17035 toc17
MAX17035 toc16
1000
FREQUENCY (kHz)
1.5
DEVIATION (mV)
LDO VOLTAGE (V)
5.46
VAA vs. TEMPERATURE
2.0
MAX17035 toc13
5.48
MAX17035 toc15
LDO VOLTAGE
vs. LDO CURRENT
VSYSLD
5V/div
VBATT
5V/div
MAX17035/MAX17435/MAX17535
Typical Operating Characteristics (continued)
300
200
VADAPTER
5V/div
100
0
0
5
10
15
20
10ms/div
40ms/div
VBATT (V)
______________________________________________________________________________________ 11
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
Pin Description
PIN
NAME
1
SCL
SMBus Clock Input. Connect to an external pullup resistor according to SMBus specifications.
2
SDA
SMBus Data I/O. Open-drain output. Connect to an external pullup resistor according to SMBus
specifications.
3
DCIN
Charger Supply Input. Connect to adapter supply. For minimum input bias current connect to the
center of the input/soft-start FETs. Bypass with a 1FF ceramic capacitor to PGND placed close to
the pin. Add a 10W resistor to reduce input surge at adapter insertion.
4
LDO
Linear Regulator Output. This is a 30mA reference and also powers the DLO driver, the BST circuit,
and the internal SMBus circuitry. Bypass with a 1FF ceramic capacitor to PGND placed close to the
pin. This output is disabled when the charger is disabled.
5
DLO
Low-Side Power-MOSFET Driver Output. Connect to low-side n-channel MOSFET gate.
6
ADAPTLIM
7
BST
8
LX
High-Side Driver Source Connection
9
DHI
High-Side Power MOSFET Driver Output. Connect to high-side n-channel MOSFET gate.
10
ACOK
AC Detect Output .This open-drain output is high impedance when ACIN is lower than 1.5V. The
ACOK output remains high when the MAX17035/MAX17435/MAX17535 are powered down. For a
typical application, use a 10kI pullup resistor to LDO (pin 4).
11
CSIN
Output Current-Sense Negative Input. Connect this pin to the negative terminal of the sense resistor.
See the Setting Charge Current section for resistor value and scaling.
12
CSIP
Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN;
the voltage across these two pins is interpreted by the MAX17035/MAX17435/MAX17535 as
proportional to the charge current delivered to the battery with approximately 110mV full-scale
voltage. See the Setting Charge Current section for resistor value and scaling.
13
BATT
Battery Voltage Feedback Input. Connect as close as possible to the battery terminal.
14
PDSL
Power-Source n-Channel MOSFET Switch Driver Output. When the adapter is not present or an
overvoltage event detected at the input, the PDSL output is pulled to GND with a 2.5kW (typ)
resistor. Otherwise, it is typically 8V above the adapter voltage when the part is not using the
battery. This is powered by an internal charge pump.
15
CSSN
Input Current-Sense Negative Input. See the description of the CSSP pin for resistor value and
scaling.
CSSP
Current Sense for Positive Input. Connect a current-sense resistor from CSSP to CSSN. The voltage
across CSSP to CSSN determines the current at which the charger reduces charging current to
keep from drawing more current from the adapter than is allowed. As the system current flowing
in the resistor from CSSN to CSSP increases, the charger reduces charge current to keep the
system current at the limit value. When the system current reaches approximately 130% of the
max programmed value, the PDSL pin changes state and turns off the input FET to prevent excess
current from the adapter. When the adapter overcurrent condition occurs, give a 16ms blanking
time, and then turn off the adapter switch. The adapter switch is turned on again after 0.6s. Try the
same thing one more time. After the third blanking time (16ms), the adapter MOSFETS are latched
in the off state. To release the adapter switch’s off state, adapter removal and reinsertion is needed.
16
FUNCTION
Adaptive System Current-Limit Comparator Output. This open-drain output is high impedance when
the voltage at the IINP pin is lower than the ITHR threshold. For a typical application, use a 10kW
pullup resistor to LDO (pin 4).
High-Side Driver Supply. Connect a 0.1FF capacitor from BST to LX.
12 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
PIN
NAME
17
CC
Voltage Regulation Loop-Compensation Point. Connect a 10nF capacitor from CC to GND.
18
IINP
Input Current-Monitor Output. The voltage at the IINP pin is 20 times the voltage from CSSP to
CSSN. This voltage is present when charging is enabled to monitor the system current, and when
the battery is discharging to monitor the battery discharge current.
ACIN
AC Adapter-Detect Input. ACIN is the input to a comparator with a comparison voltage of about
1.5V. The output of the comparator is ACOK. ACOK goes low when the threshold voltage is
exceeded to indicate that the AC adapter is present, and it enables the charger. When the ACIN
input is above 2.1V, the MAX17035/MAX17435/MAX17535 interpret that as an adapter overvoltage
event. The charger is then disabled and the adapter MOSFETs are turned off. If the part is charging
and the ACIN voltage drops below the programmed threshold, the charger is disabled and a
ChargeCurrent() and ChargeVoltage() command have to be written over the SMBus to reenable the
charger.
20
ITHR
Adaptive System Current-Limit Comparator Threshold. This pin connects to the inverting input of a
comparator. The noninverting input of the comparator is the IINP input, while the output is driving
the ADAPTLIM open drain. When the input to ITHR is greater than IINP, the ADAPTLIM output is
high.
21
VAA
4.096V Internal Reference Voltage; No External Load Allowed. Bypass to analog ground using a 1FF
or greater ceramic capacitor.
22
VCC
Circuitry Supply-Voltage Input. Connect to LDO through 10I and bypass with a 0.1FF capacitor to
GND as close as possible to the package pin.
23
GND
Analog Ground
24
EN
Enable/Disable Charger Operation. This disables the charger and associated circuitry when EN
goes low and is in addition to the ACOK charger enable. If the adapter is absent and EN is pulled
up to a voltage higher than 2.4V, the battery-discharge current monitor on IINP is enabled.
—
EP
Exposed Pad. Connect backside exposed pad to power ground.
19
FUNCTION
______________________________________________________________________________________ 13
MAX17035/MAX17435/MAX17535
Pin Description (continued)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
Q1B
R9
103kI
R9
2MI
RS1
10mI
Q1A
N3
ADAPTER
R4
150kI
C6
10nF
R17
10I
SYSTEM LOAD
R18
1kI
CIN
N4
C10
1FF
GND
DCIN
PDSL
CSSP
CSSN
ACIN
BST
DHI
R10
10kI
C4
0.1FF
LX
DLO
C1
1FF
R16
10I
R14
10kI
L1
PGND PAD
R5
10kI
R13
10kI
N2
ACOK
ACOK
LDO
C IN = 2 x 4.7FF
C OUT = 4.7FF
L1 = 2FH
N1
LDO
MAX17035
RS2
10mI
CSIP
CSIN
BATT
VAA
C3
1FF
C11
1FF
CC
GND
IINP
VCC
BATTERY
IINP VOLTAGE
C2
0.1FF
LDO
R7
10kI
SCL
SDA
SMBus
CONTROL
COUT
C5
0.01FF
ADAPTER
CURRENT
LIMIT FLAG
ADAPTLIM
ITHR
EN
R12
10kI
LDO
R6
7.06kI
R8
49.9kI
LDO
Figure 1. Standard Application Circuit
Detailed Description
The MAX17035/MAX17435/MAX17535 charger includes
all the functions necessary to charge Li+, NiMH, and
NiCd smart batteries. A high-efficiency synchronous
rectified step-down DC-DC converter is used to
implement a constant-current constant-voltage charger.
The DC-DC converter drives a high-side n-channel
MOSFET and provides synchronous rectification with a
low-side n-channel MOSFET. The charge current and
input current-sense amplifiers have low-input offset
errors (200FV typ), allowing the use of small-valued
sense resistors. The MAX17035/MAX17435/MAX17535
use an SMBus interface similar to the MAX8731A to
set charge current, charge voltage, and input current
limit. In addition, the MAX17035/MAX17435/MAX17535
SMBus interface supports RELEARN(), and IINPVoltage()
readback.
14 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
PGND
LDO
DHI
BST
DCIN
DLO
LX LDO
PGND
ADAPTER
PRESENT
5.4V
REGULATOR
LOW-SIDE
DRIVER
HIGH-SIDE
DRIVER
CSIN
CSSP
A = 20V/V
CURRENTSENSE
AMPLIFIER
BATTERY
CSSN
GMS
DCIN
VAA
CSIP
4.096V
REFERENCE
ACOVP
CHARGE
VOLTAGE()
+200mV
IN_SET
MAX17035
AC_EN
GMI
CURRENTSENSE
AMPLIFIER
EN
DC-DC
CONVERTER
IMAX
CSI
CCMP
IMIN
128mA
12A
CSIN
ZCMP
BDIV
BATT
LVC AND CAP
SWITCH LOGIC
GMV
ADAPTLIM
CHG_EN
IINP
SCL
SDA
SMBus LOGIC
CHARGE VOLTAGE()
RELEARN()
CHARGE CURRENT()
INPUT CURRENT()
CC
AC_EN
11-BIT DAC VCTL
6-BIT ISET
7-BIT IN_SET
6-BIT READBACK
PDSL LOGIC
1.5V
ACIN
ACOK
ITHR
PDSL
Figure 2. Block Diagram
The MAX17035/MAX17435/MAX17535 control input
current (CCS control loop), charge current (CCI control
loop), or charge voltage (CCV control loop), depending
on the operating condition. The three control loops,
CCV, CCI, and CCS, are brought together internally at
the lowest voltage clamp (LVC) amplifier. The output of
the LVC amplifier is the feedback control signal for the
DC-DC controller. The minimum voltage at the CCV,
CCI, or CCS appears at the output of the LVC amplifier
and clamps the other control loops to within 0.3V above
the control point. Clamping the other two control loops
close to the lowest control loop ensures fast transition
with minimal overshoot when switching between different
control loops (see the Compensation section). The
CCI loop is internally compensated and the CCV and
CCS loops share a common compensation network at
CC. The dominant control loop (CCV, CCS) drives the
compensation network.
______________________________________________________________________________________ 15
MAX17035/MAX17435/MAX17535
IINP
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
Table 1. EN Pin Function
ADAPTER
PRESENT
EN
PDSL STATUS
CHARGER STATUS
SYSTEM CURRENT MONITOR
STATUS (IINP PATH)
Yes
High
PDSL is pumped 8V above the DCIN
voltage (charge pump on).
Enabled
Enabled
Yes
Low
PDSL is pumped 8V above the DCIN
voltage (charge pump on).
Disabled
Enabled
No
High
Charge pump is off and PDSL is
forced to 0V (typ, 27C).
Disabled
Enabled
No
Low
Charge pump is off and PDSL is
forced to 0V (typ, 27C).
Disabled
Disabled
EN Pin
The EN pin is a logic input. The state of the EN pin and
the presence or absence of the adapter determines the
state of PDSL, the IINP path, and the charger function as
shown in Table 1.
30mA LDO
The 5.4V LDO is powered from DCIN and is compensated
for loads from 0 to 30mA with a single 1FF ceramic
capacitor. The load regulation over the 30mA load is
34mV (typ), 100mV max. The LDO supplies the drive for
the DLO driver and also the BST circuitry. It is shut down
when the adapter is absent.
Analog Input Current Monitor Output
IINP monitors the system-input current sensed across the
sense resistor (RS1) that connects between CSSP and
CSSN. The voltage at IINP is proportional to the input
current according to the following equation:
IINPUT =
VIINP
RS1× A
where IINPUT is the DC current supplied by the AC
adapter and A is the gain (20V/V typ). IINP has a 0V to
2.2V output-voltage range.
Table 1 shows the charge and IINP status when the
adapter is present or absent and as a function of the
EN pin. When connected as shown in the standard
application circuit, IINP monitors the input system
current when the adapter is present or the battery
discharge current when the adapter is absent. Leave
IINP unconnected if not used.
Table 2 is the fault-protection and shutdown operation
table.
SMBus Implementation
TheMAX17035/MAX17435/MAX17535receivecontrol inputs
from the SMBus interface. The MAX17035/MAX17435/
Table 2. Fault Protection and Shutdown
Operation Table
MODE
CONTROLLER
STATE
DRIVER
STATE
Thermal Fault
(Latched, Reset with
Adapter Insertion)
Charger
disabled
DHI and DLO
low
MAX17535 use a subset of the commands documented
in the System Management Bus Specifications V2.0,
which can be downloaded from www.smbus.org. The
MAX17035/MAX17435/MAX17535 use the SMBus readword and write-word protocols to communicate with the
system controller. The MAX17035/MAX17435/MAX17535
operate only as slave devices with address 0b0001001_
(0x12) and do not initiate communication on the bus. In
addition, the MAX17035/MAX17435/MAX17535 have
two identification registers: (0xFE), a 16-bit device ID
register and a 16-bit manufacturer ID register (0xFF).
The SMBus implementation is similar to the MAX8731A
with the addition of the RELEARN() and IINPVoltage()
commands. The SMBus is not powered from an external
supply, so during states that disable the charger, the
SMBus register data is lost, so the register data must be
rewritten when reenabled. See Figure 3.
The data (SDA) and clock (SCL) pins have Schmitttrigger inputs that can accommodate slow edges.
Choose pullup resistors for SDA and SCL to achieve rise
times according to the SMBus specifications.
Communication starts when the master signals a
START condition, which is a high-to-low transition on
SDA, while SCL is high. When the master has finished
communicating, the master issues a STOP condition,
which is a low-to-high transition on SDA, while SCL
is high. The bus is then free for another transmission.
16 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
sampled on the rising edge of SCL. Nine clock cycles are
required to transfer each byte in or out of the MAX17035/
MAX17435/MAX17535 because either the master or the
slave acknowledges the receipt of the correct byte during
the ninth clock. The MAX17035/MAX17435/MAX17535
support the charger commands as described in Table 4.
a) Write-Word Format
S
SLAVE
W
ADDRESS
7 bits
1b
MSB
LSB 0
COMMAND
BYTE
8 bits
MSB
LSB
ACK
1b
0
PRESET TO
0b0001001
ACK
1b
0
Relearn () = 0x3D
ChargingCurrent() = 0x14
ChargerVoltage() = 0x15
LOW DATA
BYTE
8 bits
MSB
LSB
D7
ACK
1b
0
D0
HIGH DATA
BYTE
8 bits
MSB
LSB
D15
ACK P
1b
0
D8
b) Read-Word Format
S
SLAVE
W
ADDRESS
7 bits
1b
MSB
LSB 0
COMMAND
BYTE
8 bits
MSB
LSB
ACK
1b
0
PRESET TO
0b0001001
ACK
1b
0
S
SLAVE
ADDRESS
7 bits
MSB
LSB
R
ACK
1b
1
1b
0
PRESET TO
0b0001001
INP_Voltage () = 0x3E
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
LOW DATA
BYTE
8 bits
MSB
LSB
D7
ACK
1b
0
HIGH DATA
BYTE
8 bits
MSB
LSB
D0
D15
H
I
NACK P
1b
1
D8
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 3. SMBus Write-Word and Read-Word Protocols
A
tLOW
B
tHIGH
C
D
E
F
G
J
K
L
M
SMBCLK
SMBDATA
tSU:STA
tHD:STA
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
tSU:DAT
tHD:DAT
tHD:DAT
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
tSU:STO tBUF
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
Figure 4. SMBUs Write Timing
______________________________________________________________________________________ 17
MAX17035/MAX17435/MAX17535
Figures 4 and 5 show the timing diagrams for signals on
the SMBus interface. The address byte, command byte,
and data bytes are transmitted between the START and
STOP conditions. The SDA state is allowed to change
only while SCL is low, except for the START and STOP
conditions. Data is transmitted in 8-bit bytes and is
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
A
tLOW
B
tHIGH
C
D
E
F
G
H
J
I
K
SMBCLK
SMBDATA
tSU:STA tHD:STA
tSU:DAT
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
tHD:DAT
tSU:STO
tSU:DAT
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
tBUF
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
Figure 5. SMBus Read Timing
Battery Charger Commands
Setting Charge Current
The MAX17035/MAX17435/MAX17535 support four
battery-charger commands that use either write-word
or read-word protocols as summarized in Table 3.
ManufacturerID() and DeviceID() can be used to identify
the MAX17035/MAX17435/MAX17535. On the MAX17035/
MAX17435/MAX17535 ManufacturerID() always returns
0x004D and DeviceID() always returns 0x0008.
To set the charge current, use the SMBus to write a
16-bit ChargeCurrent() command using the data format
listed in Table 5. The ChargeCurrent() command uses the
write-word protocol (see Figure 3). The command code for
ChargeCurrent() is 0x14 (0b00010100). When RS2 = 10mI,
the MAX17035/MAX17435/MAX17535 provide a chargecurrent range of 128mA to 11.004A, with 128mA resolution.
If a sense resistor other than 10mI is used, the current
limit must be scaled by RS/10mI, where RS is the sense
resistor value used on the circuit. Set ChargeCurrent() to
0 to terminate charging. Upon reset, the ChargeVoltage()
and ChargeCurrent() values are cleared and the charger
remains off until both the ChargeVoltage() and the
ChargeCurrent() command are sent. Both DHI and DLO
remain low until the charger is restarted.
Setting Charge Voltage
To set the output voltage, use the SMBus to write a
16-bit ChargeVoltage() command using the data format
listed in Table 4. The ChargeVoltage() command uses
the write-word protocol (see Figure 3). The command
code for ChargeVoltage() is 0x15 (0b00010101). The
MAX17035/MAX17435/MAX17535 provide a chargevoltage range of 4.095V to 19.200V, with 16mV resolution.
Set ChargeVoltage() below 4.095V to terminate charging.
Upon reset, the ChargeVoltage() and ChargeCurrent()
values are cleared and the charger remains off until both
the ChargeVoltage() and the ChargeCurrent() command
are sent. Both DHI and DLO remain low until the charger
is restarted.
The MAX17035/MAX17435/MAX17535 include a fault
limiter for low-battery conditions. If the battery voltage
is less than 3V, the charge current is temporarily set to
128mA. The ChargeCurrent() register is preserved and
becomes active again when the battery voltage is higher
than 3V. This function effectively provides a foldback
current limit that protects the charger during short circuit
and overload.
Table 3. Battery Charger Command Summary
COMMAND
COMMAND NAME
READ/WRITE
DESCRIPTION
POR STATE
0x14
ChargeCurrent()
Write only
6-bit charge-current setting
0x0000
0x15
ChargeVoltage()
Write only
11-bit charge-voltage setting
0x0000
0x3D
Relearn Voltage
Read and write
11-bit relearn voltage set and 1 bit enable/status
0x4B00
0x3E
IINPVoltage()
Read only
Digital read of IINP voltage
NA
0x3F
InputCurrent()
Write only
6-bit charge-current setting
0x0080
0xFE
ManufacturerID()
Read only
Manufacturer ID
0x004D
0xFF
DeviceID()
Read only
Device ID
0x0008
18 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
BIT
BIT NAME
DESCRIPTION
0
—
Not used. Normally a 1mV weight.
1
—
Not used. Normally a 2mV weight.
2
—
Not used. Normally a 4mV weight.
3
—
Not used. Normally an 8mV weight.
4
Charge Voltage, DACV 0
0 = Adds 0mV of charger voltage compliance, 4095mV min.
1 = Adds 16mV of charger voltage compliance.
5
Charge Voltage, DACV 1
0 = Adds 0mV of charger voltage compliance, 4095mV min.
1 = Adds 32mV of charger voltage compliance.
6
Charge Voltage, DACV 2
0 = Adds 0mV of charger voltage compliance, 4095mV min.
1 = Adds 64mV of charger voltage compliance.
7
Charge Voltage, DACV 3
0 = Adds 0mV of charger voltage compliance, 4095mV min.
1 = Adds 128mV of charger voltage compliance.
8
Charge Voltage, DACV 4
0 = Adds 0mV of charger voltage compliance, 4095mV min.
1 = Adds 256mV of charger voltage compliance.
9
Charge Voltage, DACV 5
0 = Adds 0mV of charger voltage compliance, 4095mV min.
1 = Adds 512mV of charger voltage compliance.
10
Charge Voltage, DACV 6
0 = Adds 0mA of charger voltage compliance, 4095mV min.
1 = Adds 1024mV of charger voltage compliance.
11
Charge Voltage, DACV 7
0 = Adds 0mV of charger voltage compliance, 4095mV min.
1 = Adds 2048mV of charger voltage compliance.
12
Charge Voltage, DACV 8
0 = Adds 0mV of charger voltage compliance.
1 = Adds 4096mV of charger voltage compliance.
13
Charge Voltage, DACV 9
0 = Adds 0mV of charger voltage compliance.
1 = Adds 8192mV of charger voltage compliance.
14
Charge Voltage, DACV 10
0 = Adds 0mV of charger voltage compliance.
1 = Adds 16384mV of charger voltage compliance, 19200mV max.
15
—
Not used. Normally a 32768mV weight.
Table 5. ChargeCurrent() (0x14) (10mI Sense Resistor, RS2)
BIT
BIT NAME
0
—
Not used. Normally a 1mA weight.
DESCRIPTION
1
—
Not used. Normally a 2mA weight.
2
—
Not used. Normally a 4mA weight.
3
—
Not used. Normally an 8mA weight.
4
—
Not used. Normally a 16mA weight.
5
—
Not used. Normally a 32mA weight.
6
—
Not used. Normally a 64mA weight.
7
Charge Current, DACI 0
0 = Adds 0mA of charger current compliance.
1 = Adds 128mA of charger current compliance.
8
Charge Current, DACI 1
0 = Adds 0mA of charger current compliance.
1 = Adds 256mA of charger current compliance.
______________________________________________________________________________________ 19
MAX17035/MAX17435/MAX17535
Table 4. ChargeVoltage() (0x15)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
Table 5. ChargeCurrent() (0x14) (10mI Sense Resistor, RS2) (continued)
BIT
BIT NAME
DESCRIPTION
9
Charge Current, DACI 2
0 = Adds 0mA of charger current compliance.
1 = Adds 512mA of charger current compliance.
10
Charge Current, DACI 3
0 = Adds 0mA of charger current compliance.
1 = Adds 1024mA of charger current compliance.
11
Charge Current, DACI 4
0 = Adds 0mA of charger current compliance.
1 = Adds 2048mA of charger current compliance.
12
Charge Current, DACI 5
0 = Adds 0mA of charger current compliance.
1 = Adds 4096mA of charger current compliance, 8064mA max
13
—
Not used. Normally a 8192mA weight.
14
—
Not used. Normally a 16386mA weight.
15
—
Not used. Normally a 32772mA weight.
Setting Input-Current Limit
System current normally fluctuates as portions of the
system are powered up or put to sleep. By using the inputcurrent-limit circuit, the output-current requirement of the
AC wall adapter can be lowered, reducing system cost.
The total input current is the sum of the system supply
current, the charge current flowing into the battery, and
the current required by the charger. When the input
current exceeds the input current limit set with the
InputCurrent() command, the MAX17035/MAX17435/
MAX17535 reduce the charge current to provide priority
to system load current. As the system supply current
increases, the charge current is reduced as needed
to maintain the total input current at the input current
limit. The MAX17035/MAX17435/MAX17535 decrease
the charge current to zero, if necessary, to reduce the
input current to the input current limit. Thereafter, if the
system current continues to increase, there is nothing the
MAX17035/MAX17435/MAX17535 can do to maintain the
input current at the input current limit. If the system current
continues to increase the total input current can increase
until the ACOCP threshold (which is 1.3 x maximum
DAC setting) is reached and the MAX17035/MAX17435/
MAX17535 drive PDSL low to remove the input voltage.
The MAX17035/MAX17435/MAX17535 wait 0.6s and
then try to charge again; after a 16ms blanking period if
the current is again over the ACOCP threshold, it again
opens up the input voltage. It goes through this cycle
three times; after three times, the MAX17035/MAX17435/
MAX17535 wait for the adapter voltage to be removed
and reinserted before it reconnects the input voltage.
The total input current can be estimated as follows:
IINPUT = I SYSTEM + I CHARGER +
[(I CHARGE × VBATTERY ) (VIN × η)]
where E is the efficiency of the DC-DC converter (typically
85% to 95%).
To set the input current limit, issue the SMBus command
InputCurrent() using the 16-bit data format listed in
Table 6. The InputCurrent() command uses the writeword protocol (see Figure 3). The command code for
InputCurrent() is 0x3F (0b00111111). When RS1 = 10mI,
the MAX17035/MAX17435/MAX17535 provide an input
current-limit range of 256mA to 11.004A with 256mA
resolution. If a resistor RS other than 10mI is used, the
input current limit is scaled by a factor of 10mI/RS1.
InputCurrent() settings from 1mA to 128mA result in a
current limit of 128mA. Upon reset, the input current limit
is 128mA.
Setting Relearn Voltage
To set the relearn voltage issue, the SMBus command
RelearnVoltage() uses the 16-bit data format listed in
Table 7. The RelearnVoltage() command uses the
write-word and read-word protocols (see Figure 3).
The command code for RelearnVoltage() is 0x3D
(0b00111101). The MAX17035/MAX17435/MAX17535
provide a charge-voltage range of 4.095V to 19.200V
with 16mV resolution. When the relearn function is
enabled by setting bit 0 to 1, the PDSL pin switches off
the input-voltage FET and switches on the battery FET,
enabling discharging of the battery. The battery voltage
is monitored until the battery voltage reaches the relearn
voltage and thus a known low state of charge. The PDSL
state is then reset to allow charging and bit 0 is set to zero.
20 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
BIT
BIT NAME
0
—
Not used. Normally a 2mA weight.
DESCRIPTION
1
—
Not used. Normally a 4mA weight.
2
—
Not used. Normally an 8mA weight.
3
—
Not used. Normally a 16mA weight.
4
—
Not used. Normally a 32mA weight.
5
—
Not used. Normally a 64mA weight.
6
—
Not used. Normally a 128mA weight.
7
Input Current, DACS 0
0 = Adds 0mA of input current compliance.
1 = Adds 256mA of input current compliance.
8
Input Current, DACS 1
0 = Adds 0mA of input current compliance.
1 = Adds 512mA of input current compliance.
9
Input Current, DACS 2
0 = Adds 0mA of input current compliance.
1 = Adds 1024mA of input current compliance.
10
Input Current, DACS 3
0 = Adds 0mA of input current compliance.
1 = Adds 2048mA of input current compliance.
11
Input Current, DACS 4
0 = Adds 0mA of input current compliance.
1 = Adds 4096mA of input current compliance.
12
Input Current, DACS 5
0 = Adds 0mA of input current compliance.
1 = Adds 8192mA of input current compliance, 11004mA max.
13
—
Not used. Normally a 16384mA weight.
14
—
Not used. Normally a 32768mA weight.
15
—
Not used. Normally a 65536mA weight.
Table 7. Relearn() (0x3D)
BIT
BIT NAME
DESCRIPTION
0 = Disables the relearn function.
1 = Enables the relearn function.
When the relearn threshold is crossed as the battery discharges, bit 0
is reset to zero by the MAX17035/MAX17435/MAX17535.
0
Relearn, RL 0
1
—
Not used.
2
—
Not used.
3
—
Not used.
4
Relearn, RL 1
0 = Adds 0mV of relearn threshold compliance, 1024 mV min.
1 = Adds 16mV of relearn threshold compliance.
5
Relearn, RL 2
0 = Adds 0mV of relearn threshold compliance, 1024 mV min.
1 = Adds 32mV of relearn threshold compliance.
6
Relearn, RL 3
0 = Adds 0mV of relearn threshold compliance, 1024 mV min.
1 = Adds 64mV of relearn threshold compliance.
7
Relearn, RL 4
0 = Adds 0mV of relearn threshold compliance, 1024 mV min.
1 = Adds 128mV of relearn threshold compliance.
8
Relearn, RL 5
0 = Adds 0mV of relearn threshold compliance, 1024 mV min.
1 = Adds 256mV of relearn threshold compliance.
______________________________________________________________________________________ 21
MAX17035/MAX17435/MAX17535
Table 6. InputCurrent() (0x3F) (10mI Sense Resistor, RS1)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
Reading IINP Voltage
To read the digital version of the IINP voltage, issue the
SMBus command IINPVoltage() command using the 16
bit data format listed in Table 8. The command code for
IINPVoltage() is 0x3E (0b00111110). The IINPVoltage()
command uses the read-word protocol (see Figure 3).
Charger Timeout
The MAX17035/MAX17435/MAX17535 include a timer
to terminate charging if the charger has not received a
ChargeVoltage() or ChargeCurrent() command within
175s. If a timeout occurs, both ChargeVoltage() and
ChargeCurrent() commands must be sent again to
reenable charging.
Table 7. Relearn() (0x3D) (continued)
BIT
BIT NAME
DESCRIPTION
9
Relearn, RL 6
0 = Adds 0mV of relearn threshold compliance, 1024 mV min.
1 = Adds 512mV of relearn threshold compliance.
10
Relearn, RL 7
0 = Adds 0mA of relearn threshold compliance.
1 = Adds 1024mV of relearn threshold compliance.
11
Relearn, RL 8
0 = Adds 0mV of relearn threshold compliance.
1 = Adds 2048mV of relearn threshold compliance.
12
Relearn, RL 9
0 = Adds 0mV of relearn threshold compliance.
1 = Adds 4096mV of relearn threshold compliance.
13
Relearn, RL 10
0 = Adds 0mV of relearn threshold compliance.
1 = Adds 8192mV of relearn threshold compliance.
14
Relearn, RL 11
0 = Adds 0mV of relearn threshold compliance.
1 = Adds 16384mV of relearn threshold compliance, 19200mV max.
15
—
Not used.
Table 8. IINPVoltage() (0x3E)
BIT
BIT NAME
DESCRIPTION
0
—
Not used. Normally a 1mV weight.
1
—
Not used. Normally a 2mV weight.
2
—
Not used. Normally a 4mV weight.
3
—
Not used. Normally a 8mV weight.
4
—
Not used. Normally a 16mV weight.
5
IINP Voltage, DACV 0
0 = Adds 0mV of IINP voltage.
1 = Adds 12.8mV of IINP voltage.
6
IINP Voltage, DACV 1
0 = Adds 0mV of IINP voltage.
1 = Adds 25.6mV of IINP voltage.
7
IINP Voltage, DACV 2
0 = Adds 0mV of IINP voltage.
1 = Adds 51.2mV of IINP voltage.
8
IINP Voltage, DACV 3
0 = Adds 0mV of IINP voltage.
1 = Adds 102.4mV of IINP voltage.
9
IINP Voltage, DACV 4
0 = Adds 0mV of IINP voltage.
1 = Adds 204.8mV of IINP voltage.
10
IINP Voltage, DACV 5
0 = Adds 0mA of IINP voltage.
1 = Adds 409.6mV of IINP voltage.
22 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
BIT
BIT NAME
DESCRIPTION
11
IINP Voltage, DACV 6
0 = Adds 0mV of IINP voltage.
1 = Adds 819.2V of IINP voltage to a maximum of 2.20V.
12
IINP Voltage, DACV 7
0 = Adds 0mV of IINP voltage.
1 = Adds 1.6384V of IINP voltage to a maximum of 2.20V.
13
—
Not used. Normally a 8192mV weight.
14
—
Not used. Normally a 16384mV weight.
15
—
Not used. Normally a 32768mV weight.
DC-DC Converter
The MAX17035/MAX17435/MAX17535 employ a synchronous
step-down DC-DC converter with an n-channel, high-side
MOSFET switch and an n-channel low-side synchronous
rectifier. The MAX17035/MAX17435/MAX17535 feature a
pseudo-fixed-frequency, current-mode control scheme
with cycle-by-cycle current limit. The controller’s constant
off-time (tOFF) is calculated based on VDCIN, VCSIN,
and a time constant with a minimum value of 300ns. The
MAX17035/MAX17435/MAX17535 can also operate in
discontinuous conduction mode for improved light-load
efficiency. The operation of the DC-to-DC controller is
determined by the following five comparators as shown in
the functional diagram in Figure 2:
U The IMIN comparator sets the peak inductor current
in discontinuous mode. IMIN compares the control
signal (LVC) against 100mV (typ). When LVC voltage
is less than 100mV, DHI and DLO are both low.
U The CCMP comparator is used for current-mode
regulation in continuous conduction mode. CCMP
compares LVC against the charging current feedback
signal (CSI). The comparator output is high and the
high-side MOSFET on-time is terminated when the
CSI voltage is higher than LVC.
U The IMAX comparator provides a cycle-by-cycle
current limit. IMAX compares CSI to 2V (corresponding
to 10A when RS2 = 10mI). The comparator output is
high and the high-side MOSFET on-time is terminated
when the current-sense signal exceeds 10A. A new
cycle cannot start until the IMAX comparator output
goes low.
U The ZCMP comparator provides zero-crossing
detection during discontinuous conduction. ZCMP
compares the current-sense feedback signal to
500mA (RS2 = 10mI). When the inductor current
is lower than the 500mA threshold, the comparator
output is high and DLO is turned off.
U The OVP comparator. The MAX17035/MAX17435/
MAX17535 incorporate a comparator to check for the
battery voltage 400mV above the set point and, if that
condition is detected, it disables charging.
CCV, CCI, CCS, and LVC Control Blocks
The MAX17035/MAX17435/MAX17535 control input current
(CCS control loop), charge current (CCI control loop), or
charge voltage (CCV control loop), depending on the
operating condition. The three control loops, CCV, CCI,
and CCS are brought together internally at the lowest
voltage clamp (LVC) amplifier. The output of the LVC
amplifier is the feedback control signal for the DC-DC
controller. The minimum voltage at the CCV, CCI, or CCS
appears at the output of the LVC amplifier and clamps
the other control loops to within 0.3V above the control
point. Clamping the other two control loops close to the
lowest control loop ensures fast transition with minimal
overshoot when switching between different control
loops (see the Compensation section).
Continuous Conduction Mode
With sufficient charge current, the MAX17035/MAX17435/
MAX17535s’ inductor current never crosses zero, which
is defined as continuous conduction mode. The regulator
switches at 1.2MHz (nominal) if it is not in dropout (VCSIN
< 0.88 O VDCIN). The controller starts a new cycle by
turning on the high-side MOSFET and turning off the
low-side MOSFET. When the charge current feedback
signal (CSI) is greater than the control point (LVC), the
CCMP comparator output goes high and the controller
initiates the off-time by turning off the high-side MOSFET
and turning on the low-side MOSFET. The operating
frequency is governed by the off-time and is dependent
upon VCSIN and VDCIN.
At the end of the fixed off-time, the controller initiates
a new cycle if the control point (LVC) is greater than
150mV, and the peak charge current is less than the
cycle-by-cycle current limit. Restated another way, IMIN
______________________________________________________________________________________ 23
MAX17035/MAX17435/MAX17535
Table 8. IINPVoltage() (0x3E) (continued)
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
must be high, MAX must be low, and OVP must be low for
the controller to initiate a new cycle. If the peak inductor
current exceeds IMAX comparator threshold or the output
voltage exceeds the OVP threshold, then the on-time is
terminated. The cycle-by-cycle current limit effectively
protects against overcurrent and short-circuit faults.
If during the off-time the inductor current goes to zero,
the ZCMP comparator output pulls high, turning off the
low-side MOSFET. Both the high- and low-side MOSFETs
are turned off until another cycle is ready to begin.
The MAX17035/MAX17435/MAX17535 enter into the
discontinuous conduction mode (see the Discontinuous
Conduction section).
The on-time is calculated according to the following
equation:
t ON =
Compensation
The CCI loop is internally compensated. The CCV and
the CCS share the external compensation capacitor.
The control loop, which is dominant, uses the external
compensation cap and the one that is not used uses an
internal compensation capacitor.
CCV Loop Compensation
The simplified schematic in Figure 6 is sufficient to
describe the operation of the MAX17035/MAX17435/
MAX17535 when the voltage loop (CCV) is in control.
The required compensation network is a pole-zero pair
formed with CCV and RCV, which is an internal 1.7kI. The
pole is necessary to roll off the voltage loop’s response
at low frequency; CCV = 330pF is sufficient for most
applications.
L × IRIPPLE
VCSSN - VBATT
where:
V
×t
IRIPPLE = BATT OFF
L
There is a 0.3Fs minimum off-time when the (VDCIN VBATT) differential becomes too small. If VBATT R 0.88
x VDCIN, then the threshold for minimum off-time is
reached and the off-time is fixed at 0.27Fs. The switching
frequency in this mode varies according to the equation:
1
f=
L × IRIPPLE
+ t OFF
VCSSN - VBATT
Discontinuous Conduction
The MAX17035/MAX17435/MAX17535 can also operate
in discontinuous conduction mode to ensure that the
inductor current is always positive. The MAX17035/
MAX17435/MAX17535 enter discontinuous conduction
mode when the output of the LVC control point falls below
150mV. For RS2 = 10mI, this corresponds to 375mA:
150mV
IDIS = 1 ×
= 375mA
2 20 × RS2
where charge current for RS2 = 10mI.
In discontinuous mode, a new cycle is not started until
the LVC voltage rises above 150mV. Discontinuous
mode operation can occur during conditioning charge of
overdischarged battery packs, when the charge current
has been reduced sufficiently by the CCS control loop,
or when the charger is in constant-voltage mode with a
nearly full battery pack.
BATT
GMOUT
RESR
RL
COUT
CCV
GMV
RCV
ROGMV
CCV
REF
Figure 6. CCV Loop Diagram
MOSFET Drivers
The DHI and DLO outputs are optimized for driving
moderate-sized power MOSFETs. The MOSFET drive
capability is the same for both the low-side and highsides switches. This is consistent with the variable duty
factor that occurs in the notebook computer environment
where the battery voltage changes over a wide range.
There must be a low-resistance, low-inductance path
from the DLO driver to the MOSFET gate to prevent shootthrough. Otherwise, the sense circuitry in the MAX17035/
MAX17435/MAX17535 interprets the MOSFET gate as
off while there is still charge left on the gate. Use very
short, wide traces measuring 10 squares to 20 squares
or less (1.25mm to 2.5mm wide if the MOSFET is 25mm
from the device). Unlike the DLO output, the DHI output
uses a 50ns (typ) delay time to prevent the low-side
MOSFET from turning on until DHI is fully off. The same
considerations should be used for routing the DHI signal
to the high-side MOSFET.
24 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
Design Procedure
MOSFET Selection
Choose the n-channel MOSFETs according to the maximum required charge current. Low-current applications
usually require less attention. The high-side MOSFET
(N1) must be able to dissipate the resistive losses plus
the switching losses at both VDCI;MIN) and VDCIN(MAX).
Calculate both these sums.
Ideally, the losses at VDCIN(MIN) should be roughly equal
to losses at VDCIN(MAX) with lower losses in between. If
the losses at VDCIN(MIN) are significantly higher than the
losses at VDCIN(MAX), consider increasing the size of M1.
Conversely, if the losses at VDCIN(MAX) are significantly
higher than the losses at VIN(MIN), consider reducing the
size of M1. If DCIN does not vary over a wide range, the
minimum power dissipation occurs where the resistive
losses equal the switching losses. Choose a low-side
MOSFET that has the lowest possible on-resistance
(RDS(ON)), comes in a moderate-sized package (i.e., one
or two 8-pin SO, DPAK, or D2 PAK), and is reasonably
priced. Make sure that the DLO gate driver can supply
sufficient current to support the gate charge and the
current injected into the parasitic gate-to-drain capacitor
caused by the high-side MOSFET turning on; otherwise,
cross-conduction problems can occur. Select devices
that have short turn-off times, and make sure that:
N2(tDOFF(MAX)) - N1(tDON(MIN)) < 40ns, and
N1(tDOFF(MAX)) - N2(tDON(MIN)) < 40ns
Failure to do so could result in efficiency-reducing shootthrough currents.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (PD) due to resistance occurs at the
minimum supply voltage:
2
V
 I

PD(High - Side) =  BATT  LOAD  × R DS(ON)
 VDCIN  2 
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages. However,
the RDS(ON) required to stay within package powerdissipation limits often limits how small the MOSFET can
be. The optimum occurs when the switching (AC) losses
equal the conduction (RDS(ON)) losses. Switching losses
in the high-side MOSFET can become an insidious
heat problem when maximum AC adapter voltages are
applied, due to the squared term in the CV2 f switchingloss equation. If the high-side MOSFET that was chosen
for adequate RDS(ON) at low supply voltages becomes
extraordinarily hot when subjected to VIN(MAX), then
choose a MOSFET with lower losses. Calculating the
power dissipation in M1 due to switching losses is
difficult since it must allow for difficult quantifying factors
that influence the turn-on and turn-off times. These
factors include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute
for breadboard evaluation, preferably including a
verification using a thermocouple mounted on N1:
PD(HS_Switching) =
VDCIN(MAX) 2 × C RSS × fSW × ILOAD
2 × IGATE
where CRSS is the reverse transfer capacitance of N1
and IGATE is the peak gate-drive source/sink current
(3.3A sourcing and 5A sinking).
For the low-side MOSFET (N2), the worst-case power
dissipation always occurs at maximum input voltage:
2
 V
 I

PD(Low - Side) = 1-  BATT  LOAD  × R DS(ON)
  VDCIN  2 
Inductor Selection
The charge current, ripple, and operating frequency
(off-time) determine the inductor characteristics. For
optimum efficiency, choose the inductance according to
the following equation:
L = VBATT O tOFF/(0.3 x ICHG)
This sets the ripple current to 1/3 the charge current and
results in a good balance between inductor size and
efficiency. Higher inductor values decrease the ripple
current. Smaller inductor values require high saturation
current capabilities and degrade efficiency.
Inductor L1 must have a saturation current rating of at
least the maximum charge current plus 1/2 the ripple
current (DIL):
ISAT = ICHG + (1/2) DIL
______________________________________________________________________________________ 25
MAX17035/MAX17435/MAX17535
The high-side driver (DHI) swings from LX to 5V above LX
(BST) and has a typical impedance of 1.5I sourcing and
0.8I sinking. The low-side driver (DLO) swings from DLOV
to ground and has a typical impedance of 3I sinking and
3I sourcing. This helps prevent DLO from being pulled
up when the high-side switch turns on due to capacitive
coupling from the drain to the gate of the low-side MOSFET.
This places some restrictions on the MOSFETs that can be
used. Using a low-side MOSFET with smaller gate-to-drain
capacitance can prevent these problems.
MAX17035/MAX17435/MAX17535
High-Frequency,
Low-Cost SMBus Chargers
The ripple current is determined by:
DIL = VBATT O tOFF/L
where:
tOFF = 2.5Fs (VDCIN - VBATT)/
VDCIN for VBATT < 0.88 VDCIN
or:
tOFF = 0.3Fs for VBATT > 0.88 VDCIN
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resilience to power-up
surge currents:
 V

BATT (VDCIN - VBATT ) 
IRMS = I CHG 


VDCIN


The input capacitors should be sized so that the
temperature rise due to ripple current in continuous
conduction does not exceed approximately 10NC. The
maximum ripple current occurs at 50% duty factor or
VDCIN = 2 x VBATT, which equates to 0.5 x ICHG. If the
application of interest does not achieve the maximum
value, size the input capacitors according to the worstcase conditions.
Output Capacitor Selection
The output capacitor absorbs the inductor ripple current
and must tolerate the surge current delivered from the
battery when it is initially plugged into the charger.
As such, both capacitance and ESR are important
parameters in specifying the output capacitor as a filter
and to the ensure stability of the DC-to-DC converter.
See the Compensation section. Beyond the stability
requirements, it is often sufficient to make sure that the
output capacitor’s ESR is much lower than the battery’s
ESR. Either tantalum or ceramic capacitors can be used
on the output. Ceramic devices are preferable because
of their good voltage ratings and resilience to surge
currents. For most applications the output cap can be
as low as 4.7FF. If the output voltage is low and the input
voltage is high, the output capacitance may need to be
increased.
Applications Information
Layout and Bypassing
Bypass DCIN with a 0.1FF ceramic to ground (Figure
1). N3 and Q1A protect the MAX17035/MAX17435/
MAX17535 when the DC power source input is reversed.
A signal diode for D2 is adequate because DCIN only
powers the LDO and the internal reference. Bypass VCC,
DCIN, LDO, DHI, and VAA, as shown in Figure 1.
Good PCB layout is required to achieve specified noise
immunity, efficiency, and stable performance. The
PCB layout artist must be given explicit instructions—
preferably, a sketch showing the placement of the power
switching components and high current routing. Refer to
the PCB layout in the MAX17035/MAX17435/MAX17535
evaluation kit for examples. A ground plane is essential
for optimum performance. In most applications, the circuit
is located on a multilayer board, and full use of the four or
more copper layers is recommended. Use the top layer
for high current connections, the bottom layer for quiet
connections, and the inner layers for an uninterrupted
ground plane.
Use the following step-by-step guide:
1) Place the high-power connections first, with their
grounds adjacent:
U Minimize the current-sense resistor trace lengths,
and ensure accurate current sensing with Kelvin
connections.
U Minimize ground trace lengths in the high-current
paths.
U Minimize other trace lengths in the high-current
paths.
U Use > 5mm wide traces in the high-current paths.
U Connect C1 and C2 to high-side MOSFET (10mm
max length).
U Minimize the LX node (MOSFETs, rectifier cathode,
inductor (15mm max length)). Keep LX on one
side of the PCB to reduce EMI radiation.
26 �������������������������������������������������������������������������������������
High-Frequency,
Low-Cost SMBus Chargers
ground island need not be very large. When placed on
an inner layer, a sizable ground island can help simplify
the layout because the low current connections can be
made through vias. The ground pad on the backside
of the package should also be connected to this quiet
ground island.
Keep the gate drive traces (DHI and DLO) as short as
possible (L < 20mm), and route them away from the
current-sense lines and REF. These traces should also
be relatively wide (W > 1.25mm).
Place ceramic bypass capacitors close to the IC. The
bulk capacitors can be placed further away. Place the
current-sense input filter capacitors under the part,
connected directly to the GND pin.
Use a single-point star ground placed directly below the
part at the PGND pin. Connect the power ground (ground
plane) and the quiet ground island at this location.
Refer to the MAX17035 EV kit layout for a layout example.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
24 TQFN
T2444-4
21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009
Maxim Integrated Products 27
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX17035/MAX17435/MAX17535
Ideally, surface-mount power components are flush
against one another with their ground terminals almost
touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer
copper, so they do not go through vias. The resulting
top-layer subground plane is connected to the normal
inner-layer ground plane at the paddle. Other highcurrent paths should also be minimized, but focusing
primarily on short ground and current-sense connections
eliminates about 90% of all PCB layout problems.
Place the IC and signal components. Keep the main
switching node (LX node) away from sensitive analog
components (current-sense traces and REF capacitor).
Important: The IC must be no further than 10mm from
the current-sense resistors. Quiet connections to REF,
CCV, CCI, ACIN, and DCIN should be returned to a
separate ground (GND) island. The appropriate traces
are marked on the schematic with the () ground symbol.
There is very little current flowing in these traces, so the