ETC CYT9174

CYT9174
Features
Description
The CYT9174 regulator is designed to convert ¾
Support Both DDR 1 (1.25VTT) and DDR 2
(0.9VTT) Requirements
voltage supplies ranging from 1.6V to 6V into a
desired output voltage, which is adjusted by two
¾
SOP-8 Packages
external voltage divider resistors. The regulator is
¾
Capable of Sourcing and Sinking Current 2.0A
capable of sourcing or sinking up to 2.0A of current
¾
Current-limiting Protection
while regulating an output voltage to within 2%
¾
Thermal Protection
(DDR 1 or DDR 2) or less.
¾
Current-shoot-through protection
The CYT9174, used in conjunction with series ¾
Integrated Power MOSFETs
termination resistors, provides an excellent voltage
¾
Generates Termination Voltages for SSTL-2
source for active termination schemes of high
¾
High Accuracy Output Voltage at Full-Load
speed transmission lines as those seen in high
¾
Adjustable Vout by External Resistors
speed memory buses and distributed back-plane
¾
Minimum External Components
designs. The voltage output of the regulator can be
¾
Shutdown for Standby or Suspend Mode
Operation with High-impedance Output
used as a termination voltage for DDR SDRAM.
Current limits in both sourcing and sinking
mode, plus on-chip thermal shutdown make the
circuit tolerant of the output fault conditions.
Pin Configuration
Application
¾
DDR Memory Termination
¾
Active Termination Buses
¾
Supply Splitter
Pin Description
Pin Name
U
Pin function
VIN
Power Input
GND
Ground
VCNTL
Gate Drive Voltage
REFEN
Reference Voltage input and
Chip Enable
VOUT
Output Voltage
Block Diagram
VCNTL
Current
Limiting Sensor
REFEN
Thermal
CNTL
VIN
VOUT
GND
All contents are subject to change without prior notice
1
CYT9174
Absolute Maximum Rating (1)
Parameter
Symbol
Value
Unit
Input Voltage
VIN
6
V
Power Dissipation
PD
Internally Limited
--
ESD Rating
--
3
KV
TS
-65 to 150
°C
TLEAD
260
°C
ΘJC
15.7
ºC/W
Storage Temperature
Range
Lead Temperature
(Soldering, 5 sec.)
Package Thermal
Resistance
Electrical Characteristics
VIN=2.5V, VCNTL=3.3V, VREFEN=1.25V, COUT=10µF (Ceramic)), TA=25ºC, unless otherwise specified
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Output Offset Voltage (2)
VOS
IOUT = 0A
-20
-5
20
mV
IL : 0A→2.0A
--
0.5
2
IL : 0A→-2.0A
--
0.5
2
Keep VCNTL≥VIN on
1.6
2.5/1.8
--
--
3.3
6
--
1
90
µA
--
2.5
--
A
--
1.4
3
mA
--
100
--
Load Regulation
(DDR 1/2)
Input Voltage Range
(DDR 1/2)
Current In Shutdown
Mode
|∆VLOAD|
VIN
VCNTL
ISHDN
operation power on and
power off sequences
VREFEN <0.2V, RL = 180Ω
%
V
Short Circuit Protection
Current limit
ILIMIT
Quiescent Current
IQ
IL=2.0A
Over Temperature Protection
Thermal Shutdown
Temperature
Thermal Shutdown
Hysterresis
TCASE
3.3V ≤ VCNTL ≤5 V
ºC
Guaranteed by design
--
30
--
Shutdown Function
Shutdown Threshold
Output=High
0.8
--
--
Trigger
Output=Low
--
--
0.2
Note 1: Exceeding the absolute maximum rating may damage the device.
Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN
All contents are subject to change without prior notice
2
V
CYT9174
Application Information
Layout Consideration
The
Internal parasitic diode
CYT9174
regulator
is
packaged
in
Avoid forward-bias internal parasitic diode,
thermally enhanced plastic SOP-8 package. This
VOUT to VCNTL, and VOUT to VIN, the VOUT should not
small footprint package is unable to convectively
be forced same voltage respect to ground on this
dissipate the heat generated when the regulator is
pin while the VCNTL or VIN is disappeared.
operating at high current levels. In order to control
Consideration while designs the resistance of
die operating temperatures, the PC board layout
voltage divider
should allow for maximum possible copper area at
Make sure the sinking current capability of
pull-down NMOS if the lower resistance was chosen
the VCNTL pins of the CYT9174.
The multiple VCNTL pins on the SOP-8 package
so that the voltage on VREFEN is below 0.2V.
are internally connected, but lowest thermal
In addition to item1, the capacitor and voltage
resistance will result if these pins are tightly
divider form the low-pass filter. There are two
connected on the PC board. This will also aid heat
reasons doing this design; one is for output voltage
dissipation at high power levels.
soft-start while another is for noise immunity.
If
the
large
copper around
the IC
is
unavailable, a buried layer may be used as a heat
Thermal Consideration
CYT9174 regulators have internal thermal
limiting circuitry designed to protect the device
during overload conditions. For continuous normal
load conditions however, the maximum junction
spreader, Use via to conduct the heat into the
buried or backside of PCB layer. The via should be
small enough to retain solder when the board is
wave-soldered.
temperature rating of 150°C must not be exceeded.
Terminator Resis
Higher continuous currents or ambient temperature
R0
require additional heatsinking. Heat sinking to the
CYT9174
IC package must consider the worst case power
dissipation which may occur.
VOUT
R2
R3
R4
REFEN
It should also be noted that with the VCNTL
equal to 5V, the point of thermal shutdown will be
degraded by approx. 20°C compared to the VCNTL
R1
R5
CYT9174
VOUT
equipped with 3.3V. It is highly recommended that
R6
R7
R8
R9
to use the 3.3V rail acting as the VCNTL so as to
minimize the thermal concern of the CYT9174 in the
SOP-8 package.
All contents are subject to change without prior notice
3
RN
RN1
BUS(0)
BUS(1)
BUS(2)
BUS(3)
BUS(4)
BUS(5)
BUS(6)
BUS(7)
BUS(8)
BUS(9)
BUS(N+1)
BUS(N)
CYT9174
Application Diagram
R1 = R2 = 100KΩ, RTT = 50Ω/33Ω/25Ω
COUT, min = 10µF(Ceramic) + 1000µF under the worst case testing condition
RDUMMY = 1KΩ as for VOUT discharge when VIN is not present but VCNTL is present
CSS = 1µF, CIN = 470µF(Low ESR), CCNTL = 47µF
All contents are subject to change without prior notice
4
CYT9174
Outline Drawing SOP-8
1
8
2
7
3
6
D
B
B1
5
4
A1
E
H
C
A
DIMN
A
A1
B
B1
C
D
H
E
DIMENSIONS
INCHES
MM
MIN MAX MIN MAX
0.0532 0.0688
0.0040 0.0098
0.0130 0.0200
0.050 BSC
0.0075 0.0098
0.1890 0.1968
0.2284 0.2440
0.1497 0.1574
All contents are subject to change without prior notice
5
1.35
1.75
0.10
0.25
0.33
0.51
1.27 BSC
0.19
0.25
4.80
5.00
5.80
6.20
3.80
4.00