RT9199 Cost-Effective, 2A Peak Sink/Source Bus Termination Regulator General Description Features The RT9199 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the devices requirements. The regulator is capable of actively sinking or sourcing up to 2A peak while regulating an output voltage to within 20mV. The output termination voltage can be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. z The RT9199 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. z The RT9199 are available in both SOP-8 and SOP-8 (Exposed Pad) surface mount packages. z z z z z z z z z z RT9199 Package Type S : SOP-8 SP : SOP-8 (Exposed Pad-Option 2) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Note : Richtek Pb-free and Green products are : `RoHS compliant and compatible with the current require- Current Limiting Protection On-Chip Thermal Protection RoHS Compliant and 100% Lead (Pb)-Free Applications z z Ordering Information Ideal for DDR-II VTT Applications Sink and Source 2A Peak Current Integrated Power MOSFETs Generate Termination Voltage for DDR Memory Interfaces High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output z z z Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR/II Memory Systems Pin Configurations (TOP VIEW) 8 VIN VCNTL GND 2 7 VCNTL REFEN 3 6 VOUT 4 5 VCNTL VCNTL ments of IPC/JEDEC J-STD-020. SOP-8 `Suitable for use in SnPb or Pb-free soldering processes. `100%matte tin (Sn) plating. 8 VIN GND 2 REFEN 3 VOUT 7 GND 6 9 4 5 NC NC VCNTL NC SOP-8 (Exposed Pad) DS9199-07 September 2007 www.richtek.com 1 RT9199 Typical Application Circuit VCNTL = 5V VIN = 1.8V RTT R1 VIN 2N7002 EN VCNTL CCNTL CIN RT9199 REFEN VOUT CSS R2 GND COUT RDUMMY R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition RDUMMY = 1kΩ as for VOUT discharge when VIN is not presented but VCNTL is presented CSS = 1μF, CIN = 470μF (Low ESR), CCNTL = 47μF Test Circuit VIN = 1.8V VIN 1.25V VCNTL = 5V VCNTL RT9199 REFEN VOUT VOUT GND COUT V IL Figure 1. Output Voltage Tolerance, ΔVLOAD VCNTL = 5V VIN = 1.8V A VIN 0.9V VCNTL RT9199 VOUT REFEN VOUT 0.9V 0V 0.15V GND RL COUT V RL and COUT Time deleay Figure 2. Current in Shutdown Mode, ISTBY www.richtek.com 2 DS9199-07 September 2007 RT9199 VCNTL = 5V VIN = 1.8V VIN VCNTL RT9199 REFEN VOUT 0.9V VOUT A GND COUT V IL Figure 3. Current Limit for High Side, ILIM Power Supply with Current Limit VCNTL = 5V VIN = 1.8V VIN A VCNTL IL RT9199 VOUT REFEN 0.9V GND VOUT COUT V Figure 4. Current Limit for Low Side, ILIM VCNTL = 5V VIN = 1.8V VIN 0.9V VREFEN VCNTL RT9199 VOUT REFEN GND 0.15V VOUT RL COUT V 0.9V VOUT 0V VOUT would be low if VREFEN < 0.15V VOUT would be high if VREFEN > 0.6V RL and COUT Time deleay Figure 5. REFEN Pin Shutdown Threshold, VIH & VIL DS9199-07 September 2007 www.richtek.com 3 RT9199 Functional Pin Description VIN Input voltage which supplies current to the output pin. Connect this pin to a well-decoupled supply voltage. To prevent the input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor should be placed as close as possible to the VIN pin. GND (Exposed Pad) Common Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. VCNTL VCNTL supplies the internal control circuitry and provides the drive voltage. The driving capability of output current is proportioned to the VCNTL. Connect this pin to 5V bias supply to handle large output current with at least 1μF capacitor from this pin to GND. An important note is that VIN should be kept lower or equal to VCNTL. REFEN Reference voltage input and active low shutdown control pin. Two resistors dividing down the VIN voltage on the pin to create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as 2N7002, signal N-MOSFET. VOUT Regulator output. VOUT is regulated to REFEN voltage that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output rail. To maintain adequate large signal transient response, typical value of 1000μF Al electrolytic capacitor with 10μF ceramic capacitors are recommended to reduce the effects of current transients on VOUT. Function Block Diagram VCNTL VIN Current Limit Thermal Protection + REFEN VOUT EA GND www.richtek.com 4 DS9199-07 September 2007 RT9199 Absolute Maximum Ratings z z z z z z z z (Note 1) Input Voltage, VIN ------------------------------------------------------------------------------------------------------ 6V Control Voltage, VCNTL ----------------------------------------------------------------------------------------------- 6V Power Dissipation, PD @ TA = 25°C SOP-8 ------------------------------------------------------------------------------------------------------------------- 0.909W SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------- 1.176W Package Thermal Resistance (Note 4) SOP-8, θJA -------------------------------------------------------------------------------------------------------------- 110° C/W SOP-8, θJC -------------------------------------------------------------------------------------------------------------- 60° C/W SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------------------------ 86° C/W SOP-8 (Exposed Pad), θJC ----------------------------------------------------------------------------------------- 15° C/W Junction Temperature ------------------------------------------------------------------------------------------------- 125°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------------------- –65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z (Note 3) Input Voltage, VIN ------------------------------------------------------------------------------------------------------ 1.6V to 5.5V Control Voltage, VCNTL ----------------------------------------------------------------------------------------------- 5V ± 5% Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C Electrical Characteristics (VIN = 1.8V, VCNTL = 5V, VREFEN = 0.9V, COUT = 10μF (Ceramic), TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units -- 1 2.5 mA -- 2 90 μA −20 -- +20 mV −20 -- +20 mV 2.0 -- 3.5 A VCNTL = 5V 125 170 -- °C ΔTSD VCNTL = 5V -- 35 -- °C VIH Enable 0.6 -- -- VIL Shutdown -- -- 0.15 Input VCNTL Operation Current ICNTL Standby Current (Note 7) ISTBY IOUT = 0A VREFEN < 0.2V (Shutdown), RLOAD = 180Ω Output (DDR II) Output Offset Voltage (Note 5) VOS Load Regulation (Note 6) ΔVLOAD IOUT = 0A IOUT = +1.8A IOUT = −1.8A Protection Current limit ILIMIT Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis REFEN Shutdown Shutdown Threshold DS9199-07 September 2007 V www.richtek.com 5 RT9199 Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers, 2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad for SOP-8 (Exposed Pad) package. Note 5. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 6. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A peak. Note 7. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on REFEN pin (VIL < 0.15V). It is measured with VIN = VCNTL = 5V. www.richtek.com 6 DS9199-07 September 2007 RT9199 Typical Operating Characteristics VCNTL Pin Current vs. Temperature Output Voltage vs. Temperature 0.92 0.6 VIN = 1.8V, VCNTL = 5V VIN = 1.8V, VCNTL = 5V 0.5 Vcntl Pin Current (mA) Output Voltage (V) 0.915 0.91 0.905 0.9 0.895 0.89 0.4 0.3 0.2 0.885 0.1 0.88 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (°C) 3.5 VIN = 1.8V, VCNTL = 5V Source Current Limit (A) Source Current Limit (A) 2.5 2 1.5 1 0.5 0 100 125 VIN = 1.8V, VCNTL = 5V 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 -50 -25 0 VIN Current vs. Temperature 3 25 50 75 100 125 Temperature (°C) Temperature (°C) Shutdown Threshold vs. Temperature 0.6 VIN = 1.8V, VCNTL = 5V RT9199SP, VCNTL = 5V 0.55 Shutdown Threshold (V) 2.5 VIN Current (mA) 75 3 3 2 1.5 1 0.5 0.5 Turn On 0.45 0.4 0.35 Turn Off 0.3 0.25 0.2 0 -50 -25 0 25 50 Temperature (°C) DS9199-07 50 Sink Current Limit vs. Temperature Source Current Limit vs. Temperature 3.5 25 Temperature (°C) September 2007 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 7 RT9199 Output Short-Circuit Protection Sink Output Short-Circuit Protection VIN = 1.8V, VCNTL = 5V Sink 10 8 6 4 2 0 6 4 2 Time (1ms/Div) Output Short-Circuit Protection Output Short-Circuit Protection Source VIN = 1.8V, VCNTL = 5V VIN = 2.5V, VCNTL = 5V 12 Output Short Circuit (A) Output Short Circuit (A) 8 Time (1ms/Div) Source 10 8 6 4 2 10 8 6 4 2 0 0 Time (1ms/Div) Time (1ms/Div) 0.9VTT @ 1.8A Transient Response 1.25VTT @ 1.8A Transient Response VIN = 1.8V, VCNTL = 5V, VOUT = 0.9V 50 Swing Frequency : 10kHz 0 -50 Output Voltage Transient (mV) Output Voltage Transient (mV) 10 0 12 2 1 0 -1 -2 0 -50 1 0 -1 -2 Time (25μs/Div) www.richtek.com 8 VIN = 2.5V, VCNTL = 5V, VOUT = 1.25V 50 Swing Frequency : 10kHz 2 Output Current (A) Output Current (A) VIN = 2.5V, VCNTL = 5V 12 Output Short Circuit (A) Output Short Circuit (A) 12 Time (25μs/Div) DS9199-07 September 2007 RT9199 Application Information Consideration while designing the resistance of voltage divider Refer to the “Typical Application Circuit”.Make sure the current sinking capability of pull-down NMOS is enough for the chosen voltage divider to pull-down the voltage at REFEN pin below 0.15V to shutdown the device. could be obtained by the product of RDS(ON) and output current. For thermal consideration, please refer to the relative sections. VREFEN VCNTL R1 In addition, the capacitor CSS and voltage divider form the low-pass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. R2 GND Figure 6 How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? RDS(ON) vs. Temperature In notebook application, using RichTek's Patent 0.48 “ Distributed 0.46 Bus Terminator Topology” with choosing RichTek's product is encouraged. 0.42 BUS(0) R1 BUS(1) RT9199 VOUT R2 R3 R4 REFEN R5 BUS(2) R7 R8 R9 R(2N) R(2N+1) 0.34 0.3 BUS(5) 0.28 -50 BUS(7) -25 0 25 50 75 100 125 Temperature (°C) Figure 7 BUS(8) BUS(9) BUS(2N) BUS(2N+1) The RT9199 could also serves as a general linear regulator. The RT9199 accepts an external reference voltage at REFEN pin and provides output voltage regulated to this reference voltage as shown in Figure 6, where VOUT = VREFEN x R2/(R1+R2) As other linear regulator, dropout voltage and thermal issue should be specially considered. Figure 7 shows the RDS(ON) over temperature of RT9199. The minimum dropout voltage September 2007 0.36 BUS(4) General Regulator DS9199-07 0.38 0.32 BUS(6) VOUT 0.4 BUS(3) R6 RT9199 R DS(ON) (Ω) R0 VCNTL = 5V, VREFEN = 1V 0.44 Distributed Bus Terminating Topology Terminator Resistor VIN RT9199 REFEN VOUT Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the RT9199. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between RT9199 and the preceding power converter. Thermal Consideration RT9199 regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ www.richtek.com 9 RT9199 PD(MAX) = ( TJ(MAX) − TA ) / θJA Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. The junction to ambient thermal resistance for SOP-8 package (Exposed Pad) is 86°C/W, on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula: PD(MAX) = (125°C − 25°C) / 86°C/W = 1.163W Figure 8 shows the package sectional drawing of SOP-8 (Exposed Pad). Every package has several thermal dissipation paths. As show in Figure 9, the thermal resistance equivalent circuit of SOP-8 (Exposed Pad). The path 2 is the main path due to these materials thermal conductivity. We define the exposed pad is the case point of the path 2. The thermal resistance θJA of SOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it’ s useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of SOP-8 package. Figure 10 show the relation between thermal resistance θJA and copper area on a standard JEDEC 51-7 (4 layers, 2S2P) thermal test board at TA = 25°C. We have to consider the copper couldn’ t stretch infinitely and avoid the tin overflow. We use the “Dog-Bone” copper patterns on the top layer as Figure 11. 100 Thermal Resistance θJA (°C/W) The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: 90 80 70 60 50 40 30 20 10 0 Ambient Molding Compound Gold Line 0 10 20 30 40 50 60 70 80 2 Copper Area (mm ) Lead Frame Figure 10. Relation Between Thermal Resistance θJA and Copper Area Die Pad PCB Case (Exposed Pad) Figure 8. SOP-8 (Exposed Pad) Package Sectional Drawing RGOLD-LINE RLEAD FRAME RPCB W≦2.28mm path 1 Junction RDIE RDIE-ATTACH RDIE-PAD path 2 Exposed Pad RPCB Case (Exposed Pad) Ambient RMOLDING-COMPOUND Figure 11. Dog-Bone Layout path 3 Figure 9. Thermal Resistance Equivalent Circuit www.richtek.com 10 DS9199-07 September 2007 RT9199 As shown in Figure 12, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad of 2 oz. copper (Figure 12.a), θJA is 86°C/W. Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 12.b) reduces the θJA to 73°C/W. Even further, increasing the copper area of pad to 70mm2 (Figure 12.d) reduces the θJA to 65°C/W. (a) Copper Area = 10mm2, θJA = 86°C/W (b) Copper Area = 30mm2, θJA = 73°C/W (c) Copper Area = 50mm2, θJA = 68°C/W (d) Copper Area = 70mm2, θJA = 65°C/W Figure 12. Thermal Resistance vs. Copper Area Layout Thermal Design DS9199-07 September 2007 www.richtek.com 11 RT9199 Outline Information H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package www.richtek.com 12 DS9199-07 September 2007 RT9199 H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Symbol Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] DS9199-07 September 2007 www.richtek.com 13