Description Features The SE9174C is a simple, cost-effective and ¾ Ideal for DDR-I, DDR-II and DDR-III VTT Applications high-speed linear regulator designed to generate ¾ Sink and Source 2A Continuous Current termination voltage in double data rate (DDR) ¾ Integrated Power MOSFETs memory system to comply with the JEDEC SSTL_2 ¾ Generates Termination Voltage for SSTL_2, SSTL and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 devices ¾ High Accuracy Output Voltage at Full-Load requirements. The regulator is capable of actively ¾ Output Adjustment by Two External Resistors sinking or sourcing up to 2A while regulating an ¾ Low External Component Count output ¾ Shutdown for Suspend to RAM (STR) Functionality voltage and to SCSI-3 within 40mV. etc. _18, HSTL, SCSI-2 and SCSI-3 Interfaces. The output termination voltage cab be tightly regulated to track with High-Impedance Output 1/2VDDQ by two external voltage divider resistors or ¾ Current Limiting Protection the desired output voltage can be pro-grammed by ¾ On-Chip Thermal Protection externally forcing the REFEN pin voltage. ¾ Available in PSOP-8 (Exposed Pad) Packages The SE9174C also incorporates a high-speed ¾ VIN and VCNTL No Power Sequence Issue differential amplifier to provide ultra-fast response in ¾ 100% Lead (Pb)-Free line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The SE9174C are available in the PSOP-8 (Exposed Pad) surface mount packages. Pin Configuration Application ¾ Desktop PCs, Notebooks, and Workstations ¾ Graphics Card Memory Termination ¾ Set Top Boxes, Digital TVs, Printers ¾ Embedded Systems ¾ Active Termination Buses ¾ DDR-I, DDR-II and DDR-III Memory Systems Block Diagram Pin Description Pin Name Pin function VIN Power Input GND Ground VCNTL Gate Drive Voltage REFEN Reference Voltage input and Chip Enable VOUT Output Voltage Revision 12/4/2008 All contents are subject to change without prior notice © Seaward Electronics Inc., 2007. • www.seawardinc.com.cn • Page 1 Absolute Maximum Rating (1) Parameter Symbol Value Unit Input Voltage VIN 6 V Control Voltage VCNTL 6 V Power Dissipation PD Internally Limited -- ESD Rating -- 3 KV Storage Temperature Range TS -65 to 150 °C Lead Temperature (Soldering, 5 sec.) TLEAD 260 °C Package Thermal Resistance ΘJC 28 ºC/W Operating Rating(2) Parameter Symbol Value Units Input Voltage VIN 2.5 to 1.5 ±3% V Control Voltage VCNTL 5.0 or 3.3 ±5% V Ambient Temperature TA -40 to +85 ℃ Junction Temperature TJ -40 to +125 ℃ Electrical Characteristics VIN=2.5V/1.8V/1.5V, VCNTL=3.3V, VREFEN=1.25V/0.9V/0.75V, COUT=10μF (Ceramic)), TA=25ºC, unless otherwise specified Parameter Symbol Test Conditions Min Typ Max Units VCNTL Operation Current ICNTL IOUT=0A -- 1 2.5 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown),RLOAD = 180Ω -- 50 90 μA VOS ΔVLOAD IOUT= 0A -20 -- +20 mV IOUT= +2A -20 -- +20 2.2 -- -- Input Output (DDR / DDR II / DDR III) Output Offset Voltage(3) Load Regulation (4) IOUT= -2A Protection Current limit ILIM Thermal Shutdown Temperature TSD ΔTSD 3.3V ≤ VCNTL ≤ 5V -- 170 -- 3.3V ≤ VCNTL ≤ 5V -- 35 -- VIH Enable 0.6 -- -- VIL Shutdown -- -- 0.2 Thermal Shutdown Hysteresis A ℃ REFEN Shutdown Shutdown Threshold Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN Note 3: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 4: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. Revision 12/4/2008 All contents are subject to change without prior notice © Seaward Electronics Inc., 2007. • www.seawardinc.com.cn • Page 2 V Typical Operating Characteristics Revision 12/4/2008 All contents are subject to change without prior notice © Seaward Electronics Inc., 2007. • www.seawardinc.com.cn • Page 3 Application Information Thermal Consideration Input Capacitor and Layout Consideration SE9174C regulators have internal thermal limiting Place the input bypass capacitor as close as possible to the SE9174C. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. circuitry designed to protect the device during overload conditions.For continued operation, do not exceed maximum operation junction temperature 125℃. The power dissipation definition in device is: PD = (VIN - VOUT) x IOUT + VIN x IQ Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between SE9174C and the preceding power converter. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature Consideration while designs the resistance of difference between junction to ambient. The voltage divider maximum power dissipation can be calculated by Make sure the sinking current capability of following formula: pull-down NMOS if the lower resistance was PD(MAX) = ( TJ(MAX) -TA ) /ΘJA chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form Where TJ(MAX) is the maximum operation junction the lowpass filter. There are two reasons doing this temperature 125℃, TA is the ambient temperature design; one is for output voltage soft-start while and the Θ JA is the junction to ambient thermal another is for noise immunity. resistance. The junction to ambient thermal resistance (ΘJA is layout dependent) for PSOP-8 package (Exposed Pad) is 75℃/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25℃ can be calculated by following formula: PD(MAX) = (125℃ - 25℃) / 75℃/W = 1.33W The thermal resistanceΘ JA of PSOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of PSOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. Revision 12/4/2008 All contents are subject to change without prior notice © Seaward Electronics Inc., 2007. • www.seawardinc.com.cn • Page 4 Application Diagram VCNTL=3.3V VIN=2.5V/1.8V/1.5V P1 R1 2N7002 EN VIN P3 R2 P6 CSS VCNTL REFEN VOUT GND P2 CIN CCNTL P4 COUT RDUMMY R1 = R2 = 100KΩ, RTT = 50Ω/33Ω/25Ω COUT, min = 10μF (Ceramic) + 1000μF under the worst case testing condition RDUMMY = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present CSS = 1μF, CIN = 470μF(Low ESR), CCNTL = 47μF Revision 12/4/2008 All contents are subject to change without prior notice © Seaward Electronics Inc., 2007. • www.seawardinc.com.cn • Page 5 RTT Outline Drawing PSOP-8 Contact Information Seaward Electronics Incorporated – China Room 1605, Building 1, International Pioneering Park, #1 Shangdi Xinxi Rd. Haidian District, Beijing 100085, China Tel: 86-10-8289-5700/01/05 Fax: 86-10-8289-5706 Email: [email protected] Seaward Electronics Corporation – Taiwan 2F, #181, Sec. 3, Min Quan East Rd. Taipei, Taiwan R.O.C Tel: 886-2-2712-0307 Fax: 886-2-2712-0191 Email: [email protected] Seaward Electronics Incorporated – North America 1512 Centre Pointe Dr. Milpitas, CA95035, USA Tel: 1-408-821-6600 Last Updated - 12/4/2008 Revision 12/4/2008 All contents are subject to change without prior notice © Seaward Electronics Inc., 2007. • www.seawardinc.com.cn • Page 6