a RGB to NTSC/PAL Encoders AD720/AD721 FEATURES Composite Video Output Chrominance and Luminance (S-Video) Outputs No External Filters or Delay Lines Required Drives 75 Ω Reverse-Terminated Loads Compact 28-Pin PLCC Logic Selectable NTSC or PAL Encoding Modes Automatically Selects Proper Chrominance Filter Cutoff Frequency for Encoding Standard Logic Selectable Encode or Power-Down Mode (AD720 Only) Logic Selectable Encode or Bypass Mode (AD721 Only) Low Power: 200 mW typical APPLICATIONS RGB to NTSC or PAL Encoding Drive RGB Signals into 75 Ω Load (AD721 Only) PRODUCT DESCRIPTION The AD720 and AD721 RGB to NTSC/PAL Encoders convert red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chrominance (subcarrier amplitude and phase) signals in accordance with either NTSC or PAL standards. These two outputs are also combined to provide a composite video output. All three outputs are available separately at voltages of twice the standard signal levels as required for driving 75 Ω reverse terminated cables. The AD721 also features a bypass mode, in which the RGB inputs may bypass the encoder section of the IC via three gain-of-two amplifiers suitable for driving 75 Ω reverse terminated cables. The AD720 and AD721 provide a complete, fully calibrated function, requiring only termination resistors, bypass capacitors, a clock input at four times the subcarrier frequency, and a composite sync pulse. There are two control inputs: one input selects the TV standard (NTSC/PAL) and the other (ENCD) powers down most sections of the chip when the encoding function is not in use (AD720) or activates the triple bypass buffer to drive the RGB signals when RGB encoding is not required (AD721). All logical inputs are CMOS compatible. The chip operates from ± 5 V supplies. (continued on page 5) FUNCTIONAL BLOCK DIAGRAM NTSC/PAL ASNC C-SYNC ENCD POWER AND GROUNDS NTSC/PAL BURST SC 90 ° 4FSC DELAYED C-SYNC C-SYNC DELAY SYNC DECODER QUADRATURE DECODER ±180° (PAL ONLY) SC 90 °/270 ° NTSC/PAL CLOCK AT 8FSC SC 0 ° +5V LOGIC +5V ANALOG –5V ANALOG ONLY AGND ANALOG DGND LOGIC BURST RED GREEN RGB-TO-YUV ENCODING MATRIX Y 5MHz 4-POLE LP PRE-FILTER U 1.2MHz 4-POLE LPF V BLUE X2 ROUT 1.5Vp-p X2 GOUT 1.2MHz 4-POLE LPF AD721 (ONLY) DC RESTORE AND C-SYNC INSERTION SAMPLEDDATA DELAY LINE 5MHz 2-POLE LP POSTFILTER NTSC/PAL BALANCED MODULATORS ∑ LUMINANCE OUTPUT* X2 ∑ 3.6MHz (NTSC) 4.4MHz (PAL) 3-POLE LPF –0.572V TO 1.43V NTSC –0.6V TO 1.4V PAL COMPOSITE OUTPUT* X2 –0.572V TO 2V NTSC –0.6V TO 2V PAL X2 CHROMINANCE OUTPUT* 572mVp-p NTSC 600mVp-p PAL *NOTE: THE LUMINANCE, COMPOSITE, AND CHROMINANCE OUTPUTS ARE AT TWICE NORMAL LEVELS FOR DRIVING 75Ω REVERSE-TERMINATED LINES. 1.5Vp-p X2 BOUT 1.5Vp-p REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD720/AD721–SPECIFICATIONS Parameter SIGNAL INPUTS (RDIN, GRIN, BLIN) Input Amplitude (TA = +25°C and supplies = ±5 V unless otherwise noted) Conditions Min NTSC PAL Input Resistances1 RDIN with Respect to AGND GRIN with Respect to AGND BLIN with Respect to AGND Input Capacitance LOGIC INPUTS (C-SYNC, 4FSC, ENCD, NTSC) Logic LO Input Voltage Logic HI Input Voltage Logic LO Input Current (DC) Logic HI Input Current (DC) BYPASS AMPLIFIERS (AD721 Only) Gain Error Small Signal –3 dB Bandwidth Output Offset Voltage (Active State) Output Voltage (Inactive State) VIDEO OUTPUTS3 (LUMA, CRMA, CMPS) Luminance (LUMA) Output Bandwidth Gain Error Linearity Sync Level Chrominance (CRMA) Output Bandwidth Color Burst Amplitude Absolute Gain Error Absolute Phase Error Chroma/Luma Time Alignment4 Composite Output Absolute Gain Error Differential Gain Differential Phase Output Offset Voltage Chroma Feedthrough POWER SUPPLIES (APOS, DPOS, VNEG) Recommended Supply Range Full Output Current5 Zero Signal Quiescent Current Bypass Mode Quiescent Current (AD721 Only) Typ Max 714 700 mV mV 2.3 4.2 4.2 5 kΩ kΩ kΩ pF 1 V V µA µA +5 % MHz mV mV 4 <1 <1 Nominal Gain of ×22 –5 100 –50 –50 –5 NTSC PAL 252 NTSC PAL NTSC PAL 257 –15 NTSC –5 With Respect to Chroma Channel With Respect to Chroma Channel Chroma, Luma, or Composite Outputs Monochrome Input Dual Supply –5 V Supply +5 V Supply –5 V Supply +5 V Supply –5 V Supply +5 V Supply +50 +50 5 ±1 ± 0.1 286 300 +5 320 MHz % % mV mV 3.6 4.4 286 315 300 ±5 +15 ±3 –170 MHz MHz mV p-p mV p-p % Degrees ns ±1 0.1 0.1 50 20 % % Degrees mV mV p-p ± 4.75 10 10 Unit +5 100 55 ± 5.25 35 67 20 20 14 14 35 35 20 20 V mA mA mA mA mA mA NOTES 1 Input scaling resistors provide best scaling accuracy when source resistance is 37.5 Ω (75 Ω reverse-terminated input). 2 Required for driving a 75 Ω double reverse terminated load. 3 All outputs are measured at a reverse-terminated load; voltages at IC pins are twice those specified here. 4 This is a predistortion (per FCC specifications) that compensates for the chroma/luma delay in the low-pass filter that separates the luminance and chrominance signals in a television receiver. 5 CRMA, LUMA, and CMPS outputs are all connected to 75 Ω reverse-terminated loads; full-white signal for entire field. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice. –2– REV. 0 AD720/AD721 ABSOLUTE MAXIMUM RATINGS* PIN DESCRIPTIONS Supply Voltage ± VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 6 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . . . . 0°C to +70°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . . +300°C Pin Mnemonic* NOTE *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. Thermal characteristics: 28-pin plastic package: θJA = 100°C. 1 2 3 4 5 (NC) GOUT (NC) APOS (NC) ROUT AGND ENCD 6 RDIN 7 8 AGND GRIN ORDERING GUIDE Model Temperature Range Package Package Option 9 10 AGND BLIN AD720JP AD721JP 0°C to +70°C 0°C to +70°C 28-Pin PLCC 28-Pin PLCC P-28A P-28A 11 STND 12 13 AGND CRMA 14 15 APOS CMPS 16 17 APOS LUMA 18 19 20 VNEG DGND 4FSC 21 22 DPOS ASNC 23 24 DPOS SYNC 25 26 27 28 DGND VNEG (NC) BOUT APOS GOUT (NC) 2 1 VNEG APOS (NC) 3 APOS ROUT (NC) 4 BOUT (NC) AGND PIN CONNECTIONS 28-Lead Plastic Leaded Chip Carrier (PLCC) Package P-28A 28 27 26 ENCD 5 25 DGND RDIN 6 24 SYNC AGND 7 GRIN 8 AGND 23 DPOS AD720/AD721 RGB TO NTSC/PAL ENCODER 22 ASNC 12 13 14 15 16 17 18 CMPS APOS LUMA VNEG 19 DGND APOS STND 11 CRMA 21 DPOS 20 4FSC AGND 9 BLIN 10 NOTE: CONNECTIONS IN ( ) PERTAIN ONLY TO AD720 Description* (No Connection) Green Bypass Buffer (No Connection) Analog Positive Supply; +5 V ± 5% (No Connection) Red Bypass Buffer Analog Ground Connection A Logical High Enables the NTSC/PAL Encode Mode (A Logical Low Powers Down the Chip) A Logical Low Enables the RGB Bypass Mode Red Component Video Input 0 mV to 714 mV for NTSC 0 mV to 700 mV for PAL Analog Ground Connection Green Component Video Input 0 mV to 714 mV for NTSC 0 mV to 700 mV for PAL Analog Ground Connection Blue Component Video Input 0 mV to 714 mV for NTSC 0 mV to 700 mV for PAL A Logical High Input Selects NTSC Encoding A Logical Low Input Selects PAL Encoding CMOS Logic Levels Analog Ground Connection Chrominance Output; Subcarrier Only** 572 mV Peak-to-Peak for NTSC 600 mV Peak-to-Peak for PAL Analog Positive Supply; +5 V ± 5% Composite Video Output** –572 mV to 2 V for NTSC –600 mV to 2 V for PAL Analog Positive Supply; +5 V ± 5% Luminance Plus SYNC Output** –572 mV to 1.43 V for NTSC –600 mV to 1.4 V for PAL System Negative Supply; –5 V ± 5% Digital Ground Connection Clock Input at Four Times the Subcarrier Frequency 14.318 180 MHz for NTSC 17.734 480 MHz for PAL CMOS Logic Levels Digital Positive Supply; +5 V ± 5% A Logical High Input Resets the Subcarrier Phase Every Frame A Logical Low Input Resets the Subcarrier Phase Every Fourth Frame CMOS Logic Levels Digital Positive Supply; +5 V ± 5% Input for Composite Television Synchronization Pulses Negative Sync Pulses CMOS Logic Levels Digital Ground Connections (One of Two) System Negative Supply; –5 V ± 5% (No Connection) Blue Bypass Buffer Analog Positive Supply; +5 V ± 5% *( ) pertain only to AD720. **The luminance, chrominance, and composite outputs are at twice normal levels for driving 75 Ω reverse-terminated lines. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD720/AD721 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD720/AD721–Typical Characteristics COMPOSITE VIDEO COMPOSITE SYNC TEKTRONIX TSG 300 COMPONENT VIDEO WAVEFORM GENERATOR RGB 3 VOLTS IRE:FLT AD720/AD721 RGB TO NTSC/PAL ENCODER SONY MONITOR MODEL 1342 75Ω GENLOCK 100.0 75Ω 0.5 50.0 4FSC TEKTRONIX 1910 COMPOSITE VIDEO WAVEFORM GENERATOR FSC FRAMES SELECTED: 1 2; APL = 45.8% 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63µs PRECISION MODE OFF SYNC = SOURCE TEKTRONIX VM700A WAVEFORM MONITOR PIXEL-CLOCK GENERATOR 0.0 Figure 1. AD720/AD721 Evaluation Setup DG DP(NTSC) (SYNC = EXT) FIELD = 1 LINE = 21 DIFFERENTIAL GAIN (%) MIN = –0.10; MAX = 0.00; p-p/MAX = 0.10 0.00 –0.04 0.00 –0.04 –0.01 0.0 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 70.0 –0.10 0.10 Figure 4. 100% Color Bars, NTSC 0.05 0.00 –0.05 VOLTS IRE:FLT FRAMES SELECTED: 1 2; APL = 11.3% 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63µs PRECISION MODE OFF SYNC = SOURCE –0.10 DIFFERENTIAL PHASE (°) MIN = 0.00; MAX = 0.07; p-p = 0.07 0.07 0.01 0.00 0.05 0.05 0.04 100.0 0.10 0.05 0.5 0.00 50.0 –0.05 –0.10 1ST 2ND 3RD 5TH 4TH 6TH 0.0 Figure 2. Composite Output Differential Phase and Gain, NTSC (Nulled to Chroma Output) VOLTS IRE:FLT 0.0 NOISE REDUCTION: 15.05dB APL = 49.6% 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63µs SYNC = SOURCE FRAMES SELECTED: 1 2 100.0 10.0 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 70.0 Figure 5. Multipulse, NTSC H TIMING MEASUREMENT RS-170A (NTSC) FIELD = 1 LINE = 22 8.0 CYCLES 5.35µs 0.5 50.0 4.82µs 0.0 85ns 39.4 IRE 73ns 0.0 10.0 20.0 30.0 40.0 50.0 60.0 39.2 IRE 70.0 AVERAGE 32 TO 32 MICROSECONDS/PRECISION MODE OFF Figure 3. Modulated Pulse and Bar, NTSC Figure 6. Horizontal Timing, NTSC H TIMING (PAL) LINE = 17 1.98µs 5.52µs 4.82µs 81ns 302.2mV 292.1mV 82ns AVERAGE 32 TO 32 Figure 7. Horizontal Timing, PAL –4– REV. 0 AD720/AD721 Y = 0.299R + 0.587G + 0.114B U = 0.493 (B-Y) V = 0.877 (R-Y) (continued from page 1) All required low-pass filters are on chip. After the input signals pass through a precision RGB to YUV encoding matrix, two onchip low-pass filters limit the bandwidth of the U and V color difference signals to 1.2 MHz prior to quadrature modulation of the color subcarrier; a third low-pass filter at 3.6 MHz (NTSC) or 4.4 MHz (PAL) follows the modulators to limit the harmonic content of the output. For NTSC operation, the chroma amplitude is increased by the factor 1.06 prior to summation with the luminance output. The burst signal is inserted into the Y channel in the encoding matrix. The three outputs of the encoding matrix, now transformed into Y, U, and V components, take two paths. The Y (luminance) signal is passed through a delay line consisting of a prefilter, a sampled-data delay line, and a post filter. The pre- and post-filters prevent aliasing of harmonics back into the baseband video. The overall delay is a nominal –170 ns relative to the chrominance signal, in keeping with broadcast requirements to compensate for delays introduced by the filters in the decoding process. Delays in the U and V chroma filters are matched by an on-chip sampled data delay line in the Y signal path; to prevent aliasing, prefilter at 5 MHz is included ahead of the delay line and a post filter at 5 MHz is added after the delay line to suppress harmonics in the output. These low-pass filters are optimized for minimum pulse overshoot. The overall delay is about 170 ns, which precompensates for delays in the filters used to decode the NTSC or PAL signal in a television receiver. (This precompensation delay is already present in TV broadcasts.) The U and V components pass through 4-pole modified Bessel low-pass filters with a 1.2 MHz –3 dB frequency to prevent aliasing in the balanced modulators, where they modulate a 3.579 545 000 MHz (NTSC) or 4.433 618 750 MHz (PAL) signal via a pair of balanced modulators driven in quadrature by the color subcarrier. The AD720 and AD721 are available in a 28-pin plastic leaded chip carrier for the 0°C to +70°C commercial temperature range. THEORY OF OPERATION The AD720/AD721 4FSC input drives a digital divide-by-4 circuit (two flip-flops) to create the quadrature signal. The reference phase 0° is used for the U signal. In the NTSC mode, the V signal is modulated at 90°, but in the PAL mode, the V modulation input alternates between 90° and 270° at half the line rate as required by the PAL standard. The outputs of the balanced modulators are summed and low-pass filtered to remove harmonics. Referring to the AD720/AD721 block diagram (Figure 8), the RGB inputs (each 0 mV to 714 mV in NTSC or 0 mV to 700 mV in PAL) are first encoded into luminance and color difference signals. The luminance signal is called the “Y” signal and the color-difference signals are called U and V. The RGB inputs are encoded into the YUV format using the transformation NTSC/PAL ASNC C-SYNC ENCD POWER AND GROUNDS NTSC/PAL BURST SC 90 ° 4FSC DELAYED C-SYNC C-SYNC DELAY SYNC DECODER QUADRATURE DECODER ±180° (PAL ONLY) SC 90 °/270 ° NTSC/PAL CLOCK AT 8FSC SC 0 ° +5V LOGIC +5V ANALOG –5V ANALOG ONLY AGND ANALOG DGND LOGIC BURST RED GREEN RGB-TO-YUV ENCODING MATRIX Y 5MHz 4-POLE LP PRE-FILTER U 1.2MHz 4-POLE LPF V 1.2MHz 4-POLE LPF BLUE X2 ROUT 1.5Vp-p X2 AD721 (ONLY) SAMPLEDDATA DELAY LINE DC RESTORE AND C-SYNC INSERTION 5MHz 2-POLE LP POSTFILTER NTSC/PAL BALANCED MODULATORS ∑ LUMINANCE OUTPUT* X2 ∑ 3.6MHz (NTSC) 4.4MHz (PAL) 3-POLE LPF *NOTE: THE LUMINANCE, COMPOSITE, AND CHROMINANCE OUTPUTS ARE AT TWICE NORMAL LEVELS FOR DRIVING 75Ω REVERSE-TERMINATED LINES. GOUT 1.5Vp-p X2 BOUT 1.5Vp-p Figure 8. AD720/AD721 Functional Block Diagram REV. 0 –5– –0.572V TO 1.43V NTSC –0.6V TO 1.4V PAL COMPOSITE OUTPUT* X2 –0.572V TO 2V NTSC –0.6V TO 2V PAL X2 CHROMINANCE OUTPUT* 572mVp-p NTSC 600mVp-p PAL AD720/AD721 Asserting the ENCD pin to a logical low routes the AD721’s RGB inputs through three gain-of-two bypass buffers for driving 75 Ω reverse-terminated lines, bypassing the encoder section of the AD721. The triple bypass amplifier is utilized to overcome the loading effects of a “TV-out” connection on the RGB monitor output. When a video encoder is connected to outputs of a current-out video RAMDAC or VGA controller, the R, G, and B signals to the monitor are loaded-down. This requires the use of a gain block to properly drive the monitor. The filtered output is summed with the luminance signal to create a composite video signal. The separate luminance, chrominance, and composite video signals are amplified by gain-of-two amplifiers for driving 75 Ω reverse-terminated lines. The separate luminance and chrominance outputs together are known as “S-Video.” The digital section of the AD720/AD721 is clocked by the 4FSC input. It measures the width of pulses in the composite sync input to separate vertical, horizontal, and serration pulses and to insert the subcarrier burst only after a valid horizontal sync pulse. +5V FROM ANALOG SUPPLY IOR 1 NC NC 5 ENCD 6 RDIN 7 AGND 28 27 26 NC 2 APOS 3 VNEG DGND 25 COMPOSITE SYNC INPUT CMOS LOGIC LEVEL NEGATIVE SYNC TIPS SYNC 24 75Ω 75Ω VIDEO RAM-DAC ADV47X ADV71XX 4 AGND NC ENCODE INPUT ENCODE = CMOS HIGH POWER DOWN = CMOS LOW –5V FROM ANALOG SUPPLY 0.1µF 0.1µF IOG 8 GRIN 0.1µF 9 AGND ASNC RGB TO NTSC/PAL ENCODER 75Ω 75Ω +5V FROM DIGITAL SUPPLY DPOS 23 AD720 22 +5V FROM DIGITAL SUPPLY DPOS 21 0.1µF IOB 10 BLIN 4FSC 20 CRMA APOS CMPS APOS LUMA 75Ω 75Ω VNEG 13 14 15 16 17 18 11 STND VIDEO STANDARD SELECTION INPUT NTSC = CMOS HIGH PAL = CMOS LOW AGND 12 DGND 19 4 X SUBCARRIER INPUT CMOS LOGIC LEVELS NTCS = 14.318 180MHz PAL = 17.734 480MHz 0.1µF –5V FROM ANALOG SUPPLY 75Ω LUMINANCE OUTPUT +5V FROM ANALOG SUPPLY 75Ω COMPOSITE OUTPUT 0.1µF 75Ω CHROMINANCE OUTPUT Figure 9. AD720 Application 75Ω RED OUTPUT 75Ω GREEN OUTPUT +5V FROM 75Ω ANALOG SUPPLY 0.1µF BLUE OUTPUT IOR 75Ω 2 1 NC 5 ENCD 6 RDIN 7 AGND 28 27 26 NC 3 APOS 4 AGND NC ENCODE INPUT ENCODE = CMOS HIGH BYPASS = CMOS LOW NC 0.1µF VNEG DGND 25 8 GRIN 9 AGND +5V FROM DIGITAL SUPPLY DPOS 23 0.1µF AD721 75Ω COMPOSITE SYNC INPUT CMOS LOGIC LEVEL NEGATIVE SYNC TIPS SYNC 24 75Ω VIDEO RAM-DAC ADV47X IOG ADV71XX –5V FROM ANALOG SUPPLY RGB TO NTSC/PAL ENCODER 75Ω ASNC 22 +5V FROM DIGITAL SUPPLY DPOS 21 0.1µF IOB 10 BLIN APOS LUMA 12 CMPS AGND APOS 11 STND VIDEO STANDARD SELECTION INPUT NTSC = CMOS HIGH PAL = CMOS LOW 4FSC 20 75Ω CRMA 75Ω 13 14 15 16 17 DGND 19 VNEG 0.1µF 4 X SUBCARRIER INPUT CMOS LOGIC LEVELS NTCS = 14.318 180MHz PAL = 17.734 480MHz 18 –5V FROM ANALOG SUPPLY 75Ω LUMINANCE OUTPUT +5V FROM ANALOG SUPPLY 75Ω 0.1µF COMPOSITE OUTPUT 75Ω CHROMINANCE OUTPUT Figure 10. AD721 Application –6– REV. 0 AD720/AD721 separator in the AD720/AD721 ignores horizontal sync pulses that are too long or too short. Figure 11 shows the timing windows for valid NTSC and PAL horizontal sync pulses. APPLYING THE AD720/AD721 Figure 9 shows the application of the AD720 and Figure 10 shows the application of the AD721. Note that the AD720 and AD721 differ from other analog encoders because they are dc coupled. This means that, for example, the expected RGB inputs are 0 mV to 714 mV in NTSC and 0 mV to 700 mV in PAL. The luminance, chrominance, and composite outputs are also dc coupled. These outputs can drive a 75 Ω reverseterminated load. Unused outputs should be terminated with 150 Ω resistors. NTSC: 5.30µs PAL: 5.46µs COLOR BURST The RGB data must be supplied to the AD720/AD721 at NTSC or PAL rates, interlaced format. Various VGA chip set vendors support this mode of operation. Most computers supply RGB outputs in noninterlaced format at higher data rates than NTSC and PAL, which means that “outboard” encoders must supply some form of timing conversion before the RGB data reaches the AD720/AD721. Note also that the AD720/AD721 does not have internal dc restoration and does not accept sync on green. The composite sync input is a separate, CMOS logical-level input and must be synchronized with the 4FSC input, which serves as the master clock for the AD720/AD721. The AD720/AD721 does not implement two elements of the PAL and NTSC standards. In NTSC operation, it does not support the 7.5 IRE unit setup (1 IRE unit = 7.14 mV)—this must be added via software using the RGB inputs. Many RAMDACs, such as the Analog Devices ADV471 and ADV478, offer a logic-selectable setup mode. In PAL operation, the AD720/ AD721 does not implement a 25 Hz subcarrier offset. Decoupling and Grounding Referring to the pin descriptions, the AD720/AD721 uses multiple analog grounds, digital grounds, digital positive supply inputs, analog positive supply inputs, and analog negative supply inputs in order to maximize isolation between analog and digital signal paths. The most sensitive input of the AD720/AD721 is the 4FSC pin: any noise on this pin directly affects the subcarrier and causes degradation of the picture. Digital and analog grounds should be kept separate and brought together at a single point. All power supply pins should be decoupled using 0.1 µF ceramic capacitors located as close to the AD720/AD721 as possible. In addition, ferrite beads may be slipped over the power supply leads to reduce high frequency noise. If a high speed RAM-DAC is used (e.g., capable of 80 MHz operation with subnanosecond rise times), care must be taken to properly terminate the input printed-circuit-board traces to the AD720/AD721. Otherwise, ringing on these traces may occur and cause degradation of the picture. APPLICATIONS HINTS In applying the AD720/AD721, problems may arise due to incorrect input signals. A few common situations follow. Fade to Black or White—Invalid Horizontal Sync Pulses Some systems produce sync pulses that are longer or shorter than the NTSC and PAL standards specify. The digital sync REV. 0 COMPOSITE SYNC PULSE NTSC: 2.79µs PAL: 3.21µs NTSC: 2.51µs PAL: 2.25µs IF THE TRAILING EDGE OF A COMPOSITE SYNC PULSE IS WITHIN THIS WINDOW, THE PULSE IS TREATED AS A HORIZONTAL SYNC PULSE. IF THE TRAILING EDGE IS OUTSIDE THIS WINDOW, THE PULSE IS TREATED AS AN EQUALIZING OR BLANKING PULSE. Figure 11. NTSC and PAL Timing for Valid Horizontal Sync Pulses When the horizontal sync pulses are too long or too short, a dc offset voltage (due to charge storage) increases on the output of the sampled data delay line’s auto-zero amplifier. Normally, this offset voltage is removed at the beginning of every line, as signified by the horizontal sync pulse. Without the horizontal sync pulse, the dc offset on the auto-zero amplifier increases over time (usually about three to five minutes) until it overrides the luminance information. The end result is a slow fade to black or white. Color Flickering—Asynchronous Operation The AD720/AD721 requires that its 4FSC and composite sync signals be synchronized. In most systems, when the two signals are synchronized, the composite sync signal is generated using a 4FSC signal as the reference. After every four frames, the AD720/AD721 resets the phase quadrature generator. When the CSYNC and 4FSC are synchronized, this reset is transparent to the system because the reference phase does not change. When the CSYNC and 4FSC are not synchronized, the difference between the reference phase and its new value upon reset causes an instantaneous color shift, which appears as a flickering in the color. Adding NTSC Setup The easiest way to add the 7.5 IRE unit1 setup is to use a ADV471/478 or ADV477/475 or ADV473 type RAM-DAC, which have a logic-selectable setup (called “pedestal” on some data sheets and “setup” on others). Color Fidelity A source impedance other than 37.5 Ω (75 Ωi75 Ω—a reverse-terminated 75 Ω input) can cause errors in the YUV encoding matrix, which is basically resistive and depends on the correct source impedance for accuracy. Figures 9 and 10 show the correct interface between a RAM-DAC and the AD720 and AD721 respectively, using 75 Ω reverse-terminated connections. NOTE 1 IRE unit = 7.14 mV. –7– NTSC: 2.51µs PAL: 2.25µs AD720/AD721 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Plastic Leaded Chip Carrier (PLCC) Package C1932–7.5–7/94 P-28A 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 26 4 PIN 1 IDENTIFIER 5 0.050 (1.27) BSC 0.025 (0.63) 0.015 (0.38) 25 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) TOP VIEW 0.032 (0.81) 0.026 (0.66) 19 11 12 0.040 (1.01) 0.025 (0.64) 0.456 (11.58) SQ 0.450 (11.43) 0.110 (2.79) 0.085 (2.16) 0.495 (12.57) SQ 0.485 (12.32) PRINTED IN U.S.A. 0.020 (0.50) R 18 –8– REV. 0