Order this document by MC13109/D UNIVERSAL CT–1 SUBSYSTEM INTEGRATED CIRCUIT The MC13109 integrates several of the functions required for a cordless telephone into a single integrated circuit. This significantly reduces component count, board space requirements, and external adjustments. It is designed for use in both the handset and the base. • Dual Conversion FM Receiver – Complete Dual Conversion Receiver – Antenna Input to Audio Output 80 MHz Maximum Carrier Frequency – RSSI Output – Carrier Detect Output with Programmable Threshold – Comparator for Data Recovery – Operates with Either a Quad Coil or Ceramic Discriminator • • • • • 52 1 FB SUFFIX PLASTIC PACKAGE CASE 848B (QFP–52) Compander – Expandor Includes Mute, Digital Volume Control and Speaker Driver – Compressor Includes Mute, ALC and Limiter Dual Universal Programmable PLL – Supports New 25 Channel U.S. Standard with No External Switches – Universal Design for Domestic and Foreign CT–1 Standards – Digitally Controlled Via a Serial Interface Port – Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit Programmable Counter and 2nd LO with 12–Bit Counter – Transmit Section Contains Phase Detector and 14–Bit Counter – MPU Clock Output Eliminates Need for MPU Crystal 48 1 FTA SUFFIX PLASTIC PACKAGE CASE 932 (Thin QFP) Supply Voltage Monitor – Externally Adjustable Trip Point ORDERING INFORMATION 2.0 to 5.5 V Operation with One–Third the Power Consumption of Competing Devices AN1575: Refer to Application Note for a List of “Worldwide Cordless Telephone Frequencies” (Chapter 8 Addendum of DL128 Data Book) Device Tested Operating Temperature Range Package MC13109FB MC13109FTA QFP–52 TA = –20° to +85°C TQFP–48 Simplified Block Diagram Rx In 1st Mixer 2nd Mixer 1st LO PLL 2nd LO PLL Limiting IF Amplifier RSSI Detector Mute Expander Rx Out Carrier Detect Tx In Data Out Mute Compressor µP Serial Interface Tx Phase Detector Low Battery Detect SPI Tx Out Tx VCO Low Battery Indicator This device contains 6,609 active transistors. Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA Rev 1 1 MC13109 Figure 1. MC13109FB Test Circuit RX_Audio Ext_C_In R30 49.9k R29 49.9k VCC/2 R31 100k C41 C42 0.47 5.0nF µF C43 0.1µF C6 0.022µF C7 15pF 7 8 EN Clk 11 Clk Out 12 N/A 13 C8 18pF L3 0.22µH C9 33pF C10 68pF R5 22.1k 14 Q1 MPS5179 VCC R6 1.0k 15 C15 10pF C13 0.01 µF 1st LO VCO Half Supply Reference 2nd LO 1st LO RSSI Expander VB E + – Spkr Cap Mute Spkr Amp Rx Mute Data Amp Pre– Amp + Vol Ctrl Mix2 Out 29 28 LS09 EN_5.0V 7 Open DA_In Data_5.0V 10 9 14 EN_5.0V DA U1 Out DB 8 R16 49.9k R9 1.0k VCC Gnd 7 LS09 Clk_5.0V VCCE 4 5 14 L2 Q Coil C28 0.1µF R22 12k TOKO A7MES–12597Z R20 49.9k R21 8.2k Det_Out R19 49.9k C26 0.01µF C25 1.0µF Audio_In_In C21 0.033µF C22 0.1µF R17 5.62k C18 1.0µF C23 0.001µF R18 20k E_Out R11 1.0k DA R10 1.0k Clk_5.0V R23 10.2 VCC C29 10µF C30 0.1µF Open U1 Out 6 DB VCC Gnd 7 LS09 VCCA C33 0.1µF 455k In C31 0.1µF VCC RF C20 0.1µF C19 10µF Ext_IF R23 1.5k C32 0.1µF DA_Fil Gnd VCC 14 R24 10 C27 0.1µF Pre_Amp DB 12 CF2 N/A Open 13 C34 27 VB 17 18 19 20 21 22 23 24 25 26 BD DA SA SA E VCC DA Pre– Rx Det RSSI Out Out Out In Out Audio In Amp Audio Out Out In C16 R13 510 R12 3.9k pF 100k R15 C24 49.9k 510pF VCCD Out 11 Out 1.0µF Lim In 16 U1 Gnd 3 Gnd RF 31 Lim C1 Lim C2 30 – C12 33pF DA VB 34 32 Carrier Detect In 2 Mix1 Out Mix2 In 33 330 1 Mix1 In1 35 2nd Mix Ref Low Battery Detect Status CD Out Out/ Hardware Interrupt R7 22.1k C11 47pF 36 PLL Vref 9 10 Compressor 37 1st LO Limiter Data C14 1.0µF R8 100k R4 100k 1N5140 Tx VCO C48 1.0µF Ext Tx_VCO R3 32.4k Ecap VCCA 1st Mix ÷1 ÷4 ÷25 Out Mix1 In2 38 IF Amp/ Limiter R2 32.4k 3 39 In 2 C36 0.01µF Detector C5 0.1µF + – ALC 1 50 R27 49.9k Tx Mute Bandgap Reference R1 1.5k Mix1_In VCC C40 1.0µF 12b Prog Ref Ctr 14b Prog Rx Ctr C3 0.047µF Spl Amp 2.2V Voltage Regulator C4 0.01µF C35 0.01µF Open LO1 VB + – 2nd LO R x Phase Detect LO2 Out 2 PLL Vref 3 Rx PD 4 Gnd PLL 5 Tx PD 6 C44 10µF VCCA VB µ P Serial Interface C2 4.3pF C45 0.1µF R33 3.0k 1 T x Phase Detect R34 1.5k 10.24 MHz 14b Prog Tx Ctr LO2 In XL1 R35 32.4k 2nd LO 10.240 C1 9–35pF C46 Open C38 5.0nF Spl Amp Tx Gnd Vcap LO1 LO1 C Tx Amp Lim In Out Cap C In Out In In Audio Ctrl Out N/A Ref Out 52 51 50 49 48 47 46 45 44 43 42 41 40 Prog Clk Ctr 0.0047 µF C30 1.0µF CF2 455 MHz Ext_Ref L1 C47 MIC_ 1.0µF Amp R28 Out 49.9k CF1 10.7 MHz R32 100k R36 22.1k TX_In Open VCCE Ext_SA_In 1 2 DA DB U1 Out 3 Gnd V 7 14 CC LS09 R14 130 C17 47µF Exp_IF SA_Out 5.0V 2 MOTOROLA ANALOG IC DEVICE DATA MC13109 Figure 2. MC13109FTA Test Circuit RX_Audio TX_In Ext_C_In Open VCCE C47 1.0µF R2 32.4k R1 1.5k 3 5 Spl Amp ÷1 C7 15pF C14 1.0 µF C8 18pF R6 1.0k C12 33pF µ P Serial Interface 9 10 R8 100k Clk Out 11 13 C10 68pF CD Out/ Hardware Interrupt C13 0.01 µF Q1 MPS5179 14 13 DA 12 DB BD Out DA Out R12 100k Data_ 5.0 V EN_5.0V Data_5.0V 10 DA RSSI 1 In Gnd RF 2 Gnd SA Out 17 SA In 18 19 E VCC Out Audio Pre– Amp + C16 510pF DA In 21 Pre– Amp Out 25 22 23 24 Rx Det RSSI Audio Out In C24 510pF R15 49.9k R19 49.9k C17 47µF 26 – VB 20 C32 0.1µF Lim C2 C31 0.1µF 27 Data Amp Vol Ctrl Lim C1 28 Rx Mute 3 Out C33 Ext_IF 0.1µF R23 1.5k R24 10 455k In R23 10.2 VCC RF C30 0.1µF Q Coil C27 0.1µF C29 10µF VCC Det_Out R21 8.2k C26 0.01µF R20 49.9k R22 12k L2 TOKO A7MES–12597Z C25 1.0µF Pre_Amp C28 0.1µF Audio_In_In SA_Out DA_Fil C22 0.1µF R18 20k R17 Clk_5.0 V Out 8 9 DB 14 Gnd 7 VCC LS09 Mix2 Out Lim In VCCE Open U1 3 Out Mix2 In 29 R14 130 Open 14 V Gnd 7 CC LS09 16 VCCD U1 Out 11 31 In 2 CF2 E + – Spkr Cap Mute Spkr Amp 15 VCC 5.0V 2nd Mix Carrier Detect Expander R13 3.9k C15 10pF 32 2nd LO VB 12 R7 22.1k Half Supply Reference Ref Low Battery Detect Clk VCC L3 0.22µH C9 33pF Data EN 1 VCC 330 1st LO 2.2V Voltage Regulator Ext 33 Mix1 Out C34 1.0µF VB 30 14b Prog Tx Ctr R4 100k 1st LO Compressor ÷4 ÷25 Mix1 In1 50 C36 0.01µF Mix1 In2 C35 0.01µF 34 PLL Vref Prog Clk Ctr 1N5140 C11 47pF 7 8 C6 0.022µF R5 22.1k E Cap C48 Tx 1.0µF VCO 35 1st Mix Limiter T x Phase Detect VCCA Tx_VCO Tx Mute ALC 6 R3 32.4k + – + – 12b Prog Ref Ctr 4 Tx PD VB 2nd LO 36 VB Open R9 1.0k R11 1.0k R10 1.0k VCCA R16 49.9k C18 1.0µF C19 10µF DA_In C21 5.62k 0.033µF C23 0.001µF C20 0.1µF EN_5.0V 4 DA U1 Out 6 5 DB 14 Gnd VCC LS09 7 Clk_5.0V 1 2 U1 DA E_Out Out 3 DB 14 V Gnd 7 CC LS09 MOTOROLA ANALOG IC DEVICE DATA CF1 10.7 MHz 2 Gnd PLL C5 0.1µF Tx Gnd Vcap LO1 LO1 In Audio In Ctrl Out 41 40 39 38 37 Amp Out C In 43 42 1 Rx PD C4 0.01µF 44 IF Amp/ Limiter C44 10µF PLL Vref C Cap 45 Mix1_In Detector LO2 Out Lim Out 46 Bandgap Reference C2 4.3pF 10.24 MHz Spl Amp In C41 0.47 µF LO1 R27 49.9k C40 1.0µF 14b Prog R x Ctr R33 3.0k C3 0.047µF LO2 In XL1 2nd LO 10.240 C1 9–35pF Tx Ref Out 48 47 R x Phase Detect C45 0.1µF Open R30 49.9k Open L1 CF2 455 MHz C43 0.1µF R28 49.9k C38 5.0nF VCCA C42 5.0nF R35 32.4k R34 1.5k C30 1.0µF R29 49.9k R31 100k C46 0.0047 µF R36 22.1k MIC_ Amp Out VCC/2 Ext_Ref 1st LO VCO R32 100k Ext_SA_In Exp_IF 3 MC13109 MAXIMUM RATINGS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ Symbol Value Unit Power Supply Voltage Rating VCC – 0.5 to + 5.5 Vdc Junction Temperature TJ – 65 to +150 °C NOTE: 1. Devices should not be operated at these limits. The “Recommended Operating Conditions” provide for actual device operation. 2. ESD data available upon request. RECOMMENDED OPERATING CONDITIONS Characteristic Min Typ Max Unit VCC 2.0 – 5.5 Vdc Operating Ambient Temperature –20 – 85 °C NOTE: All limits are not necessarily functional concurrently. ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C, RF In = 46.61 MHz, fDEV = ± 3.0 kHz, fmod = 1.0 kHz; Test Circuit Figure 1.) Characteristic POWER SUPPLY Static Current Active Mode (VCC = 2.6 V) Active Mode (VCC = 3.6 V) Receive Mode (VCC = 2.6 V) Receive Mode (VCC = 3.6 V) Standby Mode (VCC = 2.6 V) Standby Mode (VCC = 3.6 V) Inactive Mode (VCC = 2.6 V) Inactive Mode (VCC = 3.6 V) 4 Min Typ Max Unit – – – – – – – – 6.7 7.1 4.3 4.5 300 600 40 56 12 – 7.0 – 600 – 80 – mA mA mA mA µA µA µA µA MOTOROLA ANALOG IC DEVICE DATA MC13109 ELECTRICAL CHARACTERISTICS (continued) FM Receiver The FM receivers can be used with either a quad coil or a ceramic resonator. The FM receiver and 1st LO have been designed to work for all country channels, including 25 channel U.S., without the need for any external switching circuitry (see Figure 29). (Test Conditions: VCC = 2.6 V, TA = 25°C, fO = 46.61 MHz, fDEV = ± 3.0 kHz, fmod = 1.0 kHz.) Characteristic Condition Input Pin Measure Pin Symbol Min Typ Max Unit Sensitivity (Input for 12 dB SINAD) Matched Impedance Differential Input Mix1 In1/2 Det Out VSIN – 0.7 – µVrms 1st Mixer Conversion Gain Vin = 1.0 mVrms, with CF1 Load Mix1 In1/2 CF1 MXgain1 – 10 – dB 2nd Mixer Conversion Gain Vin = 3.0 mVrms, with CF2 Load Mix2 In CF2 MXgain2 – 20 – dB 1st and 2nd Mixer Gain Total Vin = 1.0 mVrms, with CF1 and CF2 Load Mix1 In1/2 CF2 MXgainT 24 30 – dB 1st Mixer Input Impedance – – Mix1 In1 Mix1 In2 Zin1 – 1.0 – kΩ 2nd Mixer Input Impedance – – Mix2 In Zin2 – 3.0 – kΩ 1st Mixer Output Impedance – – Mix1 Out Zout1 – 330 – Ω 2nd Mixer Output Impedance – – Mix2 Out Zout2 – 1.5 – kΩ IF – 3.0 dB Limiting Sensitivity fin = 455 kHz Lim In Det Out IF Sens – 55 – µVrms Total Harmonic Distortion (CCITT Filter) With RC = 8.2 kΩ/ 0.01 µF Filter at Det Out Mix1 In1/2 Det Out THD – 0.7 – % Recovered Audio With RC = 8.2 kΩ/ 0.01 µF Filter at Det Out Mix1 In1/2 Det Out AFO 80 100 154 mVrms – Lim In Det Out BW – 20 – kHz Signal to Noise Ratio Vin = 10 mVrms, RC = 8.2 kΩ/0.01 µF Mix1 In1/2 Det Out SN – 49 – dB AM Rejection Ratio 30% AM, Vin = 10 mVrms, RC = 8.2 kΩ/0.001 µF Mix1 In1/2 Det Out AMR – 37 – dB First Mixer 3rd Order Intercept (Input Referred) Matched Impedance Input Mix1 In1/2 Mix1 Out TOImix1 – –10 – dBm Second Mixer 3rd Order Intercept (Input Referred) Matched Impedance Input Mix2 In Mix2 Out TOImix2 – – 27 – dBm – Det Out ZO – 870 – Ω ā Demodulator Bandwidth Detector Output Impedance – MOTOROLA ANALOG IC DEVICE DATA 5 MC13109 ELECTRICAL CHARACTERISTICS (continued) RSSI/Carrier Detect Connect 0.01 µF to Gnd from “RSSI” output pin to form the carrier detect filter. “CD Out” is an open collector output which requires an external 100 kΩ pull–up resistor to VCC. The carrier detect threshold is programmable through the MPU interface. (RL = 100 kΩ, VCC = 2.6 V, TA = 25°C.) Condition Input Pin Measure Pin Symbol Min Typ Max Unit – Mix1 In RSSI RSSI – 65 – dB CD Threshold Adjust = (10100) Mix1 In CD Out VT – 22.5 – µVrms – Mix1 In CD Out Hys – 2.0 – dB Output High Voltage Vin = 0 µVrms, RL = 100 kΩ, CD = (10100) Mix1 In CD Out VOH VCC – 0.1 2.6 – V Output Low Voltage Vin = 100 µVrms, RL = 100 kΩ, CD = (10100) Mix1 In CD Out VOL – 0.01 0.4 V Carrier Sense Threshold Adjustment Range Programmable through MPU Interface – – VTrange – 20 – 11 dB Carrier Sense Threshold – Number of Steps Programmable through MPU Interface – – VTn – 32 – – Characteristic RSSI Output Current Dynamic Range Carrier Sense Threshold Hysteresis Data Amp Comparator (see Figure 4) Inverting hysteresis comparator. Open collector output with internal 100 kΩ pull–up resistor. A band pass filter is connected between the “Det Out” pin and the “DA In” pin with component values as shown in the attached block diagram. The “DA In” input signal is ac coupled. (VCC = 2.6 V, TA = 25°C) Condition Input Pin Measure Pin Symbol Min Typ Max Unit Hysteresis – DA In DA Out Hys 30 40 50 mV Threshold Voltage – DA In DA Out VT VCC – 0.9 VCC – 0.7 VCC – 0.5 V Input Impedance – – DA In ZI – 11 – kΩ Output Impedance – – DA Out ZO – 100 – kΩ Characteristic Output High Voltage Vin = VCC – 1.0 V, IOH = 0 mA DA In DA Out VOH VCC – 0.1 2.6 – V Output Low Voltage Vin = VCC – 0.4 V, IOL = 0 mA DA In DA Out VOL – 0.03 0.4 V 6 MOTOROLA ANALOG IC DEVICE DATA MC13109 ELECTRICAL CHARACTERISTICS (continued) Pre–Amplifier/Expander/Rx Mute/Volume Control (See Figure 4) the half supply reference so the input and output swing The Pre–Amplifier is an inverting rail–to–rail output swing capability will increase as the supply voltage increases. The operational amplifier with the non–inverting input terminal volume control can be adjusted through the MPU interface. connected to the internal VB half supply reference. External The “Rx Audio In” input signal is ac coupled. resistors and capacitors can be connected to set the gain and frequency response. The expander analog ground is set to (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, Set External Pre–Amplifier R’s for Gain of 1, Volume Control = (0111).) Condition Input Pin Measure Pin Symbol Min Typ Max Unit Pre–Amp Open Loop Gain – Rx Audio In Pre–Amp AVOL – 60 – dB Pre–Amp Gain Bandwidth – Rx Audio In Pre–Amp GBW – 100 – kHz Pre–Amp Maximum Output Swing RL = 10 kΩ Rx Audio In Pre–Amp VOmax – VCC – 0.3 – Vpp Expander 0 dB Gain Level Vin = –10 dBV Rx Audio In E Out G –3.0 –0.11 3.0 dB Expander Gain Tracking g Vin = –20 dBV, Output Relative to G Vin = –30 30 dBV dBV, O Output Relative to G Rx Audio In E Out Gt –21 –19.65 –19 dB –42 42 –39.42 39 42 –37 3 Total Harmonic Distortion Vin = –10 dBV Rx Audio In E Out THD – 0.5 – % Maximum Output Voltage Increase input voltage until output voltage THD = 5%, then measure output voltage. RL = 10 kΩ Rx Audio In E Out VOmax – –5.0 – dBV Attack Time Ecap = 1.0 µF, Rfilt = 20 kΩ (See Appendix B) Rx Audio In E Out ta – 3.0 – ms Release Time Ecap = 1.0 µF, Rfilt = 20 kΩ (See Appendix B) Rx Audio In E Out tr – 13.5 – ms Compressor to Expander Crosstalk V (Rx Audio In) = 0 Vrms, Vin = –10 dBV C In E Out CT – – –70 dB Rx Mute Vin = –10 dBV No popping detectable during Rx Mute transitions Rx Audio In E Out Me – –70 – dB Volume Control Range Programmable through MPU Interface – – VCrange –14 – 16 dB Volume Control Steps Programmable through MPU Interface – – VCn – 16 – – Characteristic MOTOROLA ANALOG IC DEVICE DATA 7 MC13109 ELECTRICAL CHARACTERISTICS (continued) Speaker Amplifier/SP Mute The Speaker Amplifier is an inverting rail–to–rail operational amplifier. The non–inverting input terminal is connected to the internal VB half supply reference. External resistors and capacitors are used to set the gain and frequency response. The “SA In” input is ac coupled. (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Characteristic Maximum Output Swing g SP Mute Input Pin Measure Pin Symbol Min Typ Max Unit VCC = 2.3 V, RL = 130 Ω VCC = 2.3 V, RL = 600 Ω VCC = 3.4 3 4 V, V RL = 600 Ω SA In SA Out VOmax – 0.8 – Vpp – 2.0 – – 3.0 30 – Vin = –20 dBV RL = 130 Ω No popping detectable during SP Mute transitions SA In – –70 – Condition SA Out Mic Amplifier (See Figure 6) The Mic Amplifier is an inverting rail–to–rail output operational amplifier with the non–inverting input terminal connected to the internal VB half supply reference. External Msp dB resistors and capacitors are connected to set the gain and frequency response. The “Tx In” input is ac coupled. (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Characteristic Open Loop Gain Gain Bandwidth Maximum Output Swing 8 Condition Input Pin Measure Pin Symbol Min Typ Max Unit – Tx In Amp Out AVOL – 60 – dB – Tx In Amp Out GBW – 100 – kHz RL = 10 kΩ Tx In Amp Out VOmax – VCC – 0.3 – Vpp MOTOROLA ANALOG IC DEVICE DATA MC13109 ELECTRICAL CHARACTERISTICS (continued) Compressor/ALC/Tx Mute/Limiter (See Figure 5) The compressor analog gound is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. The “C In” input is ac coupled. The ALC (Automatic Level Control) provides a soft limit to the output signal swing as the input voltage increases slowly (i.e., a sine wave is maintained). The Limiter circuit limits rapidly changing signal levels by clipping the signal peaks. The ALC and/or Limiter can be disabled through the MPU serial interface. (Test Conditions: VCC = 2.6 V, fin = 1.0 kHz, TA = 25°C.) Condition Input Pin Measure Pin Symbol Min Typ Max Unit Compressor 0 dB Gain Level Vin = –10 dBV, ALC disabled, Limiter disabled C In Lim Out G –3.0 –0.17 3.0 dB Compressor Gain Tracking Vin = –30 dBV, Output Relative to G C In Lim Out Gt –11 –10.23 –9.0 dB –23 –20.23 –17 Characteristic Vin = –50 dBV, Output Relative to G Maximum Compressor Gain Vin –70 dBV C In Lim Out AVmax – 30 – dB Total Harmonic Distortion Vin –10 dBV, ALC disabled, Limiter disabled C In Lim Out THD – 0.5 – % C In Lim Out Zin – 16 – kΩ Input Impedance – Attack Time Ccap = 1.0 µF, Rfilt = 20 kΩ (see Appendix B) C In Lim Out ta – 3.0 – ms Release Time Ccap = 1.0 µF, Rfilt = 20 kΩ (see Appendix B) C In Lim Out tr – 13.5 – ms Expander to Compressor Crosstalk V (C In) = 0 Vrms, Vin = –10 dBV Rx Audio In Lim Out CT – – –40 dB Tx Data Mute Vin = –10 dBV, ALC disabled No popping detectable during Rx Mute transitions C In Lim Out Me – –70 – dB – C In Lim Out DR –24 – –2.5 dBV Vin = –18 dBV Vin = –2.5 dBV C In Lim Out ALCout – –16 – dBV – –12 – ALC disabled C In – 0.8 – ALC Dynamic Range ALC Output Level Limiter Output Level MOTOROLA ANALOG IC DEVICE DATA Tx Out Vlim Vpp 9 MC13109 ELECTRICAL CHARACTERISTICS (continued) Splatter Amplifier (see Figure 7) The Splatter Amplifier is an inverting rail–to–rail output operational amplifier with the non–inverting input terminal connected to the internal VB half supply reference. External resistors and capacitors can be connected to set the gain and frequency response. The “Spl Amp In” input is ac coupled. (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External resistors Set for Gain of 1.) Characteristic Condition Input Pin Measure Pin Symbol Min Typ Max Unit Open Loop Gain – Spl Amp In Tx Out AVOL – 60 – dB Gain Bandwidth – Spl Amp In Tx Out GBW – 100 – kHz RL = 10 kΩ Spl Amp In Tx Out VOmax – VCC – 0.3 – Vpp Maximum Output Swing Tx Audio Path Recommendation The recommended configuration for the Tx Audio path includes setting the Microphone Amplifier gain to 16 dB using the external gain setting resistors and setting the Splatter Amplifier gain to 9.0 dB using the external gain setting resistors. With these gain values, the total Tx Path transfer characteristic is shown in Figure 7. PLL Voltage Regulator The PLL supply voltage is regulated to a nominal of 2.2 V. The “VCC Audio” pin is the supply voltage for the internal voltage regulator. The “PLL Vref” pin is the 2.2 V regulated output voltage. Two capacitors with 10 µF and 0.01 µF values must be connected to the “PLL Vref” pin to filter and stabilize this regulated voltage. The voltage regulator provides power for the 2nd LO, Rx and Tx PLL’s, and MPU Interface. The voltage regulator can also be used to provide a regulated supply voltage for external IC’s. Rx and Tx PLL loop performance are independent of the power supply voltage when the voltage regulator is used. The voltage regulator requires about 200 mV of “headroom”. When the power supply decreases to within about 200 mV of the output voltage, the regulator will go out of regulation but the output voltage will not turn off. Instead, the output voltage will maintain about a 200 mV delta to the power supply voltage as the power supply voltage continues to decrease. The “PLL Vref” pin can be connected to “VCC Audio” by the external wiring if voltage higher than 2.2 V is required. But it should not be connected to other supply except “VCC Audio”. The voltage regulator is “on” in the Active and Rx modes. In the Standby and Inactive modes, the voltage regulator is turned off to reduce current drain and the “PLL Vref” pin is internally connected to “VCC Audio” (i.e., the supply voltage is maintained but is now unregulated). (Test Conditions: VCC = 2.6 V, TA = 25°C.) Characteristic Output Voltge Level Condition VCC = 2.6 V, OL= 0 mA Input Pin Measure Pin Symbol Min Typ Max Unit – VCC PLL Vout 1.9 2.2 2.5 V Line Regulation IL = 0 mA, VCC = 2.6 to 5.5 V VCC VCC PLL Regline – 1.43 40 mV Load Regulation VCC = 2.6 V, IL = 0 to 1.0 mA VCC VCC PLL Regload – –1.86 40 mV Drop–Out Voltage IL = 0 mA – – DO – – Vout + 200 mV 10 MOTOROLA ANALOG IC DEVICE DATA MC13109 ELECTRICAL CHARACTERISTICS (continued) Low Battery Detect An external resistor divider is connected to the “Ref” input pin to set the threshold for the low battery detect. The voltage at the “Ref” input pin is compared to an internal 1.23 V Bandgap reference voltage. The “BD Out” pin is open collector and requires and external pull–up resistor to VCC. (Test Conditions: VCC = 2.6 V, TA = 25°C.) Input Pin Measure Pin Take average of rising and falling threshold Ref – Condition Characteristic Average Threshold Voltage Hysteresis Symbol Min Typ Max Unit Ref/ BD Out Threshold – 1.23 – V Ref Ref/ BD Out Hys – 4.0 – mV – Ref Iin –50 5.71 +50 nA Input Current Vin = 1.6 V Output High Voltage Vref = 1.6, RL = 3.9 kΩ Ref BD Out VOH VCC – 0.1 2.6 – V Output Low Voltage Vref = 0.9, RL = 3.9 kΩ Ref BD Out VOL – 0.12 0.4 V Figure 3. Data Amp Operation Data Amp Data Signal Hysteresis Data Amp Output Figure 4. Typical Expander Response 10 Expander, E Out (dBV) 0 –10 – 20 E Out = –5.0 dBV Typical at THD = 5 % – 30 – 40 – 50 – 60 – 40 – 30 – 20 –10 0 10 Rx AUDIO IN (dBV) MOTOROLA ANALOG IC DEVICE DATA 11 Figure 6. Total Tx Path, Mic Amp Gain = 16 dB, Splatter Amp Gain = 9.0 dB Figure 5. Typical Compressor/ALC/Limiter Response 0 10 (Rapidly Changing Limited Signals) Vin > = –12 dBV, Vout = 0.8 Vpp –10 OUTPUT LEVEL, Tx OUTPUT (dBV) COMPRESSOR LEVEL OUTPUT, LIM OUT (dBV) MC13109 Vin = – 2.5 dBV, Vout = –12 dBV –20 –30 Vin = –24 dBV, Vout = –17 dBV (Slowly Changing ALC Signals) –40 –50 –80 –60 –50 –40 –30 –20 –10 (Rapidly Changing Limited Signals) Vin > = –28 dBV, Vout = 2.25 Vpp 0 Vin = –18.5 dBV, Vout = –3.0 dBV –10 –20 Vin = –40 dBV, Vout = –8.0 dBV (Slowly Changing ALC Signals) –30 –40 –80 0 –60 –50 COMPRESSOR, Cin LEVEL INPUT (dBV) –40 –30 –20 0 –10 INPUT LEVEL, Tx INPUT (dBV) Figure 7. MC13109FTA Internal I/O Block Diagram LO2 In Ref Tx Out Spl Amp In 48 47 46 1 Lim Out C Cap C In Amp Out Tx In Gnd Audio Vcap Ctrl LO1 Out LO1 In 45 44 43 42 41 40 39 38 37 20k 20k 12k 8.0k 12k 2 PLL Vref 3 Rx PD 4 200 Mix1 In1 35 Mix1 In2 34 Mix1 Out 33 VB 32 Mix2 In 31 Mix2 Out 30 Gnd RF 29 Lim In 28 Lim C1 27 Lim C2 26 VCC RF 25 Q Coil 8.0k 200 LO2 Out 36 55k 20k 200 PLL Vref 1.5k 6.9k 100 200 PLL Vref Gnd PLL 1.0k 100k VCC Audio 6.9k 1.0k 200 100k 150k 5 3.0k 200 63k 80k Tx PD 20k PLL Vref 6 14k 186k PLL Vref Ecap 200 Tx VCO 1.2k 7 1.0k 36k PLL Vref 8 1.5k 2.0 k 200 36k 200 200 Data 9 200 200 200 EN 10 Clk 11 1.5k 30k 51k 100k 10k 200 200 10k 22p 200 Clk Out 30k 12 13 CD Out/ Hardware Interrupt 12 14 15 16 17 18 19 20 21 22 23 24 BD Out DA Out SA Out SA In E Out VCC Audio DA In Pre– Amp Out Rx Audio In Det Out RSSI MOTOROLA ANALOG IC DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13109 PIN FUNCTION DESCRIPTION 48–TQFP Pin 52–QFP Pin Symbol Type 1 2 1 2 LO2 In LO2 Out – 3 3 PLL Vref Supply Voltage Regulator output pin. The internal voltage regulator provides a stable power supply voltage for the Rx and Tx PLL’s and can also be used as a regulated supply voltage for the other IC’s. 4 4 Rx PD Output Three state voltage output of the Rx Phase Detector. This pin is either “high”, “low”, or “high impedance” depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Rx PLL loop filter. It is important to minimize the line length and capacitance of this pin. 5 5 Gnd PLL Gnd 6 6 Tx PD Output 7 7 E Cap – 8 8 Tx VCO Input Transmit divide counter input which is driven by an ac coupled external transmit loop VCO. The minimum signal level is 200 mVpp @ 80.0 MHz. This pin also functions as the test mode input for the counter tests. 9 10 11 9 10 11 Data EN Clk Input Microprocessor serial interface input pins for programming various counters and control functions. 12 12 Clk Out Output Microprocesor Clock Output which is derived from the 2nd LO crystal oscillator and a programmable divider. It can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. The driver has an internal resistor in series with the output whch can be combined with an external capacitor to form a low pass filter to reduce radiated noise on the PCB. This output also functions as the output for the counter test modes. N/A 14 Status Out Output This pin indicates when the internal latches may have lost memory due to a power glitch. 13 15 CD Out/ Hardware Interrupt Output/ Input Dual function pin; 1) Carrier detect output (open collector with external 100 kΩ pull–up resistor. 2) Hardware interrupt input which can be used to “wake–up” from Inactive Mode. 14 16 BD Out Output Low battery detect output (open collector with external pull–up resistor). 15 17 DA Out Output Data amplifier output (open collector with internal 100 kΩ pull–up resistor). 16 18 SA Out Output Speaker amplifier output. 17 19 SA In Input 18 20 E Out Output Expander output. 19 21 VCC Audio Supply VCC supply for audio section. 20 22 DA In Input 21 23 Pre–Amp Out Output 22 24 Rx Audio In Input 23 25 Det Out Output 24 26 RSSI – Receive signal strength indicator filter capacitor. N/A 27 N/A – Note used. 25 28 Q Coil – A quad coil or ceramic discriminator are connected to this pin. 26 29 VCC RF Supply 27 28 30 31 Lim C2 Lim C1 – MOTOROLA ANALOG IC DEVICE DATA Description These pins form the PLL reference oscillator when connected to an external parallel–resonant crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (LO2) for the RF receiver. Ground pin for PLL section of IC. Three state voltage output of the Tx Phase Detector. This pin is either “high”, “low”, or “high impedance” depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Tx PLL loop filter. It is important to minimize the line length and capacitance on this pin. Expander rectifier filter capacitor pin. Connect capacitor to VCC. Speaker amplifier input (ac coupled). Data amplifier input (ac coupled). Pre–amplifier output for connection of pre–amplifier feedback resistor. Rx audio input to pre–amplifier (ac coupled). Audio output from FM detector. VCC supply for RF receiver section. IF amplifier/limiter capacitor pins. 13 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13109 PIN FUNCTION DESCRIPTION (continued) 48–TQFP Pin 52–QFP Pin Symbol Type Description 29 32 Lim In Input Signal input for IF amplifier/limiter. 30 33 Gnd RF Gnd Ground pin for RF section of the IC. 31 34 Mix2 Out Output 32 35 Mix2 In Input 33 36 VB – 34 37 Mix1 Out Output 35 38 Mix1 In2 Input Negative polarity first mixer input. 36 39 Mix1 In1 Input Positive polarity first mixer input. 37 38 40 41 LO1 In LO1 Out – Tank elements for 1st LO multivibrator oscillator are connected to these pins. 39 42 Vcap Ctrl – 1st LO varactor control pin. 40 43 Gnd Audio Gnd Ground for audio section of the IC. 41 44 Tx In Input Tx path input to Microphone Amplifier (ac coupled). 42 45 Amp Out Output 43 46 C In Input 44 47 C Cap – 45 48 Lim Out Output 46 49 Spl Amp In Input 47 50 Tx Out Output 48 51 Ref Input N/A 52 N/A – Second mixer output. Second mixer input. Internal half supply analog ground reference. First mixer output. Microphone amplifier output. Compressor input (ac coupled). Compressor rectifier filter capacitor pin. Connect capacitor to VCC. Tx path limiter output. Splatter amplifier input (ac coupled). Tx path audio output. Reference voltage input for low battery detect. Not used. Power Supply Voltage This circuit is used in a cordless telephone handset and base unit. The handset is battery powered and can operate on two ro three NiCad cells or on 5.0 V power. PLL Frequency Synthesizer General Description Figure 8 shows a simplified block diagram of the programmable universal dual phase locked loop (PLL). This dual PLL is fully programmable thorugh the MCU serial interface and supports most country channel frequencies including USA (25 ch), France, Spain, Australia, Korea, New Zealand, U.K., Netherlands and China (see channel frequency tables in Appendix A). The 2nd local oscillator and reference divider provide the reference frequency for the Rx and Tx PLL loops. The 14 programmed divider value for the reference divider is selected based on the crystal frequency and the desired Rx and Tx reference frequency values. Additional divide by 25 and divide by 4 blocks are provided to allow for generation of the 1.0 kHz and 6.25 kHz reference frequencies required for the U.K. The 14–bit Tx counter is programmed for the desired transmit channel frequency. The 14–bit Rx counter is programmed for the desired first local oscillator frequency. All counters power up in the proper default state for USA channel #6 and for a 10.24 MHz reference frequency crystal. Internal fixed capacitors can be connected to the tank circuit of the 1st LO through microprocessor control to extend the sensitivity of the 1st LO for U.S. 25 channel operation. MOTOROLA ANALOG IC DEVICE DATA MC13109 Figure 8. Dual PLL Simplified Block Diagram LO2 In 1, 1 LO2 Out 2, 2 14–b Programmable Tx Counter Tx VCO U.K. Base Tx Ref Tx PD ÷ 25 12–b Programmable ÷4 Reference ÷1 Counter 8, 8 Tx Phase Detector 6, 6 Tx VCO LPF U.K. Handset U.K. Base Rx Ref U.K. Handset Rx PD Rx Phase Detector 4, 4 Vcap Ctrl LPF 39, 42 LO1 In 14–b Programmable Rx Counter 37, 40 LO1 Out 1st LO 38, 41 ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C) Characteristic Condition Measure Pin Symbol Min Max Unit PLL PIN DC Input Voltage Low – Data Clk EN Hardware Int. VIL – 0.3 V Input Voltage High – Data Clk EN VIH “PLL Vref” – 0.3 “VCC Audio” V Data Clk EN IIL –5.0 – µA Input Current Low Vin = 0.3 V Input Current High Vin = (VCC Audio) – 0.3 Data Clk EN IIH – 5.0 µA Hysteresis Voltage – Data Clk EN Vhys 1.0 – V Output Current High – Rx PD Tx PD IOH – – 0.7 mA Output Current Low – Rx PD Tx PD IOL 0.7 – mA Output Voltage Low IIL = 0.7 mA Rx PD Tx PD VOL – (PLL Vref)* 0.2 V Output Voltage High IIH = – 0. 7mA Rx PD Tx PD VOH (PLL Vref)* 0.8 – V Tri–State Leakage Current V = 1.2 V Rx PD Tx PD IOZ – 50 50 nA Input Capacitance – Data Clk EN Cin – 8.0 pF Output Capacitance – Rx PD Tx PD Cout – 8.0 pF MOTOROLA ANALOG IC DEVICE DATA 15 MC13109 ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C) Characteristic Measure Pin Condition Symbol Min Max Unit PLL PIN INTERFACE EN to Clk Setup Time – EN, Clk tsuEC 200 – ns Data to Clk Setup Time – Data, Clk tsuDC 100 – ns Hold Time – Data, Clk th 90 – ns Recovery Time – EN, Clk trec 90 – ns Input Pulse Width – EN, Clk tw 100 – ns Input Rise and Fall Time – Data Clk EN tr, tf – – – 9.0 – – µs – tpuMPU – 100 µs Measure Pin Symbol Min Max Unit LO2 In LO2 Out fLO – 12 MHz Tx VCO ftxmax – 80 MHz MPU Interface Power–Up Delay 90% of PLL Vref to Data, Clk, EN PLL LOOP Characteristic Condition 2nd LO Frequency – “Tx VCO” Input Frequency Vin = 200 mVpp PLL I/O Pin Specifications The 2nd LO, Rx and Tx PLL’s and MPU serial interface are normally powered by the internal voltage regulator at the “PLL Vref” pin. The “PLL Vref” pin is the output of a voltage regulator which is powered from the “VCC Audio” power supply pin. Therefore, the maximum input and output levels for most PLL I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulated voltage at the “PLL Vref” pin. The ESD protection diodes on these pins are also connected to “PLL Vref”. Internal level shift buffers are provided for the pins (Data, Clk, EN, Clk Out) which connect directly to the microprocessor. The maximum input and output levels for these pins is VCC. Figure 9 shows a simplified schematic of the PLL I/O pins. I/O VCC Audio (2.0 to 5.5 V) PLL Vref (2.2 V) VCC Audio (2.0 to 5.5 V) 1.0 kΩ In Out 2.0 µA LO2 In, LO2 Out, Rx PD, Tx PD and Tx VCO Pins Data, Clk, and EN Pins Clk Out Pin Microprocessor Serial Interface The “Data”, “Clk”, and “EN” pins provide an MPU serial interface for programming the reference counters, the transmit and receive channel divider counter and various control functions. The “Data” and “Clk” pins are used to load data into the shift register. Figure 10 shows “Data” and “Clk” pin timing. Data is clocked on positive clock transitions. 16 tr tf 90% 10% Data, Clk, EN 50% Data tsuDC th 50% Clk Figure 9. PLL I/O Pin Simplified Schematics PLL Vref (2.2 V) Figure 10. Data and Clock Timing Requirement After data is loaded into the shift register, the data is latched into the appropriate latch register using the “EN” pin. This is done in two steps. First, an 8–bit address is loaded into the shift register and latched into the 8–bit address latch register. Then, up to 16–bits of data is loaded into the shift register and latched into the data latch register specified by the address that was previously loaded. Figure 11 shows the timing required on the EN pin. Latching occurs on the negative EN transition. Figure 11. Enable Timing Requirement 50% Clk tsuEC First Clock trec 50% EN 50% Last Clock 50% Previous Data Latched MOTOROLA ANALOG IC DEVICE DATA MC13109 The state of the EN pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. Figure 12 shows the address and data programming diagrams. In the data programming mode, there must not be any clock transitions when “EN” is high. The clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the “EN” high state. The convention in these figures is that latch bits to the left are loaded into the shift register first. Figure 12. Microprocessor Interface Programming Mode Diagrams Data MSB 8–Bit Address LSB Latch EN Data Address Register Programming Mode MSB 16–Bit Data LSB Latch EN Data Register Programming Mode The MPU serial interface is fully operational within 100 µs after the power supply has reached its minimum level during power–up (See Figure 13). The MPU Interface shift registers and data latches are operational in all four power saving modes; Inactive, Standby, Rx, and Active Modes. Data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. MOTOROLA ANALOG IC DEVICE DATA Figure 13. Microprocessor Serial Interface Power–Up Delay 2.0 V tpuMPU VCC Data, Clk, EN Status Out This is a digital output which indicates whether the latch registers have been reset to their power–up default values. Latch power–up default values are given in Figure 32. If there is a power glitch or ESD event which causes the latch registers to be reset to their default values, the “Status Out” pin will indicate this to the MPU so it can reload the correct information into the latch registers. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Figure 14. Status Out Operation Status Latch Register Bits Status Out Logic Level Latch bits not at power–up default value 0 Latch bits at power–up default value 1 Data Registers Figure 15 shows the data latch registers and addresses which are used to select each of these registers. Latch bits to the left (MSB) are loaded into the shift register first. The LSB bit must always be the last bit loaded into the shift register. “Don’t care” bits can be loaded into the shift register first if 8–bit bytes of data are loaded. 17 MC13109 Figure 15. Microprocessor Interface Data Latch Registers Latch Address MSB 14–Bit Tx Counter LSB 1. (00000001) LSB 2. (00000010) Tx Counter Latch MSB 14–Bit Rx Counter Rx Counter Latch U.K. Base Select U.K. Handset Select MSB 12–Bit Reference Counter LSB 3. (00000011) Reference Counter Latch ALC Disable Not Used Limiter Disable Clk Disable 2–Bit Clk Out Select 4–Bit Volume Control Stdby Mode Rx Mode Tx Mute Rx Mute SP Mute 4. (00000100) 15–Bit Mode Control Latch 5–Bit CD Threshold Control 5. (00000101) Threshold Control Latch 6. (00000110) 4–Bit Test Mode 3–Bit 1st LO Capacitor Selection 7. (00000111) 7–Bit Auxillary Latch Reference Frequency Selection The “LO2 In” and “LO2 Out” pins form a reference oscillator when connected to an external parallel–resonant crystal. The reference oscillator is also the second local oscillator for the RF Receiver. Figure 16 shows the relationship between different crystal frequencies and reference frequencies for cordless phone applications in various countries. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Figure 16. Reference Frequency and Reference Divider Values Crystal Frequency Reference Divider Value U.K. Base/ Handset Divider Reference Frequency 10.24 MHz 2048 1 5.0 kHz 10.24 MHz 1024 4 2.5 kHz 11.15 MHz 2230 1 5.0 kHz 12.00 MHz 2400 1 5.0 kHz 11.15 MHz 1784 1 6.25 kHz 11.15 MHz 446 4 6.25 kHz 11.15 MHz 446 25 1.0 kHz 18 Reference Counter Figure 17 shows how the reference frequencies for the Rx and Tx loops are generated. All countries except U.K. require that the Tx and Rx reference frequencies be identical. In this case, set “U.K. Base Select” and “U.K. Handset Select” bits to “0”. Then the fixed divider is set to “1” and the Tx and Rx reference frequencies will be equal to the crystal oscillator frequency divided by the programmable reference counter value. The U.K. is a special case which requires a different reference frequency value fo Tx and Rx. For U.K. base operation, set “U.K. Base Select” to “1”. For U.K. handset operation, set “U.K. Handset Select” to “1”. The Netherlands is also a special case since a 2.5 kHz reference frequency is used for both the Tx and Rx reference and the total divider value required is 4096 which is larger than the maximum divide value available from the 12–bit reference divider (4095). In this case, set “U.K. Base Select” to “1” and set “U.K. Handset Select” to “1”. This will give a fixed divide by 4 for both the Tx and Rx reference. Then set the reference divider to 1024 to get a total divider of 4096. Mode Control Register Power saving modes, mutes, disables, volume control, and microprocessor clock output frequency are all set by the Control Register. Operation of the Control Register is explained in Figures 18 through 25. MOTOROLA ANALOG IC DEVICE DATA MC13109 Figure 17. Reference Register Programming Mode U.K. Base Tx Reference Frequency LO2 In ÷ 25 12–b Programmable ÷4 Reference Counter ÷1 LO2 LO2 Out U.K. Handset U.K. Base Rx Reference Frequency U.K. Handset U.K. Handset Select U.K. Base Select Tx Divider Value Rx Divider Value Application 0 0 1 1 0 1 0 1 1 25 4 4 1 4 25 4 All but U.K. and Netherlands U.K. Base Set U.K. Hand Set Netherlands Base and Hand Set U.K. Handset Select U.K. Base Select MSB 12–Bit Ref Counter LSB 14–Bit Reference Counter Latch Figure 18. Control Register Bits ALC Disable Not Used Limiter Disable Clk Disable 2–Bit Clk Out Select 4–Bit Volume Control ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Figure 19. Mute and Disable Control Bit Descriptions ALC Disable 1 0 Automatic Level Control Disabled Normal Operation Limiter Disable 1 0 Limiter Disabled Normal Operation Clock Disable 1 0 MPU Clock Output Disabled Normal Operation Tx Mute 1 0 Transmit Channel Muted Normal Operation Rx Mute 1 0 Receive Channel Muted Normal Operation SP Mute 1 0 Speaker Amp Muted Normal Operation Power Saving Operating Modes When the MC13109 is used in a handset, it is important to conserve power in order to prolong battery life. There are five modes of operation; Active, Rx, Standby, Interrupt and Inactive. In Active Mode, all circuit blocks are powered. In Rx mode, all circuitry is powered down exept for those circuit MOTOROLA ANALOG IC DEVICE DATA Stdby Mode Rx Mode Rx Mute Tx Mute SP Mute sections needed to receive a transmission from the base. In the Standby and Interrupt Modes, all circuitry is powered down except for the circuitry needed to provide the clock output for the microprocessor. In Inactive Mode, all circuitry is powered down except the MPU interface. Latch memory is maintained in all modes. Figure 20 shows the control register bit values for selection of each power saving mode and Figure 21 show the circuit blocks which are powered in each of these operating mode. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 20. Power Saving Mode Selection Stdby Mode Bit Rx Mode Bit “CD Out/Hardware Interrupt” Pin Power Saving Mode 0 0 X Active 0 1 X Rx 1 0 X Standby 1 1 1 or High Impedance Inactive 1 1 0 Inactive 19 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13109 Figure 21. Circuit Blocks Powered During Power Saving Modes Active Rx Standby Inactive “PLL Vref” Regulated Voltage Circuit Blocks X X X1 X1 MPU Interface X X X X 2nd LO Oscillator X X X MPU Clock Output X X X RF Receiver X X 1st LO VCO X X Rx PLL X X Carrier Detect X X Data Amp X X Low Battery Detect X X Tx PLL X Rx Audio Path X Tx Audio Path X NOTE: 1. In Standby and Inactive Modes, “PLL Vref” remains powered but is not regulated. It will fluctuate with VCC. Inactive Mode Operation and Hardware Interrupt In some handset applications it may be desirable to power down all circuitry including the microprocessor (MPU). First put the MC13109 into the Inactive mode, which turns off the MPU Clock Output (see Figure 22), and then disable the microprocessor. In order to give the MPU adequate time to power down, the MPU Clock output remains active for a minimum of one reference counter cycle (about 200 µs) after the command is given to switch into the “Inactive” mode. An external timing circuit should be used to initiate the turn–on sequence. The “CD Out” pin has a dual function. In the Active and Rx modes it performs the carrier detect function. In the Standby and Inactive modes the carrier detect circuit is disabled and the “CD Out” pin is in a “High” state due to the external pull–up resistor. In the Inactive mode the “CD Out” pin is the input for the hardware interrupt function. When the “CD Out” pin is pulled “low” by the external timing circuit, the MC13109 swtiches from the Inactive to the Interrupt mode thereby turning on the MPU Clock Output. The MPU can then resume control of the combo IC. The “CD Out” pin must remain low until the MPU changes the operating mode from Interrupt to Standby, Active or Rx modes. Figure 22. Hardware Interrupt Operation Mode Active/Rx EN CD Out/Hardware Interrupt Inactive Interrupt MPU Initiates Inactive Mode External Timer Pulls Pin Low CD Out Low CD Turns Off Standby/Rx/Active MPU Initiates Mode Change Timer Output Disabled MPU Clock Out Delay after MPU selects Inactive Mode to when CD turns off. “MPU Clock Out” remains active for a minimum of one count of reference counter after “CD Out/Hardware Interrupt” pin goes high 20 MOTOROLA ANALOG IC DEVICE DATA MC13109 “Clk Out” Divider Programming The “Clk Out” pin is derived from the 2nd local oscillator and can be used to drive a microprocessor, thereby reducing the number of crystals required. Figure 23 shows the relationship between the crystal frequency and the clock output for different divider values. Figure 24 shows the “Clk Out” register bit values. MPU “Clk Out“ Power–Up Default Divider Value The power–up default divider value is “divide by 10”. This provides an MPU clock of about 1.0 MHz after initial power–up. The reason for choosing this relatively low clock frequency after intial power–up is that some microprocessors that operate down to a 2.0 V power supply have a maximum clock frequency fo 1.0 MHz. After initial power–up, the MPU can change the clock divider value to set the clock to the desired operating frequency. Special care has been taken in the design of the clock divider to ensure that the transition between one clock divider value and another is “smooth” (i.e., there will be no narrow clock pulses to disturb the MPU). ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ Figure 23. Clock Output Values Clock Output Divider Crystal Frequency 2 3 5 10 10.24 MHz 5.120 MHz 3.413 MHz 2.560 MHz 2.048 MHz 11.15 MHz 5.575 MHz 3.717 MHz 2.788 MHz 2.230 MHz 12.00 MHz 6.000 MHz 4.000 MHz 3.000 MHz 2.400 MHz Figure 24. Clock Output Divider Clk Out Bit #1 Clk Out Bit #0 Clk Out Divider Value 0 0 2 0 1 3 1 0 5 1 1 10 MPU “Clk Out” Radiated Noise on Circuit Board The clock line running between the MC13109 and the microprocessor has the potential to radiate noise which can cause problems in the system especially if the clock is a square wave digital signal with large high frequency harmonics. In order to minimize radiated noise, a 1.0 kΩ resistor is included on–chip in–series with the “Clk Out” output driver. A small capacitor can be connected to the “Clk Out” line on the PCB to form a single pole low pass filter. This filter will significantly reduce noise radiated from the “Clk Out” line. Volume Control The volume control can be programmed in 2.0 dB gain steps from –14 dB to +16 dB. The power–up default value is 0 dB. Figure 25. Volume Control Volume Control Bit #3 Volume Control Bit #2 Volume Control Bit #1 Volume Control Bit #0 Volume Control # Gain/Attenuation Amount 0 0 0 0 0 –14 dB 0 0 0 1 1 –12 dB 0 0 1 0 2 –10 dB 0 0 1 1 3 – 8.0 dB 0 1 0 0 4 – 6.0 dB 0 1 0 1 5 – 4.0 dB 0 1 1 0 6 – 2.0 dB 0 1 1 1 7 0 dB 1 0 0 0 8 2.0 dB 1 0 0 1 9 4.0 dB 1 0 1 0 10 6.0 dB 1 0 1 1 11 8.0 dB 1 1 0 0 12 10 dB 1 1 0 1 13 12 dB 1 1 1 0 14 14 dB 1 1 1 1 15 16 dB Gain Control Register The gain control register contains bits which control the Carrier Detect threshold. Operation of these latch bits are explained in Figures 26 and 27. MOTOROLA ANALOG IC DEVICE DATA Figure 26. Gain Control Latch Bits MSB 5–Bit CD Threshold Control LSB 21 MC13109 Carrier Detect Threshold Programming Th “CD Out” pin will give an indication to the microprocessor if a carier signal is present on the selected channel. The nominal value and tolerance of the carrier detect threshold is given in the carrier detect specification section of this document. If a different carrier detect threshold value is desired, it can be set through the MPU interface as shown in Figure 27 below. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Figure 27. Carrier Detect Threshold Control 22 CD Bit #4 CD Bit #3 CD Bit #2 CD Bit #1 CD Bit #0 CD Control # Carrier Detect Threshold 0 0 0 0 0 0 – 20 dB 0 0 0 0 1 1 –19 dB 0 0 0 1 0 2 –18 dB 0 0 0 1 1 3 –17 dB 0 0 1 0 0 4 –16 dB 0 0 1 0 1 5 –15 dB 0 0 1 1 0 6 –14 dB 0 0 1 1 1 7 –13 dB 0 1 0 0 0 8 –12 dB 0 1 0 0 1 9 –11 dB 0 1 0 1 0 10 –10 dB 0 1 0 1 1 11 – 9.0 dB 0 1 1 0 0 12 – 8.0 dB 0 1 1 0 1 13 –7.0 dB 0 1 1 1 0 14 – 6.0 dB 0 1 1 1 1 15 – 5.0 dB 1 0 0 0 0 16 – 4.0 dB 1 0 0 0 1 17 – 3.0 dB 1 0 0 1 0 18 – 2.0 dB 1 0 0 1 1 19 –1.0 dB 1 0 1 0 0 20 0 dB 1 0 1 0 1 21 1.0 dB 1 0 1 1 0 22 2.0 dB 1 0 1 1 1 23 3.0 dB 1 1 0 0 0 24 4.0 dB 1 1 0 0 1 25 5.0 dB 1 1 0 1 0 26 6.0 dB 1 1 0 1 1 27 7.0 dB 1 1 1 0 0 28 8.0 dB 1 1 1 0 1 29 9.0 dB 1 1 1 1 0 30 10 dB 1 1 1 1 1 31 11 dB MOTOROLA ANALOG IC DEVICE DATA MC13109 schematic of the 1st LO tank circuit. Figure 30 shows the latch control bit values. The internal varactor temperature coefficient is 1800 ppm/°C (CO = 8.9 pF at 25°C, Vcap control voltage = 1.2 V, Freq = 36 MHz). Customer is suggested to use a negative temperature coefficient capacitor in 1st LO tank circuit when the whole operating temperature range of –40 to +85°C is considered. Auxiliary Register The auxiliary register contains a 3–bit 1st LO Capacitor Selection latch and a 4–bit Test Mode latch. Operation of these latch bits are explained in Figures 28, 29 and 30. Figure 28. Auxiliary Register Latch Bits MSB 4–Bit Test Mode LSB MSB 3–Bit 1st LO Capacitor Selection Figure 29. 1st LO Schematic LSB First Local Oscillator Capacitor Selection for 25 Channel U.S. Operation There is a very large frequency difference between the minimum and maximum channel frequencies in the proposed 25 Channel U.S. standard. The sensitivity of the 1st LO is not large enough to accommodate this large frequency variation. Fixed capacitors can be connected across the 1st LO tank circuit to change the 1st LO sensitivity. Internal switches and capacitors are provided to enable microprocessor control over internal fixed capacitor values. Figure 29 shows the Vcap Ctrl Varactor 42 Internal Capacitor LO1 In 1st LO Varactor Cext 40 LO1 Out Lext 41 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Figure 30. 1st LO Capacitor Select for U.S. 25 Channels U.S. Handset Channels Internal Cap. Value (Excluding Varactor) Varactor Value over 0.5 to 2.2 V Range External Capacitor Value External Inductor Value 16 – 25 – 0.92 pF 10 – 6.4 pF 27 pF 0.47 µH – 16 – 25 0.92 pF 10 – 6.4 pF 33 pF 0.47 µH 1 1–6 – 2.61 pF 10 – 6.4 pF 27 pF 0.47 µH 0 2 7 – 15 – 1.82 pF 10 – 6.4 pF 27 pF 0.47 µH 1 1 3 – 1–6 8.69 pF 10 – 6.4 pF 33 pF 0.47 µH 0 0 4 – 7 – 15 7.19 pF 10 – 6.4 pF 33 pF 0.47 µH 1st LO Cap. Bit 2 1st LO Cap. Bit 1 1st LO Cap Bit 0 1st LO Cap. Select U.S. Base Channels 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 MOTOROLA ANALOG IC DEVICE DATA 23 MC13109 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 31. Test Mode Description Counter Under Test or Test Mode Option “Tx VCO” Input Signal “Clk Out” Output Expected >200 mVpp – TM # TM 3 TM 2 TM 1 TM 0 0 0 0 0 0 Normal Operation 1 0 0 0 1 Rx Counter, upper 6 0 to 2.2 V Input Frequency/64 2 0 0 1 0 Rx Counter, lower 8 0 to 2.2 V See Note Below 3 0 0 1 1 Rx Prescaler 0 to 2.2 V Input Frequency/4 4 0 1 0 0 Tx Counter, upper 6 0 to 2.2 V Input Frequency/64 5 0 1 0 1 Tx Counter, lower 8 0 to 2.2 V See Note Below 6 0 1 1 0 Tx Prescaler 7 0 1 1 1 Reference Counter 0 to 2.2 V Input Frequency/Reference Counter Value 8 1 0 0 0 Divide by 4, 25 0 to 2.2 V Input Frequency/100 9 1 0 0 1 AGC Gain = 10 Option N/A – 1 0 1 0 AGC Gain = 25 Option N/A – 10 NOTE: >200 mVpp Input Frequency/4 To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3 of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60). Test Modes Test Mode Control latch bits enable independent testing of internal counters and set AGC Gain Options. In test mode, the “Tx VCO” input pin is multiplexed to the input of the counter under test and the output of the counter under test is multiplexed to the “Clk Out” output pin so that each counter can be individually tested. Make sure test mode bits are set to “0” for normal operation. Test mode operation is described in Figure 31. During normal operation and when testing the Tx Prescaler, the “Tx VCO” input can be a minimum of 200 mVpp at 80 MHz and should be ac coupled. For other test modes, input signals should be standard logic levels of 0 to 2.2 V and a maximum frequency of 16 MHz. Power–Up Defaults for Control and Counter Registers When the IC is first powered up, all latch registers are initialized to a defined state. The MC13109 is initially placed in the Rx mode with all mutes active and nothing disabled. The reference counter is set to generate a 5.0 kHz reference frequency from a 10.24 MHz crystal. The MPU clock output divider is set to 10 to give the minimum clock output frequency. The Tx and Rx latch registers are set for USA Channel Frequency #21. Figure 32 shows the initial power–up states for all latch registers. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ Figure 32. Latch Register Power–Up Defaults MSB LSB R i Register C Count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tx 9966 – – 1 0 0 1 1 0 1 1 1 0 1 1 1 0 Rx 7215 – – 0 1 1 1 0 0 0 0 1 0 1 1 1 1 Ref 2048 – – 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Mode N/A – 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 Gain N/A – – – – – – – – – – – 1 0 1 0 0 TM N/A – – – – – – – – – 0 0 0 0 0 0 0 24 MOTOROLA ANALOG IC DEVICE DATA MC13109 Figure 34. ICC versus VCC at Receive Mode Figure 33. ICC versus VCC at Active Mode 8.0 I CC , SUPPLY CURRENT (mA) I CC , SUPPLY CURRENT (mA) 8.0 6.0 4.0 2.0 0 2.5 3.0 3.5 4.0 4.5 6.0 4.0 2.0 0 2.5 5.0 3.0 Figure 35. ICC versus VCC at Standby Mode 4.5 5.0 Figure 36. ICC versus VCC at Inactive Mode I CC , SUPPLY CURRENT (µ A) I CC , SUPPLY CURRENT (mA) 4.0 80 1.0 0.8 0.6 0.4 0.2 0 2.5 3.5 VCC, SUPPLY VOLTAGE (V) VCC, SUPPLY VOLTAGE (V) 3.0 3.5 4.0 4.5 60 40 20 0 2.5 5.0 3.0 VCC, SUPPLY VOLTAGE (V) 3.5 4.0 4.5 5.0 VCC, SUPPLY VOLTAGE (V) Figure 37. RFin versus AFout, N+D, N, AMR Figure 38. Recovered Audio/THD versus fDEV 3.0 0.30 10 R22 = 12 kΩ –20 –30 AMR N+D –50 2.0 0.20 Recovered Audio 0.15 1.5 0.10 1.0 THD 0.5 0.05 N –60 –120 –100 –80 –60 –40 RFin, RF INPUT (dBm) MOTOROLA ANALOG IC DEVICE DATA –20 0 0 0 2.0 4.0 6.0 8.0 10 0 fDEV, DEVIATION, (kHz) 25 THD (%) –10 –40 2.5 0.25 AFout RECOVERED AUDIO (V) RELATIVE OUTPUT (dB) 0 MC13109 Figure 40. First Mixer Third Order Intercept Performance Figure 39. RSSI Output versus RFin 1.4 0 1.2 MIXER OUTPUT (dBm) RSSI OUTPUT (V) –20 1.0 0.8 0.6 0.4 –60 –80 0.2 0 –120 –40 –100 –80 –60 –40 –20 0 –100 –120 –100 RFin, RF INPUT (dBm) –80 –60 –40 –20 0 RFin, RF INPUT (dBm) APPENDIX A – MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME This measurement definition is based on EIA/CCITT recommendations. Compressor Attack Time For a 12 dB step up at the input, attack time is defined as the time for the output to settle to 1.5X of the final steady state value. Compressor Decay Time For a 12 dB step down at the input, decay time is defined as the time for the input to settle to 0.75X of the final steady state value. Expander Attack For a 6.0 dB step up at the input, attack time is defined as the time for the output to settle to 0.57X of the final steady state value. Expander Decay For a 6.0 dB step down at the input, decay time is defined as the time for the output to settle to 1.5X of the final steady state value. 6.0 dB Input 12 dB 0 mV Input Attack Time Decay Time 0 mV Attack Time Decay Time 0.57X Final Value 1.5X Final Value 1.5X Final Value Output Output 0 mV 0.75X Final Value 0 mV 26 MOTOROLA ANALOG IC DEVICE DATA MC13109 OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848B–04 (QFP–52) ISSUE C L B B 39 27 S D V S 0.20 (0.008) 0.20 (0.008) M L –A–, –B–, –D– DETAIL A F M C A–B S S B H A–B –B– –A– 0.05 (0.002) A–B DETAIL A D 26 40 J N BASE METAL 14 52 1 D 13 0.02 (0.008) –D– B 0.20 (0.008) M H A–B S D S S D S V M C A–B DETAIL C M_ C E –H– DATUM PLANE 0.10 (0.004) H –C– M_ G C A–B S D S SECTION B–B 0.05 (0.002) A–B 0.20 (0.008) M U_ R Q_ K T W X DETAIL C SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.10 2.45 0.22 0.38 2.00 2.10 0.22 0.33 0.65 BSC ––– 0.25 0.13 0.23 0.65 0.95 7.80 REF 5_ 10_ 0.13 0.17 0_ 7_ 0.13 0.30 12.95 13.45 0.13 ––– 0_ ––– 12.95 13.45 0.35 0.45 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.009 0.015 0.079 0.083 0.009 0.013 0.026 BSC ––– 0.010 0.005 0.009 0.026 0.037 0.307 REF 5_ 10_ 0.005 0.007 0_ 7_ 0.005 0.012 0.510 0.530 0.005 ––– 0_ ––– 0.510 0.530 0.014 0.018 0.063 REF Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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MOTOROLA ANALOG IC DEVICE DATA 27 MC13109 OUTLINE DIMENSIONS 4 FTA SUFFIX PLASTIC PACKAGE CASE 932–02 (Thin QFP) ISSUE D 0 . 0 0 8 ) X 0 . 2 9 0 0Z ( D A A 4 3 A P I L 7 3 T T NOTES: T1 DIMENSIONING – U AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. Y 3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL A CAUSE E THE D DIMENSION TO EXCEED NOT 0.350 (0.014). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER IS OPTIONAL. B 1 8 1 – E A 6 – – U – V B B A 1 1 2 2 1 3 2 E 1 4 – S 5 V Z – 1 – T – , – U T A S 4 D X 0 . 2 0 0Z ( 0 . 0 G – A B – – A C – A ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ B A S E 0 . 0 8 0 8 ) 0 A C ( 0 T . D M E T A O P & B R J C – M_ L T N E MILLIMETERS INCHES DIM MIN MAX MIN MAX A 7.000 BSC 0.276 BSC A1 3.500 BSC 0.138 BSC B 7.000 BSC 0.276 BSC – B1 , 3.500 BSC – 0.138ZBSC C 1.400 1.600 0.055 0.063 I D L0.170 0.270 Y0.007 0.011 E 1.350 1.450 0.053 0.057 F 0.170 0.230 0.007 0.009 – G U 0.500 BASIC 0.020 BASIC H 0.050 0.150 0.002 0.006 J 0.090 0.200 0.004 0.008 K 0.500 0.700 0.020 0.028 M 12 _REF 12 _REF 0 N 0 0.0903 0.160 ) A C 0.004 0.006 P 0.250 BASIC 0.010 BASIC Q 1_ 5_ 1_ 5_ R 0.150 0.250 0.006 0.010 S 9.000 BSC 0.354 BSC S1 4.500 BSC 0.177 BSC V 9.000 BSC 0.354 BSC V1 4.500 BSC 0.177 BSC W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF O T G A 0 . T U O G 2 M E 5 P 0 L A ( N 0 E F D 0 . S 0 M E 8A T0C C S– S (U T I 0 . O 0 N 0 3 ) HA Z E D –W E T A E A Q_ I K L A D X H o w t o r e a c h USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com 28 ◊ u s : JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA ANALOG IC DEVICE DATA *MC13109/D* MC13109/D E . 0 1