Order this document by MC13109A/D MC13109A Universal Cordless Telephone Subsystem IC The MC13109A integrates several of the functions required for a cordless telephone into a single integrated circuit. This significantly reduces component count, board space requirements, and external adjustments. It is designed for use in both the handset and the base. • Dual Conversion FM Receiver – Complete Dual Conversion Receiver – Antenna Input to Audio Output 80 MHz Maximum Carrier Frequency – RSSI Output – Carrier Detect Output with Programmable Threshold – Comparator for Data Recovery – Operates with Either a Quad Coil or Ceramic Discriminator • • • • UNIVERSAL CT–0 SUBSYSTEM INTEGRATED CIRCUIT 52 Compander – Expandor Includes Mute, Digital Volume Control and Speaker Driver – Compressor Includes Mute, ALC and Limiter 1 FB SUFFIX PLASTIC PACKAGE CASE 848B (QFP–52) Dual Universal Programmable PLL – Supports New 25 Channel U.S. Standard with No External Switches – Universal Design for Domestic and Foreign CT–0 Standards – Digitally Controlled Via a Serial Interface Port – Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit Programmable Counter and 2nd LO with 12–Bit Counter – Transmit Section Contains Phase Detector and 14–Bit Counter – MPU Clock Output Eliminates Need for MPU Crystal 48 1 FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP–48) Supply Voltage Monitor – Externally Adjustable Trip Point 2.0 to 5.5 V Operation with One–Third the Power Consumption of Competing Devices ORDERING INFORMATION Device Tested Operating Temperature Range MC13109AFB MC13109AFTA TA = –20 to 85°C Package QFP–52 LQFP–48 Simplified Block Diagram Rx In 1st Mixer 2nd Mixer 1st LO PLL 2nd LO PLL Limiting IF Amplifier RSSI Detector Mute Expander Rx Out Carrier Detect Tx In Data Out Mute Compressor µP Serial Interface Tx Phase Detector Low Battery Detect SPI Tx Out Tx VCO Low Battery Indicator This device contains 6,609 active transistors. Motorola, Inc. 1999 MOTOROLA RF/IF DEVICE DATA Rev 1 1 MC13109A Figure 1. MC13109AFB Test Circuit Rx_Audio Ext_C_In R30 49.9k R29 49.9k VCC/2 R31 100k C41 C42 0.47 5.0nF µF C43 0.1µF C5 0.1µF R2 32.4k C6 0.022µF C7 15pF 7 8 EN Clk 11 Clk Out 12 N/A 13 C8 18pF L3 0.22µH C9 33pF C10 68pF R5 22.1k 14 Q1 MPS5179 Data_5.0 V VCC C13 0.01 µF R6 1.0k Compressor 1st LO VCO 36 Half Supply Reference 2nd LO 1st LO 15 C15 10pF RSSI Expander VB E + – Spkr Cap Mute Spkr Amp Rx Mute Data Amp Pre– Amp + Vol Ctrl 28 12 14 LS09 EN_5.0V 7 Open DA_In Data_5.0V 10 9 14 EN_5.0V DA U1 Out DB 8 R16 49.9k R9 1.0k VCC Gnd 7 LS09 Clk_5.0V VCCE 5 14 C32 0.1µF VCC RF C29 10µF L2 Q Coil C28 0.1µF R22 12k TOKO A7MES–12597Z R20 49.9k R21 8.2k Det_Out R19 49.9k C26 0.01µF C25 1.0µF Audio_In_In C21 0.033µF C22 0.1µF R17 5.62k C20 0.1µF C18 1.0µF C23 0.001µF R18 20k E_Out R11 1.0k DA R10 1.0k Clk_5.0V R23 10.2 VCC C30 0.1µF 455k In Open U1 Out 6 DB VCC Gnd 7 LS09 VCCA C19 10µF C33 0.1µF C31 0.1µF DA_Fil Gnd VCC 4 Lim In Ext_IF R23 1.5k C27 0.1µF Pre_Amp DB R24 10 N/A Open 13 CF2 27 VB 17 18 19 20 21 22 23 24 25 26 BD DA SA SA E VCC DA Pre– Rx Det RSSI Out Out Out In Out Audio In Amp Audio Out Out In C16 R13 510 R12 3.9k pF 100k R15 C24 49.9k 510pF VCCD Out 11 C34 Gnd RF 16 U1 Out 3 1.0µF 31 Lim C1 Lim C2 30 – C12 33pF DA VB Mix2 Out 29 Gnd Mix1 Out 34 32 Carrier Detect In 2 Mix2 In 33 330 1 Mix1 In1 35 2nd Mix Ref Low Battery Detect CD Status Out Out/ Hardware Interrupt R7 22.1k C11 47pF ÷1 ÷4 ÷25 37 1st LO PLL Vref 9 10 ALC Out Mix1 In2 38 1st Mix 12b Prog Ref Ctr Limiter Data C14 1.0µF R8 100k R4 100k 1N5140 Tx VCO C48 1.0µF Ext Tx_VCO R3 32.4k Ecap VCCA 3 39 In 2 C36 0.01µF IF Amp/ Limiter R1 1.5k Spl Amp + – Tx Mute 1 50 R27 49.9k Detector C3 0.047µF Mix1_In VCC C40 1.0µF Bandgap Reference C4 0.01µF + – 2nd LO 14b Prog Rx Ctr C44 10µF C35 0.01µF Open LO1 VB 2.2V Voltage Regulator LO2 Out 2 PLL Vref 3 Rx PD 4 Gnd PLL 5 Tx PD 6 R x Phase Detect C2 4.3pF VCCA VB µ P Serial Interface C45 0.1µF R33 3.0k 1 T x Phase Detect R34 1.5k 10.24 MHz 14b Prog Tx Ctr LO2 In XL1 R35 32.4k 2nd LO 10.240 C1 9–35pF C46 Open C38 5.0nF Spl Tx Amp Lim C Amp Tx Gnd Vcap LO1 LO1 In Out Cap C In Out In Audio Ctrl Out In N/A Ref Out 52 51 50 49 48 47 46 45 44 43 42 41 40 Prog Clk Ctr 0.0047 µF C30 1.0µF CF2 455 MHz Ext_Ref L1 C47 MIC_ 1.0µF Amp R28 Out 49.9k CF1 10.7 MHz R32 100k R36 22.1k Tx_In Open VCCE Ext_SA_In 1 2 DA DB U1 Out 3 Gnd V 7 14 CC LS09 R14 130 C17 47µF Exp_IF SA_Out 5.0V 2 MOTOROLA RF/IF DEVICE DATA MC13109A Figure 2. MC13109AFTA Test Circuit Rx_Audio Tx_In Ext_C_In Open VCCE C47 1.0µF R2 32.4k R1 1.5k 3 5 Spl Amp ÷1 C7 15pF C14 1.0 µF C8 18pF R6 1.0k C12 33pF µ P Serial Interface 9 10 R8 100k Clk Out 11 13 C10 68pF CD Out/ Hardware Interrupt C13 0.01 µF Q1 MPS5179 14 13 DA 12 DB BD Out DA Out R12 100k Data_ 5.0 V EN_5.0V Data_5.0V 10 DA RSSI Open R9 1.0k R11 1.0k R10 1.0k Gnd RF SA Out 17 SA In Pre– Amp + Vol Ctrl 18 19 E VCC Out Audio C16 510pF DA In 21 Pre– Amp Out 25 22 23 24 Rx Det RSSI Audio Out In C24 510pF R15 49.9k R19 49.9k C17 47µF 26 – VB 20 Lim C1 C32 0.1µF Lim C2 C31 0.1µF 27 Data Amp 3 Out C33 0.1µF Ext_IF R23 1.5k R24 10 455k In R23 10.2 VCC RF C30 0.1µF Q Coil C27 0.1µF C29 10µF VCC Det_Out R21 8.2k C26 0.01µF R20 49.9k R22 12k L2 TOKO A7MES–12597Z C25 1.0µF Pre_Amp C28 0.1µF Audio_In_In DA_Fil Clk_5.0 V 9 DB 14 Gnd 7 VCC LS09 1 In 2 Gnd 28 Rx Mute SA_Out Out 8 Mix2 Out Lim In VCCE Open U1 3 Out Mix2 In 29 R14 130 Open 14 V Gnd 7 CC LS09 16 VCCD U1 Out 11 31 In 2 CF2 E + – Spkr Cap Mute Spkr Amp 15 VCC 5.0V 2nd Mix Carrier Detect Expander R13 3.9k C15 10pF 32 2nd LO VB 12 R7 22.1k Half Supply Reference Ref Low Battery Detect Clk VCC L3 0.22µH C9 33pF Data EN 1 VCC 330 1st LO 2.2V Voltage Regulator Ext 33 Mix1 Out C34 1.0µF VB 30 14b Prog Tx Ctr R4 100k 1st LO Compressor ÷4 ÷25 Mix1 In1 50 C36 0.01µF Mix1 In2 C35 0.01µF 34 PLL Vref Prog Clk Ctr 1N5140 C11 47pF 7 8 C6 0.022µF R5 22.1k E Cap Tx C48 1.0µF VCO 35 1st Mix Limiter T x Phase Detect VCCA Tx_VCO Tx Mute ALC 6 R3 32.4k + – + – 12b Prog Ref Ctr 4 Tx PD VB 2nd LO 36 VB VCCA R16 49.9k C18 1.0µF C19 10µF DA_In C22 0.1µF R17 5.62k C21 0.033µF R18 20k C23 0.001µF C20 0.1µF EN_5.0V 4 DA U1 Out 6 5 DB 14 Gnd VCC LS09 7 Clk_5.0V 1 U1 DA 2 E_Out Out 3 DB 14 V Gnd 7 CC LS09 MOTOROLA RF/IF DEVICE DATA CF1 10.7 MHz 2 Gnd PLL C5 0.1µF Tx Gnd Vcap LO1 LO1 In Audio In Ctrl Out 41 40 39 38 37 Amp Out C In 43 42 1 Rx PD C4 0.01µF 44 IF Amp/ Limiter C44 10µF PLL Vref C Cap 45 Mix1_In Detector LO2 Out Lim Out 46 Bandgap Reference C2 4.3pF 10.24 MHz Spl Amp In C41 0.47 µF LO1 R27 49.9k C40 1.0µF 14b Prog R x Ctr R33 3.0k C3 0.047µF LO2 In XL1 2nd LO 10.240 C1 9–35pF Tx Ref Out 48 47 R x Phase Detect C45 0.1µF Open R30 49.9k Open L1 CF2 455 MHz C43 0.1µF R28 49.9k C38 5.0nF VCCA C42 5.0nF R35 32.4k R34 1.5k C30 1.0µF R29 49.9k R31 100k C46 0.0047 µF R36 22.1k MIC_ Amp Out VCC/2 Ext_Ref 1st LO VCO R32 100k Ext_SA_In Exp_IF 3 MC13109A MAXIMUM RATINGS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ Symbol Value Unit Power Supply Voltage Rating VCC – 0.5 to + 5.5 Vdc Junction Temperature TJ – 65 to +150 °C NOTES: 1. Devices should not be operated at or outside these limits. The “Recommended Operating Conditions” table provides for actual device operation. 2. ESD data available upon request. 3. Meets Human Body Model (HBM) ≤2000V and Machine Model (MM) ≤200V. RECOMMENDED OPERATING CONDITIONS Min Typ Max Unit VCC Characteristic 2.0 – 5.5 Vdc Operating Ambient Temperature –20 – 85 °C NOTE: All limits are not necessarily functional concurrently. ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C, RF In = 46.61 MHz, fDEV = ± 3.0 kHz, fmod = 1.0 kHz; Test Circuit Figure 1.) Characteristic POWER SUPPLY Static Current Active Mode (VCC = 2.6 V) Active Mode (VCC = 3.6 V) Receive Mode (VCC = 2.6 V) Receive Mode (VCC = 3.6 V) Standby Mode (VCC = 2.6 V) Standby Mode (VCC = 3.6 V) Inactive Mode (VCC = 2.6 V) Inactive Mode (VCC = 3.6 V) 4 Min Typ Max Unit – – – – – – – – 6.1 6.5 3.9 4.3 320 550 40 54 12 – 7.0 – 600 – 80 – mA mA mA mA µA µA µA µA MOTOROLA RF/IF DEVICE DATA MC13109A ELECTRICAL CHARACTERISTICS (continued) FM Receiver The FM receivers can be used with either a quad coil or a ceramic resonator. The FM receiver and 1st LO have been designed to work for all country channels, including 25 channel U.S., without the need for any external switching circuitry (see Figure 25.) (Test Conditions: VCC = 2.6 V, TA = 25°C, fO = 46.61 MHz, fDEV = ± 3.0 kHz, fmod = 1.0 kHz.) Characteristic Condition Input Pin Measure Pin Symbol Min Typ Max Unit Sensitivity (Input for 12 dB SINAD) Matched Impedance Differential Input Mix1 In1/2 Det Out VSIN – 0.7 – µVrms 1st Mixer Voltage Conversion Gain Vin = 1.0 mVrms, with CF1 as Load Mix1 In1/2 Mix1 Out MXgain1 – 10 – dB 2nd Mixer Voltage Conversion Gain Vin = 3.0 mVrms, with CF2 as Load Mix2 In Mix2 Out MXgain2 – 20 – dB 1st Mixer Input Impedance – – Mix1 In1 Mix1 In2 RP1 CP1 – 0.88 2.5 – kΩ pF 2nd Mixer Input Impedance – – Mix2 In RP2 CP2 – 3.0 2.7 – kΩ pF 1st Mixer Output Impedance – – Mix1 Out RP1 Out CP1 Out – 390 1.8 – Ω pF 2nd Mixer Output Impedance – – Mix2 Out RP2 Out CP2 Out – 1.5 12 – kΩ pF 1st and 2nd Mixer Voltage Gain Total Vin = 1.0 mVrms, with CF1 and CF2 as Load Mix1 In1/2 Mix2 Out MXgainT 24 27 – dB IF – 3.0 dB Limiting Sensitivity fin = 455 kHz Lim In Det Out IF Sens – 55 100 µVrms Total Harmonic Distortion (CCITT Filter) With RC = 8.2 kΩ/ 0.01 µF Filter at Det Out Mix1 In1/2 Det Out THD – 1.0 3.0 % Recovered Audio With RC = 8.2 kΩ/ 0.01 µF Filter at Det Out Mix1 In1/2 Det Out AFO 80 100 154 mVrms – Lim In Det Out BW – 20 – kHz Signal to Noise Ratio Vin = 10 mVrms, RC = 8.2 kΩ/0.01 µF Mix1 In1/2 Det Out SN – 50 – dB AM Rejection Ratio 30% AM, Vin = 10 mVrms, RC = 8.2 kΩ/0.001 µF Mix1 In1/2 Det Out AMR 30 40 – dB First Mixer 3rd Order Intercept (Input Referred) Matched Impedance Input Mix1 In1/2 Mix1 Out TOImix1 – –10 – dBm Second Mixer 3rd Order Intercept (Input Referred) Matched Impedance Input Mix2 In Mix2 Out TOImix2 – – 27 – dBm – Det Out ZO – 870 – Ω Demodulator Bandwidth Detector Output Impedance – MOTOROLA RF/IF DEVICE DATA 5 MC13109A ELECTRICAL CHARACTERISTICS (continued) RSSI/Carrier Detect Connect 0.01 µF to Gnd from “RSSI” output pin to form the carrier detect filter. “CD Out” is an open collector output which requires an external 100 kΩ pull–up resistor to VCC. The carrier detect threshold is programmable through the MPU interface. (RL = 100 kΩ, VCC = 2.6 V, TA = 25°C.) Condition Input Pin Measure Pin Symbol Min Typ Max Unit – Mix1 In RSSI RSSI – 65 – dB CD Threshold Adjust = (10100) Mix1 In CD Out VT – 11 – mVrms – Mix1 In CD Out Hys – 1.5 – dB Output High Voltage Vin = 0 µVrms, RL = 100 kΩ, CD = (10100) Mix1 In CD Out VOH – 2.6 – V Output Low Voltage Vin = 100 µVrms, RL = 100 kΩ, CD = (10100) Mix1 In CD Out VOL – 0.01 0.4 V Carrier Sense Threshold Adjustment Range Programmable through MPU Interface – – VTrange – 20 – 11 dB Carrier Sense Threshold – Number of Steps Programmable through MPU Interface – – VTn – 32 – – Characteristic RSSI Output Current Dynamic Range Carrier Sense Threshold Hysteresis Data Amp Comparator Inverting hysteresis comparator. Open collector output with internal 100 kΩ pull–up resistor. A band pass filter is connected between the “Det Out” pin and the “DA In” pin with component values as shown in the attached block diagram. The “DA In” input signal is ac coupled. (VCC = 2.6 V, TA = 25°C) Condition Input Pin Measure Pin Symbol Min Typ Max Unit Hysteresis – DA In DA Out Hys 30 40 50 mV Threshold Voltage – DA In DA Out VT VCC – 0.9 VCC – 0.7 VCC – 0.5 V Input Impedance – – DA In ZI – 12 – kΩ Output Impedance – – DA Out ZO – 104 – kΩ Characteristic Output High Voltage Vin = VCC – 1.0 V, IOH = 0 mA DA In DA Out VOH VCC – 0.1 2.6 – V Output Low Voltage Vin = VCC – 0.4 V, IOL = 0 mA DA In DA Out VOL – 0.04 0.4 V 6 MOTOROLA RF/IF DEVICE DATA MC13109A ELECTRICAL CHARACTERISTICS (continued) Pre–Amplifier/Expander/Rx Mute/Volume Control The Pre–Amplifier is an inverting rail–to–rail output swing operational amplifier with the non–inverting input terminal connected to the internal VB half supply reference. External resistors and capacitors can be connected to set the gain and frequency response. The expander analog ground is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. The volume control can be adjusted through the MPU interface. The “Rx Audio In” input signal is ac coupled. (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, Set External Pre–Amplifier R’s for Gain of 1, Volume Control = (0111).) Characteristic Condition Input Pin Measure Pin Symbol Min Typ Max Unit Pre–Amp Open Loop Gain – Rx Audio In Pre–Amp AVOL – 60 – dB Pre–Amp Gain Bandwidth – Rx Audio In Pre–Amp GBW – 100 – kHz Pre–Amp Maximum Output Swing RL = 10 kΩ Rx Audio In Pre–Amp VOmax – VCC – 0.3 – Vpp Expander 0 dB Gain Level Vin = –10 dBV Rx Audio In E Out G –3.0 –0.3 3.0 dB Expander Gain Tracking Vin = –20 dBV, Output Relative to G Vin = –30 dBV, Output Relative to G Rx Audio In E Out Gt –21 –19.84 –19 dB –42 –40.12 –37 Total Harmonic Distortion Vin = –10 dBV Rx Audio In E Out THD – 0.2 – % Maximum Output Voltage Increase input voltage until output voltage THD = 5%, then measure output voltage. RL = 10 kΩ Rx Audio In E Out VOmax – –5.0 – dBV Attack Time Ecap = 1.0 µF, Rfilt = 20 kΩ (See Appendix B) Rx Audio In E Out ta – 3.0 – ms Release Time Ecap = 1.0 µF, Rfilt = 20 kΩ (See Appendix B) Rx Audio In E Out tr – 13.5 – ms Compressor to Expander Crosstalk V (Rx Audio In) = 0 Vrms, Vin = –10 dBV C In E Out CT – –76 – dB Rx Mute Vin = –10 dBV No popping detectable during Rx Mute transitions Rx Audio In E Out Me – –65 – dB Volume Control Range Programmable through MPU Interface – – VCrange –14 – 16 dB Volume Control Steps Programmable through MPU Interface – – VCn – 16 – – MOTOROLA RF/IF DEVICE DATA 7 MC13109A ELECTRICAL CHARACTERISTICS (continued) Speaker Amplifier/SP Mute The Speaker Amplifier is an inverting rail–to–rail operational amplifier. The non–inverting input terminal is connected to the internal VB half supply reference. External resistors and capacitors are used to set the gain and frequency response. The “SA In” input is ac coupled. (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Characteristic Maximum Output Swing SP Mute Input Pin Measure Pin Symbol Min Typ Max Unit VCC = 2.3 V, RL = 130 Ω VCC = 2.3 V, RL = 600 Ω VCC = 3.4 3 4 V, V RL = 600 Ω SA In SA Out VOmax – 0.8 – Vpp – 2.0 – – 3.0 30 – Vin = –20 dBV RL = 130 Ω No popping detectable during SP Mute transitions SA In – –67 – Condition Mic Amplifier The Mic Amplifier is an inverting rail–to–rail output operational amplifier with the non–inverting input terminal connected to the internal VB half supply reference. External SA Out Msp dB resistors and capacitors are connected to set the gain and frequency response. The “Tx In” input is ac coupled. (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External Resistors Set for Gain of 1.) Condition Input Pin Measure Pin Symbol Min Typ Max Unit Open Loop Gain – Tx In Amp Out AVOL – 60 – dB Gain Bandwidth – Tx In Amp Out GBW – 100 – kHz Tx In Amp Out VOmax – VCC – 0.3 – Vpp Characteristic Maximum Output Swing 8 RL = 10 kΩ MOTOROLA RF/IF DEVICE DATA MC13109A ELECTRICAL CHARACTERISTICS (continued) Compressor/ALC/Tx Mute/Limiter The compressor analog gound is set to the half supply reference so the input and output swing capability will increase as the supply voltage increases. The “C In” input is ac coupled. The ALC (Automatic Level Control) provides a soft limit to the output signal swing as the input voltage increases slowly (i.e., a sine wave is maintained). The Limiter circuit limits rapidly changing signal levels by clipping the signal peaks. The ALC and/or Limiter can be disabled through the MPU serial interface. (Test Conditions: VCC = 2.6 V, fin = 1.0 kHz, TA = 25°C.) Characteristic Condition Input Pin Measure Pin Symbol Min Typ Max Unit Compressor 0 dB Gain Level Vin = –10 dBV, ALC disabled, Limiter disabled C In Lim Out G –3.0 –0.06 3.0 dB Compressor Gain Tracking Vin = –30 dBV, Output Relative to G C In Lim Out Gt –11 –10.12 –9.0 dB –23 –20.16 –17 Vin = –50 dBV, Output Relative to G Maximum Compressor Gain Vin –70 dBV C In Lim Out AVmax – 29 – dB Total Harmonic Distortion Vin –10 dBV, ALC disabled, Limiter disabled C In Lim Out THD – 0.5 – % C In Lim Out Zin – 16 – kΩ Input Impedance – Attack Time Ccap = 1.0 µF, Rfilt = 20 kΩ (see Appendix B) C In Lim Out ta – 3.0 – ms Release Time Ccap = 1.0 µF, Rfilt = 20 kΩ (see Appendix B) C In Lim Out tr – 13.5 – ms Expander to Compressor Crosstalk V (C In) = 0 Vrms, Vin = –10 dBV Rx Audio In Lim Out CT – –43.6 – dB Tx Data Mute Vin = –10 dBV, ALC disabled No popping detectable during Rx Mute transitions C In Lim Out Me – –76 – dB – C In Lim Out DR – –18 to 2.5 – dBV C In Lim Out ALCout – –16 – dBV Vlim – – –11.4 0.8 – – Vpp ALC Dynamic Range ALC Output Level Limiter Output Level Vin = –18 dBV Vin = –2.5 dBV ALC disabled MOTOROLA RF/IF DEVICE DATA C In Tx Out 9 MC13109A ELECTRICAL CHARACTERISTICS (continued) Splatter Amplifier The Splatter Amplifier is an inverting rail–to–rail output operational amplifier with the non–inverting input terminal connected to the internal VB half supply reference. External resistors and capacitors can be connected to set the gain and frequency response. The “Spl Amp In” input is ac coupled. (Test Conditions: VCC = 2.6 V, TA = 25°C, fin = 1.0 kHz, External resistors Set for Gain of 1.) Characteristic Condition Input Pin Measure Pin Symbol Min Typ Max Unit Open Loop Gain – Spl Amp In Tx Out AVOL – 60 – dB Gain Bandwidth – Spl Amp In Tx Out GBW – 100 – kHz Spl Amp In Tx Out VOmax – VCC – 0.3 – Vpp Maximum Output Swing RL = 10 kΩ Tx Audio Path Recommendation The recommended configuration for the Tx Audio path includes setting the Microphone Amplifier gain to 16 dB using the external gain setting resistors and setting the Splatter Amplifier gain to 9.0 dB using the external gain setting resistors. PLL Voltage Regulator The PLL supply voltage is regulated to a nominal of 2.2 V. The “VCC Audio” pin is the supply voltage for the internal voltage regulator. The “PLL Vref ” pin is the 2.2 V regulated output voltage. Two capacitors with 10 µF and 0.01 µF values must be connected to the “PLL Vref ” pin to filter and stabilize this regulated voltage. The voltage regulator provides power for the 2nd LO, Rx and Tx PLL’s, and MPU Interface. The voltage regulator can also be used to provide a regulated supply voltage for external IC’s. Rx and Tx PLL loop performance are independent of the power supply voltage when the voltage regulator is used. The voltage regulator requires about 200 mV of “headroom”. When the power supply decreases to within about 200 mV of the output voltage, the regulator will go out of regulation but the output voltage will not turn off. Instead, the output voltage will maintain about a 200 mV delta to the power supply voltage as the power supply voltage continues to decrease. The “PLL Vref” pin can be connected to “VCC Audio” by the external wiring if voltage higher than 2.2 V is required. But it should not be connected to other supply except “VCC Audio”. The voltage regulator is “on” in the Active and Rx modes. In the Standby and Inactive modes, the voltage regulator is turned off to reduce current drain and the “PLL Vref” pin is internally connected to “VCC Audio” (i.e., the supply voltage is maintained but is now unregulated). (Test Conditions: VCC = 2.6 V, TA = 25°C.) Characteristic Condition Input Pin Measure Pin Symbol Min Typ Max Unit – VCC PLL Vout – 2.2 – V Output Voltge Level VCC = 2.6 V, OL= 0 mA Line Regulation IL = 0 mA, VCC = 2.6 to 5.5 V VCC VCC PLL Regline – 3.66 40 mV Load Regulation VCC = 2.6 V, IL = 0 to 1.0 mA VCC VCC PLL Regload –40 –2.28 – mV 10 MOTOROLA RF/IF DEVICE DATA MC13109A ELECTRICAL CHARACTERISTICS (continued) Low Battery Detect An external resistor divider is connected to the “Ref” input pin to set the threshold for the low battery detect. The voltage at the “Ref” input pin is compared to an internal 1.23 V Bandgap reference voltage. The “BD Out” pin is open collector and requires and external pull–up resistor to VCC. (Test Conditions: VCC = 2.6 V, TA = 25°C.) Characteristic Average Threshold Voltage Hysteresis Input Pin Measure Pin Take average of rising and falling threshold Ref – Condition Symbol Min Typ Max Unit Ref/ BD Out Threshold – 1.23 – V Ref Ref/ BD Out Hys – 2.0 – mV – Ref Iin – 12.33 50 nA Input Current Vin = 1.6 V Output High Voltage Vref = 1.6, RL = 3.9 kΩ Ref BD Out VOH VCC – 0.1 2.59 – V Output Low Voltage Vref = 0.9, RL = 3.9 kΩ Ref BD Out VOL – 0.6 0.4 V Figure 3. Data Amp Operation Data Amp Data Signal Hysteresis Data Amp Output MOTOROLA RF/IF DEVICE DATA 11 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13109A PIN FUNCTION DESCRIPTION 48–TQFP Pin 52–QFP Pin Symbol Type Description 1 2 1 2 LO2 In LO2 Out – These pins form the PLL reference oscillator when connected to an external parallel–resonant crystal (10.24 MHz typical). The reference oscillator is also the second Local Oscillator (LO2) for the RF receiver. 3 3 PLL Vref Supply Voltage Regulator output pin. The internal voltage regulator provides a stable power supply voltage for the Rx and Tx PLL’s and can also be used as a regulated supply voltage for the other IC’s. 4 4 Rx PD Output Three state voltage output of the Rx Phase Detector. This pin is either “high”, “low”, or “high impedance” depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Rx PLL loop filter. It is important to minimize the line length and capacitance of this pin. 5 5 Gnd PLL Gnd 6 6 Tx PD Output 7 7 E Cap – 8 8 Tx VCO Input Transmit divide counter input which is driven by an ac coupled external transmit loop VCO. The minimum signal level is 200 mVpp @ 80.0 MHz. This pin also functions as the test mode input for the counter tests. 9 10 11 9 10 11 Data EN Clk Input Microprocessor serial interface input pins for programming various counters and control functions. 12 12 Clk Out Output Microprocessor Clock Output which is derived from the 2nd LO crystal oscillator and a programmable divider. It can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. The driver has an internal resistor in series with the output which can be combined with an external capacitor to form a low pass filter to reduce radiated noise on the PCB. This output also functions as the output for the counter test modes. N/A 14 Status Out Output This pin indicates when the internal latches may have lost memory due to a power glitch. 13 15 CD Out/ Hardware Interrupt Output/ Input Dual function pin; 1) Carrier detect output (open collector with external 100 kΩ pull–up resistor. 2) Hardware interrupt input which can be used to “wake–up” from Inactive Mode. 14 16 BD Out Output Low battery detect output (open collector with external pull–up resistor). 15 17 DA Out Output Data amplifier output (open collector with internal 100 kΩ pull–up resistor). 16 18 SA Out Output Speaker amplifier output. 17 19 SA In Input 18 20 E Out Output Expander output. 19 21 VCC Audio Supply VCC supply for audio section. 20 22 DA In Input 21 23 Pre–Amp Out Output 22 24 Rx Audio In Input 23 25 Det Out Output 24 26 RSSI – Receive signal strength indicator filter capacitor. N/A 27 N/A – Not used. 25 28 Q Coil – A quad coil or ceramic discriminator are connected to this pin. 26 29 VCC RF Supply 27 28 30 31 Lim C2 Lim C1 – 12 Ground pin for PLL section of IC. Three state voltage output of the Tx Phase Detector. This pin is either “high”, “low”, or “high impedance” depending on the phase difference of the phase detector input signals. During lock, very narrow pulses with a frequency equal to the reference frequency are present. This pin drives the external Tx PLL loop filter. It is important to minimize the line length and capacitance on this pin. Expander rectifier filter capacitor pin. Connect capacitor to VCC. Speaker amplifier input (ac coupled). Data amplifier input (ac coupled). Pre–amplifier output for connection of pre–amplifier feedback resistor. Rx audio input to pre–amplifier (ac coupled). Audio output from FM detector. VCC supply for RF receiver section. IF amplifier/limiter capacitor pins. MOTOROLA RF/IF DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13109A PIN FUNCTION DESCRIPTION (continued) 48–TQFP Pin 52–QFP Pin Symbol Type 29 32 Lim In Input Signal input for IF amplifier/limiter. 30 33 Gnd RF Gnd Ground pin for RF section of the IC. 31 34 Mix2 Out Output 32 35 Mix2 In Input 33 36 VB – 34 37 Mix1 Out Output 35 38 Mix1 In2 Input Negative polarity first mixer input. 36 39 Mix1 In1 Input Positive polarity first mixer input. 37 38 40 41 LO1 In LO1 Out – Tank elements for 1st LO multivibrator oscillator are connected to these pins. 39 42 Vcap Ctrl – 1st LO varactor control pin. 40 43 Gnd Audio Gnd Ground for audio section of the IC. 41 44 Tx In Input Tx path input to Microphone Amplifier (ac coupled). 42 45 Amp Out Output 43 46 C In Input 44 47 C Cap – 45 48 Lim Out Output 46 49 Spl Amp In Input 47 50 Tx Out Output 48 51 Ref Input N/A 52 N/A – Description Second mixer output. Second mixer input. Internal half supply analog ground reference. First mixer output. Microphone amplifier output. Compressor input (ac coupled). Compressor rectifier filter capacitor pin. Connect capacitor to VCC. Tx path limiter output. Splatter amplifier input (ac coupled). Tx path audio output. Reference voltage input for low battery detect. Not used. Power Supply Voltage This circuit is used in a cordless telephone handset and base unit. The handset is battery powered and can operate on two or three NiCad cells or on 5.0 V power. PLL Frequency Synthesizer General Description Figure 4 shows a simplified block diagram of the programmable universal dual phase locked loop (PLL). This dual PLL is fully programmable through the MCU serial interface and supports most country channel frequencies including USA (25 ch), France, Spain, Australia, Korea, New Zealand, U.K., Netherlands and China (see channel frequency tables in Appendix A). The 2nd local oscillator and reference divider provide the reference frequency for the Rx and Tx PLL loops. The MOTOROLA RF/IF DEVICE DATA programmed divider value for the reference divider is selected based on the crystal frequency and the desired Rx and Tx reference frequency values. Additional divide by 25 and divide by 4 blocks are provided to allow for generation of the 1.0 kHz and 6.25 kHz reference frequencies required for the U.K. The 14–Bit Tx counter is programmed for the desired transmit channel frequency. The 14–Bit Rx counter is programmed for the desired first local oscillator frequency. All counters power up in the proper default state for USA channel #6 and for a 10.24 MHz reference frequency crystal. Internal fixed capacitors can be connected to the tank circuit of the 1st LO through microprocessor control to extend the sensitivity of the 1st LO for U.S. 25 channel operation. 13 MC13109A Figure 4. Dual PLL Simplified Block Diagram LO2 In 1, 1 LO2 Out 12–b ÷ 25 Programmable ÷4 Reference ÷1 Counter LO2 2, 2 14–b Programmable Tx Counter Tx VCO U.K. Base Tx Ref Tx PD Tx VCO 8, 8 Tx Phase Detector LPF 6, 6 U.K. Handset U.K. Base Rx Ref Rx PD Rx Phase Detector U.K. Handset 4, 4 Vcap Ctrl LPF 39, 42 LO1 In 14–b Programmable Rx Counter 37, 40 LO1 Out 1st LO 38, 41 ELECTRICAL CHARACTERISTICS (VCC = 2.6 V, TA = 25°C) Characteristic Condition Measure Pin Symbol Min Typ Max Unit PLL PIN DC Input Voltage Low – Data Clk EN Hardware Int. VIL – – 0.3 V Input Voltage High – Data Clk EN VIH “PLL Vref” – 0.3 – “VCC Audio” V Input Current Low Vin = 0.3 V Data Clk EN IIL –5.0 –3.0 – µA Input Current High Vin = (VCC Audio) – 0.3 Data Clk EN IIH – 0.6 5.0 µA Hysteresis Voltage – Data Clk EN Vhys – 1.0 – V Output Current High – Rx PD Tx PD IOH – – – 0.7 mA Output Current Low – Rx PD Tx PD IOL 0.7 – – mA Output Voltage Low IIL = 0.7 mA Rx PD Tx PD VOL – – (PLL Vref)* 0.2 V Output Voltage High IIH = – 0. 7mA Rx PD Tx PD VOH (PLL Vref)* 0.8 – – V Tri–State Leakage Current V = 1.2 V Rx PD Tx PD IOZ – 50 – 50 nA Input Capacitance – Data Clk EN Cin – – 8.0 pF Output Capacitance – Rx PD Tx PD Cout – – 8.0 pF 14 MOTOROLA RF/IF DEVICE DATA MC13109A ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.6 V, TA = 25°C) Condition Measure Pin Symbol Min Typ Max Unit EN to Clk Setup Time – EN, Clk tsuEC 200 – – ns Data to Clk Setup Time – Data, Clk tsuDC 100 – – ns Hold Time – Data, Clk th 90 – – ns Recovery Time – EN, Clk trec 90 – – ns Input Pulse Width – EN, Clk tw 100 – – ns Input Rise and Fall Time – Data Clk EN tr, tf – – 9.0 µs 90% of PLL Vref to Data, Clk, EN – tpuMPU – 100 – µs – LO2 In LO2 Out fLO – – 12 MHz Tx VCO ftxmax – – 80 MHz Characteristic PLL PIN INTERFACE MPU Interface Power–Up Delay PLL LOOP 2nd LO Frequency “Tx VCO” Input Frequency Vin = 200 mVpp PLL I/O Pin Specifications The 2nd LO, Rx and Tx PLL’s and MPU serial interface are normally powered by the internal voltage regulator at the “PLL Vref” pin. The “PLL Vref” pin is the output of a voltage regulator which is powered from the “VCC Audio” power supply pin. Therefore, the maximum input and output levels for most PLL I/O pins (LO2 In, LO2 Out, Rx PD, Tx PD, Tx VCO) is the regulated voltage at the “PLL Vref” pin. The ESD protection diodes on these pins are also connected to “PLL Vref”. Internal level shift buffers are provided for the pins (Data, Clk, EN, Clk Out) which connect directly to the microprocessor. The maximum input and output levels for these pins is VCC. Figure 5 shows a simplified schematic of the PLL I/O pins. Figure 6. Data and Clock Timing Requirement tr tf 90% 10% Data, Clk, EN 50% Data tsuDC th 50% Figure 5. PLL I/O Pin Simplified Schematics PLL Vref (2.2 V) I/O VCC Audio (2.0 to 5.5 V) PLL Vref (2.2 V) VCC Audio (2.0 to 5.5 V) 1.0 kΩ In Clk Out 2.0 µA LO2 In, LO2 Out, Rx PD, Tx PD and Tx VCO Pins Data, Clk, and EN Pins Clk Out Pin After data is loaded into the shift register, the data is latched into the appropriate latch register using the “EN” pin. This is done in two steps. First, an 8–Bit address is loaded into the shift register and latched into the 8–Bit address latch register. Then, up to 16–Bits of data is loaded into the shift register and latched into the data latch register specified by the address that was previously loaded. Figure 7 shows the timing required on the EN pin. Latching occurs on the negative EN transition. Microprocessor Serial Interface The “Data”, “Clk”, and “EN” pins provide an MPU serial interface for programming the reference counters, the transmit and receive channel divider counter and various control functions. The “Data” and “Clk” pins are used to load data into the shift register. Figure 6 shows “Data” and “Clk” pin timing. Data is clocked on positive clock transitions. MOTOROLA RF/IF DEVICE DATA 15 MC13109A modes; Inactive, Standby, Rx, and Active Modes. Data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. Figure 7. Enable Timing Requirement 50% 50% Last Clock Clk tsuEC First Clock Figure 9. Microprocessor Serial Interface Power–Up Delay trec 50% 2.0 V 50% Previous Data Latch EN tpuMPU VCC The state of the EN pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. Figure 8 shows the address and data programming diagrams. In the data programming mode, there must not be any clock transitions when “EN” is high. The clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the “EN” high state. The convention in these figures is that latch bits to the left are loaded into the shift register first. Figure 8. Microprocessor Interface Programming Mode Diagrams Data MSB 8–Bit Address LSB Data 16–Bit Data LSB Latch EN Data Register Programming Mode The MPU serial interface is fully operational within 100 µs after the power supply has reached its minimum level during power–up (See Figure 9). The MPU Interface shift registers and data latches are operational in all four power saving 16 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Status Latch Register Bits Address Register Programming Mode MSB Status Out This is a digital output which indicates whether the latch registers have been reset to their power–up default values. Latch power–up default values are given in Figure 28. If there is a power glitch or ESD event which causes the latch registers to be reset to their default values, the “Status Out” pin will indicate this to the MPU so it can reload the correct information into the latch registers. Figure 10. Status Out Operation Latch EN Data, Clk, EN Status Out Logic Level Latch bits not at power–up default value 0 Latch bits at power–up default value 1 Data Registers Figure 11 shows the data latch registers and addresses which are used to select each of these registers. Latch bits to the left (MSB) are loaded into the shift register first. The LSB bit must always be the last bit loaded into the shift register. “Don’t Care” bits can be loaded into the shift register first if 8–Bit bytes of data are loaded. MOTOROLA RF/IF DEVICE DATA MC13109A Figure 11. Microprocessor Interface Data Latch Registers Latch Address MSB 14–Bit Tx Counter LSB 1. (00000001) LSB 2. (00000010) Tx Counter Latch MSB 14–Bit Rx Counter Rx Counter Latch U.K. Handset Select U.K. Base Select MSB LSB 12–Bit Reference Counter 3. (00000011) Reference Counter Latch ALC Disable Not Used Limiter Disable Clk Disable MPU Clk1 MPU Clk0 MSB 14–Bit Volume Control LSB Stdby Mode Rx Mode Tx Mute Rx Mute SP Mute 4. (00000100) Mode Control Latch MSB 5–Bit CD Threshold Control LSB 5. (00000101) Threshold Control Latch 6. (00000110) 4–Bit Test Mode 3–Bit 1st LO Capacitor Selection 7. (00000111) 7–Bit Auxillary Latch Reference Frequency Selection The “LO2 In” and “LO2 Out” pins form a reference oscillator when connected to an external parallel–resonant crystal. The reference oscillator is also the second local oscillator for the RF Receiver. Figure 12 shows the relationship between different crystal frequencies and reference frequencies for cordless phone applications in various countries. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Figure 12. Reference Frequency and Reference Divider Values Crystal Frequency Reference Divider Value U.K. Base/ Handset Divider Reference Frequency 10.24 MHz 2048 1 5.0 kHz 10.24 MHz 1024 4 2.5 kHz 11.15 MHz 2230 1 5.0 kHz 12.00 MHz 2400 1 5.0 kHz 11.15 MHz 1784 1 6.25 kHz 11.15 MHz 446 4 6.25 kHz 11.15 MHz 446 25 1.0 kHz MOTOROLA RF/IF DEVICE DATA Reference Counter Figure 13 shows how the reference frequencies for the Rx and Tx loops are generated. All countries except U.K. require that the Tx and Rx reference frequencies be identical. In this case, set “U.K. Base Select” and “U.K. Handset Select” bits to “0”. Then the fixed divider is set to “1” and the Tx and Rx reference frequencies will be equal to the crystal oscillator frequency divided by the programmable reference counter value. The U.K. is a special case which requires a different reference frequency value of Tx and Rx. For U.K. base operation, set “U.K. Base Select” to “1”. For U.K. handset operation, set “U.K. Handset Select” to “1”. The Netherlands is also a special case since a 2.5 kHz reference frequency is used for both the Tx and Rx reference and the total divider value required is 4096 which is larger than the maximum divide value available from the 12–Bit reference divider (4095). In this case, set “U.K. Base Select” to “1” and set “U.K. Handset Select” to “1”. This will give a fixed divide by 4 for both the Tx and Rx reference. Then set the reference divider to 1024 to get a total divider of 4096. Mode Control Register Power saving modes, mutes, disables, volume control, and microprocessor clock output frequency are all set by the Control Register. Operation of the Control Register is explained in Figures 14 through 21. 17 MC13109A Figure 13. Reference Register Programming Mode U.K. Base Tx Reference Frequency LO2 In ÷ 25 12–b Programmable ÷4 Reference Counter ÷1 LO2 LO2 Out U.K. Base Rx Reference Frequency U.K. Handset U.K. Handset Select U.K. Base Select Tx Divider Value Rx Divider Value Application 0 0 1 1 0 1 0 1 1 25 4 4 1 4 25 4 All but U.K. and Netherlands U.K. Baseset U.K. Handset Netherlands Base and Handset U.K. Base Select U.K. Handset Select U.K. Handset MSB 12–Bit Reference Counter LSB 14–Bit Reference Counter Latch Figure 14. Control Register Bits ALC Disable Not Used Limiter Disable Clk Disable MPU Clk1 MPU Clk0 MSB 4–Bit Volume Control ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Figure 15. Mute and Disable Control Bit Descriptions ALC Disable 1 0 Automatic Level Control Disabled Normal Operation Limiter Disable 1 0 Limiter Disabled Normal Operation Clock Disable 1 0 MPU Clock Output Disabled Normal Operation Tx Mute 1 0 Transmit Channel Muted Normal Operation Rx Mute 1 0 Receive Channel Muted Normal Operation 1 0 Speaker Amp Muted Normal Operation SP Mute Power Saving Operating Modes When the MC13109A is used in a handset, it is important to conserve power in order to prolong battery life. There are five modes of operation; Active, Rx, Standby, Interrupt and Inactive. In Active Mode, all circuit blocks are powered. In Rx mode, all circuitry is powered down except for those circuit 18 Stdby Mode LSB Rx Mode Tx Mute Rx Mute SP Mute sections needed to receive a transmission from the base. In the Standby and Interrupt Modes, all circuitry is powered down except for the circuitry needed to provide the clock output for the microprocessor. In Inactive Mode, all circuitry is powered down except the MPU interface. Latch memory is maintained in all modes. Figure 16 shows the control register bit values for selection of each power saving mode and Figure 17 show the circuit blocks which are powered in each of these operating mode. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Figure 16. Power Saving Mode Selection Stdby Mode Bit Rx Mode Bit “CD Out/Hardware Interrupt” Pin Power Saving Mode 0 0 X Active 0 1 X Rx 1 0 X Standby 1 1 1 or High Impedance Inactive 1 1 0 Inactive MOTOROLA RF/IF DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13109A Figure 17. Circuit Blocks Powered During Power Saving Modes Active Rx Standby Inactive “PLL Vref” Regulated Voltage Circuit Blocks X X X1 X1 MPU Interface X X X X 2nd LO Oscillator X X X MPU Clock Output X X X RF Receiver X X 1st LO VCO X X Rx PLL X X Carrier Detect X X Data Amp X X Low Battery Detect X X Tx PLL X Rx Audio Path X Tx Audio Path X NOTE: 1. In Standby and Inactive Modes, “PLL Vref” remains powered but is not regulated. It will fluctuate with VCC. Inactive Mode Operation and Hardware Interrupt In some handset applications it may be desirable to power down all circuitry including the microprocessor (MPU). First put the MC13109A into the Inactive mode, which turns off the MPU Clock Output (see Figure 18), and then disable the microprocessor. In order to give the MPU adequate time to power down, the MPU Clock output remains active for a minimum of one reference counter cycle (about 200 µs) after the command is given to switch into the “Inactive” mode. An external timing circuit should be used to initiate the turn–on sequence. The “CD Out” pin has a dual function. In the Active and Rx modes it performs the carrier detect function. In the Standby and Inactive modes the carrier detect circuit is disabled and the “CD Out” pin is in a “High” state due to the external pull–up resistor. In the Inactive mode the “CD Out” pin is the input for the hardware interrupt function. When the “CD Out” pin is pulled “low” by the external timing circuit, the MC13109A switches from the Inactive to the Interrupt mode thereby turning on the MPU Clock Output. The MPU can then resume control of the combo IC. The “CD Out” pin must remain low until the MPU changes the operating mode from Interrupt to Standby, Active or Rx modes. Figure 18. Hardware Interrupt Operation Mode Active/Rx Interrupt MPU Initiates Inactive Mode EN CD Out/Hardware Interrupt Inactive Standby/Rx/Active MPU Initiates Mode Change External Timer Pulls Pin Low CD Out Low CD Turns Off Timer Output Disabled MPU Clock Out Delay after MPU selects Inactive Mode to when CD turns off “MPU Clock Out” remains active for a minimum of one count of reference counter after “CD Out/Hardware Interrupt” pin goes high MOTOROLA RF/IF DEVICE DATA 19 MC13109A “Clk Out” Divider Programming The “Clk Out” pin is derived from the 2nd local oscillator and can be used to drive a microprocessor, thereby reducing the number of crystals required. Figure 19 shows the relationship between the crystal frequency and the clock output for different divider values. Figure 20 shows the “Clk Out” register bit values. MPU “Clk Out” Power–Up Default Divider Value The power–up default divider value is “divide by 10”. This provides an MPU clock of about 1.0 MHz after initial power–up. The reason for choosing this relatively low clock frequency after intial power–up is that some microprocessors that operate down to a 2.0 V power supply have a maximum clock frequency of 1.0 MHz. After initial power–up, the MPU can change the clock divider value to set the clock to the desired operating frequency. Special care has been taken in the design of the clock divider to ensure that the transition between one clock divider value and another is “smooth” (i.e., there will be no narrow clock pulses to disturb the MPU). ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ Figure 19. Clock Output Values Clock Output Divider Crystal Frequency 2 3 5 10 10.24 MHz 5.120 MHz 3.413 MHz 2.048 MHz 1.024 MHz 11.15 MHz 5.575 MHz 3.717 MHz 2.230 MHz 1.115 MHz 12.00 MHz 6.000 MHz 4.000 MHz 2.400 MHz 1.200 MHz Figure 20. Clock Output Divider Clk Out Bit #1 Clk Out Bit #2 Clk Out Divider Value 0 0 2 0 1 3 1 0 5 1 1 10 MPU “Clk Out” Radiated Noise on Circuit Board The clock line running between the MC13109A and the microprocessor has the potential to radiate noise which can cause problems in the system especially if the clock is a square wave digital signal with large high frequency harmonics. In order to minimize radiated noise, a 1.0 kΩ resistor is included on–chip in–series with the “Clk Out” output driver. A small capacitor can be connected to the “Clk Out” line on the PCB to form a single pole low pass filter. This filter will significantly reduce noise radiated from the “Clk Out” line. Volume Control The volume control can be programmed in 2.0 dB gain steps from –14 dB to 16 dB. The power–up default value is 0 dB. Figure 21. Volume Control Volume Control Bit #3 Volume Control Bit #2 Volume Control Bit #1 Volume Control Bit #0 Volume Control # Gain/Attenuation Amount 0 0 0 0 0 –14 dB 0 0 0 1 1 –12 dB 0 0 1 0 2 –10 dB 0 0 1 1 3 – 8.0 dB 0 1 0 0 4 – 6.0 dB 0 1 0 1 5 – 4.0 dB 0 1 1 0 6 – 2.0 dB 0 1 1 1 7 0 dB 1 0 0 0 8 2.0 dB 1 0 0 1 9 4.0 dB 1 0 1 0 10 6.0 dB 1 0 1 1 11 8.0 dB 1 1 0 0 12 10 dB 1 1 0 1 13 12 dB 1 1 1 0 14 14 dB 1 1 1 1 15 16 dB Gain Control Register The gain control register contains bits which control the Carrier Detect threshold. Operation of these latch bits are explained in Figures 22 and 23. 20 Figure 22. Gain Control Latch Bits MSB 5–Bit CD Threshold Control LSB MOTOROLA RF/IF DEVICE DATA MC13109A Carrier Detect Threshold Programming The “CD Out” pin will give an indication to the microprocessor if a carrier signal is present on the selected channel. The nominal value and tolerance of the carrier detect threshold is given in the carrier detect specification section of this document. If a different carrier detect threshold value is desired, it can be set through the MPU interface as shown in Figure 23 below. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Figure 23. Carrier Detect Threshold Control CD Bit #4 CD Bit #3 CD Bit #2 CD Bit #1 CD Bit #0 CD Control # Carrier Detect Threshold 0 0 0 0 0 0 – 20 dB 0 0 0 0 1 1 –19 dB 0 0 0 1 0 2 –18 dB 0 0 0 1 1 3 –17 dB 0 0 1 0 0 4 –16 dB 0 0 1 0 1 5 –15 dB 0 0 1 1 0 6 –14 dB 0 0 1 1 1 7 –13 dB 0 1 0 0 0 8 –12 dB 0 1 0 0 1 9 –11 dB 0 1 0 1 0 10 –10 dB 0 1 0 1 1 11 – 9.0 dB 0 1 1 0 0 12 – 8.0 dB 0 1 1 0 1 13 –7.0 dB 0 1 1 1 0 14 – 6.0 dB 0 1 1 1 1 15 – 5.0 dB 1 0 0 0 0 16 – 4.0 dB 1 0 0 0 1 17 – 3.0 dB 1 0 0 1 0 18 – 2.0 dB 1 0 0 1 1 19 –1.0 dB 1 0 1 0 0 20 0 dB 1 0 1 0 1 21 1.0 dB 1 0 1 1 0 22 2.0 dB 1 0 1 1 1 23 3.0 dB 1 1 0 0 0 24 4.0 dB 1 1 0 0 1 25 5.0 dB 1 1 0 1 0 26 6.0 dB 1 1 0 1 1 27 7.0 dB 1 1 1 0 0 28 8.0 dB 1 1 1 0 1 29 9.0 dB 1 1 1 1 0 30 10 dB 1 1 1 1 1 31 11 dB MOTOROLA RF/IF DEVICE DATA 21 MC13109A Auxiliary Register The auxiliary register contains a 3–Bit 1st LO Capacitor Selection latch and a 4–Bit Test Mode latch. Operation of these latch bits are explained in Figures 24, 25 and 26. circuit to change the 1st LO sensitivity. Internal switches and capacitors are provided to enable microprocessor control over internal fixed capacitor values. Figure 25 shows the schematic of the 1st LO tank circuit. Figure 26 shows the latch control bit values. Figure 24. Auxiliary Register Latch Bits Figure 25. First LO Schematic MSB 4–Bit Test Mode LSB MSB 3–Bit 1st LO LSB Capacitor Selection Vcap Ctrl Varactor First Local Oscillator Capacitor Selection for 25 Channel U.S. Operation There is a very large frequency difference between the minimum and maximum channel frequencies in the proposed 25 Channel U.S. standard. The sensitivity of the 1st LO is not large enough to accommodate this large frequency variation. Fixed capacitors can be connected across the 1st LO tank 42 Internal Capacitor LO1 In 1st LO Varactor Cext 40 LO1 Out Lext 41 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Figure 26. 1st LO Capacitor Select for U.S. 25 Channels 1st LO Cap. Bit 2 1st LO Cap. Bit 1 1st LO Cap. Bit 0 1st LO Cap. Select U.S. Base Channels U.S. Handset Channels Varactor Value over 0.5 to 2.2 V Range External Capacitor Value External Inductor Value 0 0 0 0 16 – 25 – 10 – 6.4 pF 27 pF 0.47 µH 0 0 0 0 – 16 – 25 10 – 6.4 pF 33 pF 0.47 µH 0 0 1 1 1–6 – 10 – 6.4 pF 27 pF 0.47 µH 0 1 0 2 7 – 15 – 10 – 6.4 pF 27 pF 0.47 µH 0 1 1 3 – 1–6 10 – 6.4 pF 33 pF 0.47 µH 1 0 0 4 – 7 – 15 10 – 6.4 pF 33 pF 0.47 µH 22 MOTOROLA RF/IF DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13109A Figure 27. Test Mode Description Counter Under Test or Test Mode Option “Tx VCO” Input Signal “Clk Out” Output Expected >200 mVpp – TM # TM 3 TM 2 TM 1 TM 0 0 0 0 0 0 Normal Operation 1 0 0 0 1 Rx Counter, upper 6 0 to 2.2 V Input Frequency/64 2 0 0 1 0 Rx Counter, lower 8 0 to 2.2 V See Note Below 3 0 0 1 1 Rx Prescaler 0 to 2.2 V Input Frequency/4 4 0 1 0 0 Tx Counter, upper 6 0 to 2.2 V Input Frequency/64 5 0 1 0 1 Tx Counter, lower 8 0 to 2.2 V See Note Below 6 0 1 1 0 Tx Prescaler 7 0 1 1 1 Reference Counter 0 to 2.2 V Input Frequency/Reference Counter Value 8 1 0 0 0 Divide by 4, 25 0 to 2.2 V Input Frequency/100 9 1 0 0 1 AGC Gain = 10 Option N/A – 10 1 0 1 0 AGC Gain = 25 Option N/A – NOTE: >200 mVpp Input Frequency/4 To determine the correct output, look at the lower 8 bits in the Rx or Tx register (Divisor (7;0). If the value of the divisor is > 16, then the output divisor value is Divisor (7;2) (the upper 6 bits of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) > = 2, then output divisor value is Divisor (3;2) (bits 2 and 3 of the divisor). If Divisor (7;0) < 16 and Divisor (3;2) < 2, then output divisor value is (Divisor (3;2) + 60). Test Modes Test Mode Control latch bits enable independent testing of internal counters and set AGC Gain Options. In test mode, the “Tx VCO” input pin is multiplexed to the input of the counter under test and the output of the counter under test is multiplexed to the “Clk Out” output pin so that each counter can be individually tested. Make sure test mode bits are set to “0” for normal operation. Test mode operation is described in Figure 27. During normal operation and when testing the Tx Prescaler, the “Tx VCO” input can be a minimum of 200 mVpp at 80 MHz and should be ac coupled. For other test modes, input signals should be standard logic levels of 0 to 2.2 V and a maximum frequency of 16 MHz. Power–Up Defaults for Control and Counter Registers When the IC is first powered up, all latch registers are initialized to a defined state. The MC13109A is initially placed in the Rx mode with all mutes active and nothing disabled. The reference counter is set to generate a 5.0 kHz reference frequency from a 10.24 MHz crystal. The MPU clock output divider is set to 10 to give the minimum clock output frequency. The Tx and Rx latch registers are set for USA Channel Frequency #21. Figure 28 shows the initial power–up states for all latch registers. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ Figure 28. Latch Register Power–Up Defaults MSB LSB Register Count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tx 9965 – – 1 0 0 1 1 0 1 1 1 0 1 1 1 0 Rx 7215 – – 0 1 1 1 0 0 0 0 1 0 1 1 1 1 Ref 2048 – – 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Mode N/A – 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 Gain N/A – – – – – – – – – – – 1 0 1 0 0 TM N/A – – – – – – – – – 0 0 0 0 0 0 0 MOTOROLA RF/IF DEVICE DATA 23 MC13109A Figure 29. ICC versus VCC at Active Mode Figure 30. ICC versus VCC at Receive Mode 5.0 7.0 I CC , SUPPLY CURRENT (mA) I CC , SUPPLY CURRENT (mA) 8.0 6.0 5.0 4.0 3.0 2.0 4.5 4.0 3.5 3.0 1.0 3.0 3.5 4.0 4.5 2.5 2.5 5.0 3.0 3.5 Figure 31. ICC versus VCC at Standby Mode I CC , SUPPLY CURRENT (µ A) I CC , SUPPLY CURRENT (mA) 0.8 0.6 0.4 0.2 70 60 50 40 30 20 10 3.0 3.5 4.0 4.5 0 2.5 5.0 3.0 3.5 VCC, SUPPLY VOLTAGE (V) Figure 33. RSSI Output versus RFin 4.5 5.0 Figure 34. Recovered Audio/THD versus fDEV 300 1.4 250 RECOVERED AUDIO (V) RSSI OUTPUT (dB) 4.0 VCC, SUPPLY VOLTAGE (V) 1.6 1.2 1.0 0.8 0.6 0.4 6.0 R22 = 12 kΩ 200 5.0 4.0 Recovered Audio 3.0 150 100 2.0 THD 1.0 50 0.2 –100 –80 –60 –40 RFin, RF INPUT (dBm) 24 5.0 80 1.0 0 –120 4.5 Figure 32. ICC versus VCC at Inactive Mode 1.2 0 2.5 4.0 VCC, SUPPLY VOLTAGE (V) VCC, SUPPLY VOLTAGE (V) –20 0 THD (%) 0 2.5 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 9.0 fDEV, DEVIATION, (kHz) MOTOROLA RF/IF DEVICE DATA MC13109A Figure 36. Typical Compressor Response EXPANDER, E OUT (dBV) 0 –10 –20 –30 –40 –50 –60 –30 –25 –20 –15 –10 –5.0 0 0 –30 –40 –50 –60 –80 –70 –60 –50 –40 –30 –20 –10 COMPRESSOR, Cin LEVEL INPUT (dBV) Figure 37. First Mixer Third Order Intercept Performance Figure 38. Second Mixer Third Order Intercept Performance 0 –20 –20 –40 –60 –70 ACL “On” –20 0 –80 –80 ACL “Off” –10 Rx AUDIO IN (dBV) MIXER OUTPUT (dBm) MIXER OUTPUT (dBm) –70 –35 COMPRESSOR LEVEL OUTPUT, LIM OUT (dBV) Figure 35. Typical Expander Response 10 –60 –50 –40 –30 MIXER1 IN (dBm) MOTOROLA RF/IF DEVICE DATA –20 –10 0 0 –40 –60 –80 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 MIXER2 IN (dBm) 25 MC13109A APPENDIX A – MEASUREMENT OF COMPANDOR ATTACK/DECAY TIME This measurement definition is based on EIA/CCITT recommendations. Compressor Attack Time For a 12 dB step up at the input, attack time is defined as the time for the output to settle to 1.5X of the final steady state value. Compressor Decay Time For a 12 dB step down at the input, decay time is defined as the time for the input to settle to 0.75X of the final steady state value. Expander Attack For a 6.0 dB step up at the input, attack time is defined as the time for the output to settle to 0.57X of the final steady state value. Expander Decay For a 6.0 dB step down at the input, decay time is defined as the time for the output to settle to 1.5X of the final steady state value. 6.0 dB 12 dB Input Input 0 mV 0 mV Attack Time Decay Time Attack Time Decay Time 1.5X Final Value 0.57X Final Value Output 1.5X Final Value 0.75X Final Value Output 0 mV 0 mV 26 MOTOROLA RF/IF DEVICE DATA MC13109A OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848B–04 (QFP–52) ISSUE C L 39 B B 27 –A–, –B–, –D– F S D C A–B J N 0.20 (0.008) V M B 0.20 (0.008) M L DETAIL A S S H A–B –B– –A– 0.05 (0.002) A–B S DETAIL A D 26 40 BASE METAL D 14 52 1 0.02 (0.008) 13 M C A–B S D S SECTION B–B –D– 0.20 (0.008) M B H A–B S D S S D S 0.05 (0.002) A–B V 0.20 (0.008) M C A–B DETAIL C M_ C E –H– DATUM PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. 0.10 (0.004) H –C– M_ G U_ R Q_ K T W X DETAIL C SEATING PLANE DIM A B C D E F G H J K L M N Q R S T U V W X MILLIMETERS MIN MAX 9.90 10.10 9.90 10.10 2.10 2.45 0.22 0.38 2.00 2.10 0.22 0.33 0.65 BSC ––– 0.25 0.13 0.23 0.65 0.95 7.80 REF 5_ 10_ 0.13 0.17 0_ 7_ 0.13 0.30 12.95 13.45 0.13 ––– 0_ ––– 12.95 13.45 0.35 0.45 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.009 0.015 0.079 0.083 0.009 0.013 0.026 BSC ––– 0.010 0.005 0.009 0.026 0.037 0.307 REF 5_ 10_ 0.005 0.007 0_ 7_ 0.005 0.012 0.510 0.530 0.005 ––– 0_ ––– 0.510 0.530 0.014 0.018 0.063 REF Motorola reserves the right to make changes without further notice to any products herein. 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MOTOROLA RF/IF DEVICE DATA 27 MC13109A OUTLINE DIMENSIONS FTA SUFFIX PLASTIC PACKAGE CASE 932–02 (Thin QFP) ISSUE D 4X 0.200 (0.008) AB T–U Z 9 DETAIL Y A P A1 48 37 1 36 –T– –U– B V AE B1 12 25 13 AE V1 NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER IS OPTIONAL. 24 DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X –Z– S1 –T–, –U–, –Z– S DETAIL Y 4X 0.200 (0.008) AC T–U Z 0.080 (0.003) AC G –AB– –AC– AD M_ BASE METAL ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ TOP & BOTTOM N MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BASIC 0.050 0.150 0.090 0.200 0.500 0.700 12 _REF 0.090 0.160 0.250 BASIC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BASIC 0.002 0.006 0.004 0.008 0.020 0.028 12 _REF 0.004 0.006 0.010 BASIC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF R J GAUGE PLANE 0.250 (0.010) C E F D 0.080 (0.003) M AC T–U S Z SECTION AE–AE S W H Q_ K DETAIL AD X Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan. 81–3–5487–8488 Customer Focus Center: 1–800–521–6274 Mfax: [email protected] – TOUCHTONE 1–602–244–6609 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System – US & Canada ONLY 1–800–774–1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. – http://sps.motorola.com/mfax/ 852–26668334 HOME PAGE: http://motorola.com/sps/ 28 ◊ MC13109A/D MOTOROLA RF/IF DEVICE DATA