CY7C1021DV33 1-Mbit (64K x 16) Static RAM Functional Description[1] Features • Temperature Ranges The CY7C1021DV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. — Industrial: –40°C to 85°C — Automotive-A: –40°C to 85°C — Automotive-E: –40°C to 125°C • Pin-and function-compatible with CY7C1021CV33 • High speed — tAA = 10 ns • Low active power — ICC = 60 mA @ 10 ns • Low CMOS standby power • • • • • — ISB2 = 3 mA 2.0V data retention Automatic power-down when deselected CMOS for optimum speed/power Independent control of upper and lower bits Available in Pb-free 44-pin 400-Mil wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the end of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages. Logic Block Diagram 64K x 16 RAM Array SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation Document #: 38-05460 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 8, 2006 [+] Feedback CY7C1021DV33 Selection Guide –10 (Industrial/Automotive-A) –12 (Automotive-E)[2] Unit Maximum Access Time 10 12 ns Maximum Operating Current 60 100 mA Maximum CMOS Standby Current 3 15 mA Pin Configuration[3] SOJ/TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 48-ball VFBGA Top View A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O2 I/O1 C VSS I/O11 NC A7 I/O3 VCC D VCC I/O12 NC NC I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Notes 2. Automotive product information is Preliminary. 3. NC pins are not connected on the die. Document #: 38-05460 Rev. *D Page 2 of 11 [+] Feedback CY7C1021DV33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Supply Voltage on VCC to Relative GND[4] .... –0.3V to +4.6V Range Ambient Temperature VCC Speed DC Voltage Applied to Outputs in High-Z State[4] ......................................–0.3V to VCC+0.3V Industrial –40°C to +85°C 3.3V ± 0.3V 10 ns DC Input Voltage[4] ...................................–0.3V to VCC+0.3V Automotive-A –40°C to +85°C 10 ns Automotive-E –40°C to +125°C 12 ns DC Electrical Characteristics Over the Operating Range Parameter Description –10 (Ind’l/Auto-A) Test Conditions Min. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage –12 (Auto-E) Max. Min. 2.4 2.4 0.4 Voltage[4] Unit Max. V 0.4 V 2.0 VCC + 0.3 2.0 VCC + 0.3 V −0.3 0.8 −0.3 0.8 V VIL Input LOW IIX Input Leakage Current GND < VI < VCC −1 +1 −5 +5 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled −1 +1 −5 +5 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 ISB2 100 MHz 60 - mA 83 MHz 55 100 mA 66 MHz 45 90 mA 40 MHz 30 60 mA Automatic CE Power-Down Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Current —TTL Inputs Automatic CE Power-Down Max. VCC, CE > VCC – 0.3V, Current —CMOS Inputs VIN > VCC – 0.3V or VIN < 0.3V, f = 0 10 50 mA 3 15 mA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 8 pF 8 pF TA = 25°C, f = 1 MHz, VCC = 3.3V Thermal Resistance[5] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ TSOP II VFBGA Unit 59.52 53.91 36 °C/W 36.75 21.24 9 °C/W Notes 4. VIL (min.) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05460 Rev. *D Page 3 of 11 [+] Feedback CY7C1021DV33 AC Test Loads and Waveforms[6] 90% OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT ALL INPUT PULSES 3.0V Z = 50Ω 30 pF* GND 90% 10% 10% 1.5V Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns High-Z characteristics: R 317Ω 3.3V OUTPUT R2 351Ω 5 pF (c) Note 6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05460 Rev. *D Page 4 of 11 [+] Feedback CY7C1021DV33 Switching Characteristics Over the Operating Range[7] -10 (Ind’l/Auto-A) Parameter Description Min. Max. -12 (Auto-E) Min. Max. Unit Read Cycle tpower[8] VCC(typical) to the first access 100 100 µs tRC Read Cycle Time 10 12 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6 ns tLZOE tHZOE OE LOW to Low-Z[10] OE HIGH to High-Z[9, 10] CE LOW to Low-Z[10] tHZCE CE HIGH to High-Z[9, 10] tPU[11] tPD[11] CE LOW to Power-Up CE HIGH to Power-Down tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low-Z tLZCE 12 3 0 3 ns 6 3 5 ns ns 0 5 ns ns 6 ns 10 12 ns 5 6 ns 0 0 0 Byte Disable to High-Z tHZBE Write 10 3 ns 0 6 ns 6 ns Cycle[12] tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 8 9 ns tAW Address Set-Up to Write End 8 9 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-Up to Write End 5 6 ns tHD Data Hold from Write End 0 0 ns 3 3 ns WE HIGH to Low-Z[10] tHZWE WE LOW to High-Z[9, 10] tBW Byte Enable to End of Write tLZWE 5 7 6 8 ns ns Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. This parameter is guaranteed by design and is not tested. 12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05460 Rev. *D Page 5 of 11 [+] Feedback CY7C1021DV33 Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[5] tR[13] Conditions Min. Max. Unit 2 V VCC = VDR = 2.0V, CE > VCC – 0.3V, Industrial VIN > VCC – 0.3V or VIN < 0.3V Automotive Chip Deselect to Data Retention Time Operation Recovery Time 3 mA 15 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V tCDR 3.0V tR CE Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[14, 15] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE tLZOE BHE, BLE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tHZBE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05460 Rev. *D Page 6 of 11 [+] Feedback CY7C1021DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes 17. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05460 Rev. *D Page 7 of 11 [+] Feedback CY7C1021DV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read – All bits Active (ICC) L H Data Out High-Z Read – Lower bits only Active (ICC) H L High-Z Data Out Read – Upper bits only Active (ICC) L L Data In Data In Write – All bits Active (ICC) L H Data In High-Z Write – Lower bits only Active (ICC) H L High-Z Data In Write – Upper bits only Active (ICC) L X L BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) L X X H H High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code Package Name Package Type CY7C1021DV33-10VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1021DV33-10ZSXI 51-85087 44-pin TSOP Type II (Pb-free) Operating Range Industrial CY7C1021DV33-10BVXI 51-85150 48-ball VFBGA (Pb-free) 10 CY7C1021DV33-10ZSXA 51-85087 44-pin TSOP Type II (Pb-free) Automotive-A 12 CY7C1021DV33-12ZSXE 51-85087 44-pin TSOP Type II (Pb-free) Automotive-E Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05460 Rev. *D Page 8 of 11 [+] Feedback CY7C1021DV33 Package Diagrams Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082) 51-85082-*B Figure 2. 44-pin Thin Small Outline Package Type II (51-85087) 51-85087-*A Document #: 38-05460 Rev. *D Page 9 of 11 [+] Feedback CY7C1021DV33 Package Diagrams (continued) Figure 3. 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B 0.15(4X) 51-85150-*D 1.00 MAX 0.26 MAX. SEATING PLANE C All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05460 Rev. *D Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1021DV33 Document History Page Document Title: CY7C1021DV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05460 REV. ECN NO. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233693 See ECN RKF DC parameters are modified as per Eros (Spec # 01-02165). Pb-free Offering In Ordering Information *B 263769 See ECN RKF Changed I/O1 – I/O16 to I/O0 – I/O15 Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307601 See ECN RKF Reduced Speed bins to –8 and –10 ns *D 520652 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 8 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Added Automotive Information Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4 Document #: 38-05460 Rev. *D Description of Change Page 11 of 11 [+] Feedback