AVAGO ADJD-J823

ADJD-J823
Color Management Controller with Integrated RGB Photosensor
Data Sheet
Description
Features
The ADJD-J823 is a CMOS mixed-signal IC with integrated
RGB photosensors designed to be the optical feedback
device of an RGB LED-based backlighting system. A
typical system consists of an array of red, green and blue
(RGB) LEDs, LED drivers and the ADJD-J823. The device
samples the light output from the RGB LED array, processes the color information and adjusts the light output
from the RGB LEDs until the target color is achieved. To
achieve this, the device integrates an RGB photosensor
array, an analog-to-digital converter front-end, a color
data processing logic core and a high-resolution 12-bit
PWM output generator.
• Integrated RGB photosensor
• Integrated color management feedback controller
• Serial Interface
• Direct interface to standard I2C EEPROM
• 3-channel 12-bit PWM output – Red, Green and Blue LED channels
• Built-in oscillator
Applications
• LCD Backlighting
By employing a feedback system and the ADJD-J823,
the light output produced by the LED array maintains
its color over time and temperature. In addition, using
a serial interface, specifying the color of the LED array’s
light output is as simple as picking the target color coordinates from the CIE color space and writing several
bytes of data to the device.
The sensitivity of the device to light can be adjusted
through an automated process. The PWM output signals
control the on-time duration of the red, green and blue
LEDs. That duration is continually adjusted in real-time
to match the light output from the RGB LED array to the
target color.
ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge.
AVAGO TECHNOLOGIES’ PRODUCTS AND SOFTWARE ARE NOT SPECIFICALLY DESIGNED, MANUFACTURED OR AUTHORIZED FOR SALE AS
PARTS, COMPONENTS OR ASSEMBLIES FOR THE PLANNING, CONSTRUCTION, MAINTENANCE OR DIRECT OPERATION OF A NUCLEAR FACILITY
OR FOR USE IN MEDICAL DEVICES OR APPLICATIONS. CUSTOMER IS SOLELY RESPONSIBLE, AND WAIVES ALL RIGHTS TO MAKE CLAIMS
AGAINST AVAGO TECHNOLOGIES OR ITS SUPPLIERS, FOR ALL LOSS, DAMAGE, EXPENSE OR LIABILITY IN CONNECTION WITH SUCH USE.
Package Dimensions
0.75 ± 0.1
A
Seating Plane
0.2 ref
0.3
0.65 ref
1.05
3.2 ref
5.0 ± 0.1
3.2 ref
0.5 ref
5.0 ± 0.1
Note: Dimensions are in millimeter (mm)
Bottom View
Pin 1
Pin 15
Pin 14
Pin 13
Pin 12
Pin 11
Pin 1
marker
notch
Pin Information
PIN
NAME
TYPE
DESCRIPTION
1
NC
No connect
No connect. Leave floating.
2
PWMB
Output
PWMB is the active-high blue pulse width modulation output pin.
Tie it to the blue LED driver channel.
3
PWMG
Output
PWMG is the active-high green pulse width modulation output pin.
Tie it to the green LED driver channel.
4
PWMR
Output
PWMR is the active-high red pulse width modulation output pin.
Tie it to the red LED driver channel.
5
DGND
Ground
Tie to digital ground.
6
DGND
Ground
Tie to digital ground.
7
DVDD
Power
Digital power pin.
8
AGND
Ground
Tie to analog ground.
9
CLKIO
Output
CLKIO outputs a reference internal clock signal.
10
XRST
Input
Global, asynchronous, active low system reset.
When asserted low, XRST resets all registers.
Minimum reset pulse low is 10us and must be provided by external
circuitry.
11
SCLSLV
Input
12
SDASLV
Input/Output
(tri-state high)
SDASLV and SCLSLV are the serial interface communications pins.
SDASLV is the bidirectional data pin and SCLSLV is the interface clock.
A pull-up resistor should be tied to SDASLV because it goes tri-state to
output logic 1.
13
SCLPROM
Output
14
SDAPROM
Input/Output
(tri-state high)
15
SLEEP
Input
When SLEEP=1, the device goes into sleep mode. In sleep mode, all
analog circuits are powered down and the clock signal is gated away from
the core logic resulting in very low current consumption.
16
AGND
Ground
Tie to analog ground.
17
AGND
Ground
Tie to analog ground.
18
AGND
Ground
Tie to analog ground.
19
AVDD
Power
Analog power pin.
20
NC
No connect
No connect. Leave floating.
An external serial I2C EEPROM can be connected to the device to store
calibration and configuration data. SDAPROM and SCLPROM should be
tied to the I2C data (SDA) and clock (SCL) pins of the EEPROM. A pull-up
resistor should be tied to SDAPROM because it goes tri-state to output
logic 1.
Powering the Device
No voltage must be applied to IO's during
power-up and power-down ramp time
VDDD / VDDA
0V
tVDD_RAMP
ESD Protection Diode Turn-On During Power-Up and Power-Down
A particular power-up and power-down sequence must
be used to prevent any ESD diode from turning on inadvertently. The figure above describes the sequence. In
general, AVDD and DVDD should power-up and powerdown together to prevent ESD diodes from turning on
inadvertently. During this period, no voltage should be
applied to the IO’s for the same reason.
Block Diagram
SDASLV
SCLSLV
RGB
PHOTOSENSOR
ARRAY
SDAPROM
SCLPROM
PWMR
Ground Connection
PWMG
AGND and DGND must both be set to 0V and preferably
star-connected to a central power source as shown in
the application diagram. A potential difference between
AGND and DGND may cause the ESD diodes to turn on
inadvertently.
PWMB
DEVICE
CONTROLLER
XRST
PHOTOCURRENT
TO VOLTAGE
CONVERSION
RED
SLEEP
ANALOG TO
DIGITAL
CONVERSION
General Specifications
Feature
Value
Interface
100kHz serial interface
Input color format
CIE Yxy
Output PWM frequency
6.35kHz (nominal)
Output PWM resolution
12 bits
Supply
2.6V digital (nominal), 2.6V analog (nominal)
PHOTOCURRENT
TO VOLTAGE
CONVERSION
GREEN
PHOTOCURRENT
TO VOLTAGE
CONVERSION
BLUE
High Level Description
Dedicated NVPROM in Interactive Mode
A hardware reset (by asserting XRST) should be performed
before starting any operation. It is assumed that factory
calibration was performed prior deployment of ADJD-J823.
Calibration is discussed at the end of this section.
A dedicated NVPROM is connected to the device. During
factory calibration, the host can instruct the device to
upload the register data to the NVPROM. At the start of
application, the host can instruct the device to download
the register data from the NVPROM, after which the device will wait for further instructions in normal mode. The
serial interface protocol between device and NVPROM
is hard coded. A standard NVPROM such as a serial I2C
EEPROM with address 0x50 (7-bit) must be used.
The user controls and configures the device by programming a set of internal registers through a serial interface. At
the start of application, the following register data must be
written to it:
• Frequency registers
• Setup data
• Calibration data
HOST
CONTROLLER
• Bright and color input registers.
The register data is usually gathered during a calibration
process which is performed once in manufacturing. Factory
calibration is needed at a system level to map the integrated
tri-color sensor’s reading (device dependent) with a standard
device independent color space.
Once the register data is entered, the feedback operation
begins; the device starts to sample the RGB sensor using
the internal ADC. That data is compared to a user-controlled
color point target. The PWM duty factor for each channel is
adjusted in response to any error signal generated by that
comparison operation.
Thus, the actual color produced by the LEDs is maintained
close to the target.
There are three methods to operate the device. They are
differentiated by the technique in which the register data
is stored and used. The three figures below describe the
methods. NVPROM stands for Non-Volatile Programmable
Read-Only Memory such as an EEPROM.
Independent NVPROM
The NVPROM is independent from the device. During
factory calibration, the host must read the register data
from the device and write it to the NVPROM. At the start
of application, the host must read the register data from
the NVPROM and write it back to the device, after which
the device will wait for further instructions in normal
mode.
NVPROM
HOST
CONTROLLER
SDASLV
SCLSLV
DEVICE
SDASLV
SCLSLV
SDAPROM
DEVICE
SCLPROM
NVPROM
Dedicated NVPROM in Standalone Mode
A dedicated NVPROM is connected to the device. During
factory calibration, the host can instruct the device to
upload the register data to the NVPROM. The difference
versus Interactive Mode is that, in application, the device
itself will download the register data and immediately
after, enter normal mode. Then, it will start driving the
PWM channels to achieve a default target color point.
The default color point is programmed after factory
calibration. A host controller is not necessary during application. The serial interface protocol between device
and NVPROM is hard coded. So, a standard NVPROM
such as a serial I2C EEPROM with address 0x50 (7-bit)
must be used.
SDAPROM
DEVICE
SCLPROM
NVPROM
Factory Calibration
Factory calibration is needed at a system level to create
a ‘snapshot’ of the initial conditions of the system. The
color management algorithm references the snapshot
data. In effect, the calibration data trims out variation in
the entire signal chain from LEDs to sensor to ADC. The
figure below shows the calibration procedure in brief.
First, the device is put into “open loop” mode in which the
color management algorithm is turned off.
Second, the host controller needs to determine the
optimum sensor sensitivity for the given brightness detection level. The sensitivity is a combination of several
internal settings. Searching for the optimum settings can
be performed manually or through an automatic search
routine which is built into the device. The host can start
the routine by issuing a command to the device. The
device will then turn the LEDs (usually at maximum duty
factor) and start the search routine.
Next, the host needs to turn only the Red LEDs on. An
external camera must be set up to capture the CIE coordinates of the RED LEDs. The scaled XYZ readings are
then written to the device. At the same time, the host
needs to instruct the device to sample the RGB sensor
and store the results.
This is repeated for the Green and Blue LEDs.
Lastly, the host needs to instruct the device to start a
calibration calculator. The calculator uses the camera
and sensor readings for each color to develop a mapping matrix that maps the RGB sensor to the standard
CIE color space.
The mapping matrix and other configuration data is the
device setup data referred to in the previous section.
Open Loop
Sensor Gain Self-Adjustment
Read and Store Red LEDs Data
Read and Store Green LEDs Data
Read and Store Blue LEDs Data
Compute Calibration Data
Store Calibration Data &
Other Configuration Data
Factory Calibration Flow Chart
For details, refer to application note 5241 ADJD-J823
programming manual
Electrical Specifications
Absolute Maximum Ratings (Notes 1 & 2)
Parameter
Symbol
Minimum
Maximum
Units
Storage temperature
TSTG_ABS
-40
85
°C
Digital supply voltage, DVDD to DVSS
VDDD_ABS
-0.5
3.7
V
Analog supply voltage, AVDD to AVSS
VDDA_ABS
-0.5
3.7
V
Input voltage
VIN_ABS
-0.5
VDDD+0.5
V
Solder Reflow Peak temperature
TL_ABS
235
°C
Human Body Model ESD rating
ESDHBM_
2
kV
ABS
Notes
All I/O pins
All pins, human body
model per JESD22A114-B
Recommended Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Units
Free air operating temperature
TA
0
25
70
°C
Digital supply voltage, DVDD to DVSS
VDDD
2.5
2.6
3.6
V
Analog supply voltage, AVDD to AVSS
VDDA
2.5
2.6
3.6
V
Output current load high
IOH
3
mA
Output current load low
IOL
3
mA
Input voltage high level (Note 4)
VIH
0.7VDDD
VDDD
V
Input voltage low level (Note 4)
VIL
0
0.3VDDD
V
Power supply ramp period
tVDD_
100
ms
RAMP
DC Electrical Specifications Over Recommended Operating Conditions (unless otherwise specified)
Parameter
Symbol
Conditions
Minimum
Typical
(Note 3)
Output voltage high level (Note 5)
VOH
IOH = 3mA
VDDD-0.8
VDDD-0.4
Output voltage low level (Note 6)
VOL
IOL = 3mA
Dynamic supply current (Note 7,8)
Static supply current (Note 8)
Maximum
Units
V
0.2
0.4
V
IDD_DYN (Note 9)
9.4
14
mA
IDD_
(Note 9)
2.7
6
mA
(Note 9)
0.2
15
uA
10
uA
STATIC
Sleep-mode supply current (Note 8)
IDD_SLP
Input leakage current
ILEAK
-10
AC Electrical Specifications Over Recommended Operating Conditions (unless otherwise specified)
Parameter
Symbol
Internal clock frequency
fCLK
Conditions
Minimum
Typical
(Note 3)
Maximum
Units
16
26
38
MHz
Optical Specifications
Parameter
Symbol
Conditions
Minimum
Maximum
Units
Sensor operating detection range
EV
(Note 3 &10)
800
10000
Lux
Serial Interface Timing Information
Parameter
Symbol
Minimum
Maximum
Units
SCL clock frequency
fscl
0
100
kHz
(Repeated) START condition hold time
tHD:STA
4
-
ms
Data hold time
tHD:DAT
0 (Note 11)
3.45
ms
SCL clock low period
tLOW
4.7
-
ms
SCL clock high period
tHIGH
4.0
-
ms
Repeated START condition setup time
tSU:STA
4.7
-
ms
Data setup time
tSU:DAT
250
-
ns
STOP condition setup time
tSU:STO
4.0
-
ms
Bus free time between START and STOP conditions
tBUF
4.7
-
ms
tHD:STA
tHIGH
tSU:DAT
tSU:STA
tBUF
SDA
SCL
S
Sr
tLOW
tHD:DAT
tHD:STA
P
S
tSU:STO
Figure 1. Serial Interface Bus Timing Waveforms
Notes:
1. The “Absolute Maximum Ratings” are those values beyond which damage to the device may occur. The device should not be operated at these
limits. The parametric values defined in the “Electrical Specifications” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
2. Unless otherwise specified, all voltages are referenced to ground.
3. Specified at room temperature (25°C) and VDDD = VDDA = 2.6V.
4. Applies to all digital input pins.
5. Applies to all digital output pins and CLKIO pin. SDASLV and SDAPROM pins go tri-state when output logic high. Minimum VOH depends on the pull-up resistor value.
6. Applies to all digital output and digital input-output pins.
7. Dynamic testing is performed with the IC operating in a mode representative of typical operation.
8. Refers to total device current consumption.
9. Output and bidirectional pins are not loaded.
10.Using R:G:B LED light source brightness ratio of 7:13:1 to achieve white D90 color point
Red LED (x,y) = (0.700, 0.300)
Green LED (x,y) = (0.171, 0.715)
Blue LED (x,y) = (0.158, 0.019)
11. A hold time of at least 300ns must be provided internally by a device for the SDA signal ( with reference to the minimum VIH of SCL) to bridge
the undefined region of the falling edge of SCL.
Sensor Optical Performance
The integrated sensor spectral respond graph from 400 to 700nm. The color indicates the color channel of the color
sensor.
Spectral response
1
Red
Green
Blue
0.8
Red
Relative sensitivity
Green
0.6
Blue
0.4
0.2
0
400
450
500
550
600
650
700
Wavelength (nm)
System Performance
Color Accuracy chart.
Data obtain from 1078 units at 25oC and VDDD & VDDA at 2.6V. Color set point at CIE x=0.287, y=0.296 (9000K)
The average du’v’ is 0.002 with standard deviation 0.0012 and a maximum value of 0.0062.
Color Accuracy
40.0%
34.5%
35.0%
30.0%
Units
25.0%
24.9%
21.9%
20.0%
15.0%
12.9%
10.0%
4.4%
5.0%
0.0%
1.4%
0 to <1
1 to <2
2 to <3
3 to <4
du'v' (x 10-3)
4 to <5
5 to <6
0.1%
6 to <7
Color drift over temperature
Data obtain from 5 units. Color set point is at 9000K and VDDD & VDDA at 2.6V.
System consists of ADJD-J823 and RGB LEDs with color coordinates, Red (x,y) = (0.691, 0.309), Green (x,y) = (0.161, 0.704),
Blue (x,y) = (0.131, 0.073). The R:G:B luminance ratio is 2.6 : 3.9 : 1.0
Color drift
0.009
0.008
0.007
du'v'
0.006
0.005
0.004
0.003
0.002
0.001
0
0
10
20
30
40
System temperature (˚C)
50
60
Note: The starting point is at 25oC and is zero color drift as all measurements are made relative to the starting point at 25oC.
Calculating Sampling Frequency and PWM Output Frequency
The sampling frequency, fSAMP, which is the frequency at which ADJD-J823 samples the tricolor photosensor, is related
to the system clock frequency, fCLK. The output PWM frequency, fPWM, is also related to fCLK.
Calculation example:
fCLK = 26 MHz (nominal)
fCLK
fSAMP =
= 108Hz(nominal)
SAMPFREQ x 8
fPWM =
fCLK
= 6.35kHz(nominal)
(PWMFREQ + 1) x 4096
SAMPFREQ = Sampling frequency register setting = concatenation of registers [0x06][0x07]
PWMFREQ = PWM frequency register setting = register [0x05]
The internal oscillator frequency varies from part-to-part but it will not vary as significantly during operation.
10
Serial Interface Reference
Description
The programming interface to the ADJD-J823 is a 2-wire serial bus. The bus consists of a serial clock (SCL) and a serial
data (SDA) line. The SDA line is bi-directional on ADJD-J823 and must be connected through a pull-up resistor to the
positive power supply. When the bus is free, both lines are HIGH.
The 2-wire serial bus on ADJD-J823 requires one device to act as a master while all other devices must be slaves. A
master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer
while a device addressed by the master is called a slave. Slaves are identified by unique device addresses.
Both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. A
transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus.
The ADJD-J823 serial bus interface always operates as a slave transceiver with a data transfer rate of up to 100kbit/s.
START/STOP Condition
The master initiates and terminates all serial data transfers. To begin a serial data transfer, the master must send a
unique signal to the bus called a START condition. This is defined as a HIGH to LOW transition on the SDA line while
SCL is HIGH.
The master terminates the serial data transfer by sending another unique signal to the bus called a STOP condition.
This is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH.
The bus is considered to be busy after a START (S) condition. It will be considered free a certain time after the STOP (P)
condition. The bus stays busy if a repeated START (Sr) is sent instead of a STOP condition.
The START and repeated START conditions are functionally identical.
SDA
SCL
S
P
START condition
STOP condition
Figure 2. START/STOP Condition
Data Transfer
The master initiates data transfer after a START condition. Data is transferred in bits with the master generating one
clock pulse for each bit sent. For a data bit to be valid, the SDA data line must be stable during the HIGH period of the
SCL clock line. Only during the LOW period of the SCL clock line can the SDA data line change state to either HIGH or
LOW.
SDA
SCL
Data valid
Figure 3. Data Bit Transfer
11
Data change
The SCL clock line synchronizes the serial data transmission on the SDA data line. It is always generated by the master.
The frequency of the SCL clock line may vary throughout the transmission as long as it still meets the minimum timing requirements.
The master by default drives the SDA data line. The slave drives the SDA data line only when sending an acknowledge
bit after the master writes data to the slave or when the master requests the slave to send data.
The SDA data line driven by the master may be implemented on the negative edge of the SCL clock line. The master
may sample data driven by the slave on the positive edge of the SCL clock line. Figure 4 shows an example of a master
implementation and how the SCL clock line and SDA data line can be synchronized.
SDA data sampled on the
positive edge of SCL
SDA
SCL
SDA data driven on the
negative edge of SCL
Figure 4. Data Bit Synchronization
A complete data transfer is 8-bits long or 1-byte. Each byte is sent the most significant bit (MSB) first followed by an
acknowledge or not acknowledge bit. Each data transfer can send an unlimited number of bytes (depending on the
data format).
P
SDA
SCL
MSB
S
or
Sr
START or repeated
START condition
Figure 5. Data Byte Transfer
12
1
LSB
2
8
ACK
9
MSB
1
LSB
2
8
NO
ACK
9
Sr
Sr
or
P
STOP or repeated
START condition
Acknowledge/Not acknowledge
The receiver must always acknowledge each byte sent in a data transfer. In the case of the slave-receiver and mastertransmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either STOP the transfer
or generate a repeated START to start a new transfer.
SDA pulled LOW
by receiver
SDA
(SLAVE-RECEIVER)
Acknowledge
SDA
(MASTER-TRANSMITTER)
SDA left HIGH
by transmitter
LSB
SCL
(MASTER)
9
8
Acknowledge
clock pulse
Figure 6. Slave-Receiver Acknowledge
In the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end
of the data transfer to the slave-transmitter. The master can then send a STOP or repeated START condition to begin
a new data transfer.
In all cases, the master generates the acknowledge or not acknowledge SCL clock pulse.
SDA
(SLAVE-TRANSMITTER)
SDA left HIGH
by transmitter
LSB
P
SDA
(MASTER-RECEIVER)
SCL
(MASTER)
SDA left HIGH
by receiver
8
Not
acknowledge
Sr
9
Acknowledge
clock pulse
Figure 7. Master-Receiver Acknowledge
13
STOP or repeated
START condition
Addressing
Each slave device on the serial bus needs to have a unique address. This is the first byte that is sent by the mastertransmitter after the START condition. The address is defined as the first seven bits of the first byte.
The eighth bit or least significant bit (LSB) determines the direction of data transfer. A ‘one’ in the LSB of the first byte
indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). A ‘zero’ in
this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver).
A device whose address matches the address sent by the master will respond with an acknowledge for the first byte
and set itself up as a slave-transmitter or slave-receiver depending on the LSB of the first byte.
The slave address on ADJD-J823 is 0x58 (7-bits).
MSB
LSB
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
0
0
0
R/W
Slave address
Figure 8. Slave Addressing
Data format
ADJD-J823 uses a register-based programming architecture. Each register has a unique address and controls a specific
function inside the chip.
To write to a register, the master first generates a START condition. Then it sends the slave address for the device it
wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants to
write to the slave. The addressed device will then acknowledge the master.
The master writes the register address it wants to access and waits for the slave to acknowledge. The master then
writes the new register data. Once the slave acknowledges, the master generates a STOP condition to end the data
transfer.
Start condition
S
Master will write data
A6 A5 A4 A3 A2 A1 A0 W
A
Stop condition
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
Master writes
Master writes
slave address
register address
register data
Slave acknowledge
Figure 9. Register Byte Write Protocol
14
A
Slave acknowledge
A
P
Slave acknowledge
To read from a register, the master first generates a START condition. Then it sends the slave address for the device it
wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants
to write to the slave. The addressed device will then acknowledge the master.
The master writes the register address it wants to access and waits for the slave to acknowledge. The master then
generates a repeated START condition and resends the slave address sent previously. The least significant bit (LSB)
of the slave address must indicate that the master wants to read from the slave. The addressed device will then acknowledge the master.
The master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. The master
then generates a STOP condition to end the data transfer.
Start condition
Repeated start
condition
Master will write data
Master will read data
Stop condition
S A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Master sends
slave address
Master writes
register address
Slave acknowledge
Master sends
slave address
Slave acknowledge
Master reads
register data
Master not
acknowledge
Slave acknowledge
Figure 10. Register Byte Read Protocol
Application Diagrams
NC
CLKIO
1, 20
9
Float
Float
RGB LED DRIVER
PWMR
PWMG
HOST
PWMB
SYSTEM
XRST
SLEEP
SDA
SCL
10
15
12
11
4
3
2
ENABLE_RED
ENABLE_GREEN
ENABLE_BLUE
XRST
I2C SERIAL
SLEEP
EEPROM
SDASLV
SDAPROM
SCLSLV
SCLPROM
14
13
SDA
SCL
Connect pull-up
Connect pull-up
resistor to SDA
resistor to SDA
AVDD
19
AGND
8, 16,
DGND
DVDD
5, 6
7
17, 18
Voltage
Voltage
Regulator
Regulator
Star-connected ground
15
Recommended Reflow Profile
It is recommended that Henkel Pb-free solder paste LF310 be used for soldering ADJD-J823. Below is the recommended soldering profile.
T -peak
T -reflow
230 ± 5 ˚C
218 ˚C
Delta -flux = 2˚C/sec max
Delta -cooling = 2˚C/sec max
T -max
TEMPERATURE
160 ˚C
T -min 120 ˚C
Delta -ramp = 1˚C/sec max
t -pre = 40-60 sec max
t -reflow = 20 - 40 sec max
TIME
20 Lead QFN Recommended PCB Land Pad Design
20 Lead QFN Recommended Stencil Design
IPC-SM-782 is used as the standard for the PCB land pad
design. Recommended PCB finishing is gold plated.
A stencil thickness of 2.18mm (6 mils) for this QFN package is recommended
0.8 mm
0.4 mm
0.8 mm
3.19 mm
5.5 mm
3.19 mm
0.4 mm
2.18mm
3.9 mm
5.5 mm
16
Recommendations for Handling and Storage of ADJD-J823
· Before Opening the MBB (Moisture Barrier Bag)
- The sensor component must be kept sealed in a MBB (Moisture Barrier Bag) stored at 30°C and 70%RH or less at all times.
- It should also be seal with a moisture absorbent material (Silica Gel) and an indicator card (Cobalt Chloride) to
indicate the moisture within the bag.
· After Opening the MBB (Moisture Barrier Bag)
- The sensor component must be kept at 30°C and 60%RH or less
- The sensor component should have a MET (Manufacturing Exposure Time) of 24 hours starting from the time of
removal from the MBB to the soldering oven.
- If unused sensor component remain, it is recommended to store them back to the MBB.
- If the indicator card has turned from blue to pink or it has exceeded the recommended MET (Manufacturing
Exposure Time) of 24hrs, baking treatment should be performed using the following conditions before continue to IR reflow soldering.
- Baking treatment: 24 hours at 125°C.
Package Tape and Reel Dimensions
Carrier Tape Dimensions
4.00 ± 0.10
SEE NOTE #2
∅1.55 ± 0.05
2.00 ± 0.05
SEE NOTE #2
B
R 0.50 TYP.
1.75 ± 0.10
5.50 ± 0.05
12.00 ± 0.10
Bo
A
Ko
A
8.00 ± 0.10
B
∅1.50 (MIN.)
SECTION B-B
Ao
0.30 ± 0.05
SECTION A-A
NOTES:
1. Ao AND Bo MEASURED AT 0.3 mm ABOVE BASE OF POCKET.
2. 10 PITCHES CUMULATIVE TOLERANCE IS ± 0.2 mm.
3. DIMENSIONS ARE IN MILLIMETERS (mm).
17
Ao:
Bo:
Ko:
PITCH:
WIDTH:
5.30
5.30
2.20
8.00
12.00
Reel Dimensions
65°
+1.5*
12.4 - 0.0
45°
R10.65
R5.2
∅55.0 ± 0.5
45°
∅178.0 ± 0.5
∅178.0
EMBOSSED RIBS
RAISED: 0.25 mm
WIDTH: 1.25 mm
BACK VIEW
∅51.2
18.0 MAX.*
NOTES:
1. *MEASURED AT HUB AREA.
2. ALL FLANGE EDGES TO BE ROUNDED.
ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge.
AVAGO TECHNOLOGIES’ PRODUCTS AND SOFTWARE ARE NOT SPECIFICALLY DESIGNED, MANUFACTURED OR AUTHORIZED FOR SALE AS
PARTS, COMPONENTS OR ASSEMBLIES FOR THE PLANNING, CONSTRUCTION, MAINTENANCE OR DIRECT OPERATION OF A NUCLEAR FACILITY
OR FOR USE IN MEDICAL DEVICES OR APPLICATIONS. CUSTOMER IS SOLELY RESPONSIBLE, AND WAIVES ALL RIGHTS TO MAKE CLAIMS
AGAINST AVAGO TECHNOLOGIES OR ITS SUPPLIERS, FOR ALL LOSS, DAMAGE, EXPENSE OR LIABILITY IN CONNECTION WITH SUCH USE.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0106EN
AV02-0492EN - June 13, 2007