AGILENT HDJD-J822

Agilent HDJD-J822-SCR00
Color Management System
Feedback Controller
Data Sheet
Description
The HDJD-J822 is a CMOS mixedsignal IC designed to be the
optical feedback controller of an
LED-based lighting system. A
typical system consists of an
array of red, green and blue
LEDs, LED drivers, a tri-color
photosensor that samples the
light output, and the HDJD-J822.
The IC interfaces directly to the
photosensor, processes the color
information and adjusts the light
output from the LEDs until the
desired color is achieved. To
achieve this, the IC integrates a
high-accuracy 10-bit analog-todigital converter front-end, a
color data processing logic core,
and a high-resolution 12-bit PWM
output generator.
By employing a feedback system
and the HDJD-J822, the light
output produced by the LED
array maintains its color over
time and temperature. In
addition, the desired color can be
specified using a standard CIE
color space.
In addition, by incorporating a
standard I2C serial interface,
specifying the color of the LED
array’s light output is as simple as
picking the color coordinates
from the CIE color space and
writing several bytes of data to
the device.
The output PWM signals are
connected directly to the LED
drivers as enable signals. The
PWM signals control the on-time
duration of the red, green and
blue LEDs. That duration is
continually adjusted in real-time
to match the light output from the
LED array to the specified,
desired color.
Features
• –40 to 85°C operation
• I2C serial interface
• Robust CMOS-Schmitt input
• CMOS/TTL compatible output
• Multiple color input formats –
CIE XYZ, Yxy, Yu’v’ and RGB
• 3-channel analog interface to
color sensor – X, Y and Z channels
• 3-channel 12-bit PWM output –
Red, Green, and Blue LED channels
• Internal computation of calibration
data
• Internal clock generator
• Internal reference voltage
generator
• Error flag output
• External push-button interface
• Only passive components required
externally
Applications
• Backlighting
• General illumination
• Mood/accent lighting
• Color context sensitive appliances
h x 45°
Package Dimensions
E
C
H
0° MIN.
PIN 1 INDICATOR
SEE DETAIL A
SEATING PLANE
D
7° TYP.
A2
A
PARTING LINE
alpha°
e
A1
B
L
DETAIL A
DIMENSIONS IN INCHES
SYMBOL
MIN.
NOM.
A
0.093
0.099
A1
0.004
0.008
A2
0.088
0.094
B
0.013
0.016
C
0.0090
0.0100
D
0.599
0.606
E
0.292
0.296
e
0.050 BSC.
H
0.394
0.402
h
0.010
0.015
L
0.016
0.033
alpha
0°
5°
2
MAX.
0.104
0.012
0.100
0.020
0.0125
0.613
0.299
0.419
0.019
0.050
8°
Part Numbering System
HDJD - J822 - XX X XX
Option
00: Default
Packaging Type
R: Tape and Reel Standard Pack
Product Packaging
SC: SOIC
Pinout of HDJD-J822 Color Management System Feedback Controller
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
XRST
SLEEP
CLK_SEL
A1
A0
SDA
SCL
TEST
COLOR
BRIGHT
CLK_EXT
DVDD
DVSS
PWM_B
PWM_G
PWM_R
ERR_FLAG
AVSS
ROSC
VREF_EXT
SENSE_Z
SENSE_Y
SENSE_X
AVDD
Type
DI
DI
DI
DI
DI
DIO
DI
DI
DI
DI
DI
DP
DP
DO
DO
DO
DO
AP
ANA
ANA
ANA
ANA
ANA
AP
Legend
DI
Digital input pin
DO
Digital output pin
DIO Digital bi-directional pin
DP
Digital supply/ground pin
ANA Analog interface pin
AP
Analog supply/ground pin
3
XRST
P1
P24
AVDD
SLEEP
P2
P23
SENSE_X
CLK_SEL
P3
P22
SENSE_Y
A1
P4
P21
SENSE_Z
A0
P5
P20
VREF_EXT
SDA
P6
P19
ROSC
SCL
P7
P18
AVSS
TEST
P8
P17
ERR_FLAG
COLOR
P9
P16
PWM_R
BRIGHT
P10
P15
PWM_G
CLK_EXT
P11
P14
PWM_B
DVDD
P12
P13
DVSS
Top View
24-Pin SOIC
Pin Descriptions
XRST (Pin 1)
Global, asynchronous, active-low
system reset. When asserted low,
XRST resets all registers.
Minimum reset pulse low is
10 µs and must be provided by
external circuitry.
SLEEP (Pin 2)
When asserted high, SLEEP puts
the device into sleep mode. In
sleep mode, all analog circuits are
powered down and the clock
signal is gated away from the core
logic.
CLK_SEL (Pin 3)
CLK_SEL is used to select
between internal and external
clock modes. Internal clock mode
is selected when CLK_SEL=0 and
external clock mode is selected
when CLK_SEL=1.
A1, A0 (Pin 4, Pin 5)
A1 (MSB) and A0 (LSB) define the
lower two bits of the I2C slave
address.
SDA (Pin 6)
The SDA pin is the I2C data I/O
pin. SDA is a bi-directional pin.
The I/O direction is defined by an
internal signal generated by the
I2C interface block.
SCL (Pin 7)
The SCL pin is the I2C clock pin.
TEST (Pin 8)
Connect to digital ground (DVSS).
COLOR, BRIGHT (Pin 9, Pin 10)
COLOR and BRIGHT are button
interface pins. Asserting COLOR
high with BRIGHT low makes the
output color go up a color
selection ‘slider.’ To effect a
direction change, COLOR and
BRIGHT must be asserted
simultaneously for at least 0.1
second. Now, asserting COLOR
with BRIGHT low makes the
output color go down the color
4
selection slider.
Button brightness control follows
a similar procedure. Asserting
BRIGHT high with COLOR low
increases or decreases brightness
depending on the direction. To
effect a direction change, COLOR
and BRIGHT must be asserted
simultaneously for at least 0.1
second. (Refer to Application
Note 5070 for color selection
‘slider.’)
CLK_EXT (Pin 11)
CLK_EXT is the external clock
input pin. Users can choose to
use an external clock instead of
the internal clock generator by
setting CLK_SEL to high.
PWM_R, PWM_G, PWM_B (Pin 16,
Pin 15, Pin 14)
The PWM_R, PWM_G, and
PWM_B output pins drive the
external LED drivers that drive
the LED arrays. Typically PWM_R
drives only the red LEDs, PWM_G
drives only the green LEDs and
PWM_B drives only the blue
LEDs. They are the output enable
signals of the red, green and blue
LED drivers. So, they control the
on-time duration of the LEDs.
The assertion level of the PWM*
signals can be toggled by the user
to support both active-low and
active-high enable input pins at
the LED driver side. This is done
by configuring the PWML bit of
register CONFIG1.
ERR_FLAG (Pin 17)
The ERR_FLAG pin is asserted
high when an error condition is
detected. The user can determine
the type of error by reading the
ERROR register. The error
conditions are described in the
‘High Level Description’ section.
SENSE_X, SENSE_Y, SENSE_Z (Pin
23, Pin 22, Pin 21)
The SENSE_X, SENSE_Y and
SENSE_Z pins are analog input
pins which are tied to the
X-channel, Y-channel and
Z-channel of the photosensor
output respectively. An averaging
filter is placed in between the
sensor output and the SENSE_X,
SENSE_Y and SENSE_Z pins. The
filter is typically a 68 kΩ -1 µF
single-pole low-pass filter.
VREF_EXT (Pin 20)
The VREF_EXT pin is an analog
input pin, which provides an
external reference voltage for the
ADC. Typically, users will use the
internal reference generator to
operate the ADC. However, in
specific application conditions,
an external reference may be
required. The external reference
is enabled by setting the VREFS
bit of register CONFIG1 high.
ROSC (Pin 19)
A 68 kΩ precision 1% resistor is
connected from the ROSC to
AVSS pin for use by the internal
oscillator. In external clock
mode, ROSC can be left floating.
(Refer to Application Note 5070
for resistor selection.)
DVDD, DVSS, AVDD, AVSS (Pin 12,
Pin 13, Pin 24, Pin 18)
HDJD-J822 has separate power
ground nets for the analog and
digital section. A star connection
from a central power source is
recommended when designing
the wiring to these supply pins.
DVDD
DVSS
AVDD
AVSS
= Digital positive supply
= Digital ground
= Analog positive supply
= Analog ground
General Specifications
Feature
Interface
Input Color Format
Input Sensor Signal
Minimum Dynamic Range
Value
I2C 100 kHz
CIE XYZ, Yxy, Yu’v’ and RGB (illuminant E)
0 to 2.5 V (typical configuration)
Sensor output > 500 (ADC output code, each channel)
during calibration
610 Hz nominal (typical configuration)
12 bits
Assertion on ERR_FLAG pin indicates an error condition
Upper 5 bits 10101 binary, lower 2 bits defined by
A1:A0 pins in that order
5 V digital, 5 V analog (nominal)
Schmitt-CMOS input and CMOS/TTL compatible output
Output PWM Frequency
Output PWM Resolution
Error Flag
Device Address Control
Supply
I/O
Block Diagram
CLK_EXT
VREF_EXT
ROSC
XRST
VREF
CLOCK
REFERENCE
VOLTAGE
MUX
INTERNAL
OSCILLATOR
SENSE_X
SENSE_Y
ADC
SENSE_Z
BRIGHT
PUSH_BUTTON
SENSOR
COLOR
PROGRAMMABLE
AMPLIFIER
DUTY FACTOR
MODE SELECT
CLK_SEL
SDA
SCL
A1
I2C
INTERFACE
CONTROL
INTERNAL REGISTERS
CONTROL
CONFIG
DATA:
SETPOINT
CALIBRATION
COLOR
CONTROLLER
PWM GENERATOR
TEST
SLEEP
PWM_R
PWM_G
PWM_B
A0
CONTROL
SIGNALS
DVDD
DVSS
AVDD
AVSS
5
SYSTEM CONTROLLER
ERR_FLAG
HDJD-J822 Block Diagram Description
Function
Description
Programmable
Amplifier
If the sensor output is not within the required dynamic range, the amplifier’s gain can be
changed from unity to 2 to boost the sensor signal.
ADC
Analog-to-digital converter. Converts the sensor signal from analog to digital.
VREF
Reference voltage generator. Provides a stable voltage level to the ADC. Can be bypassed with an
external reference generator.
Internal Oscillator
Generates a clock signal for the logic circuits. Can be bypassed with an external clock signal.
Mode Select
The device operation mode (normal, sleep, internal/external clock) is determined by the
status of the SLEEP and CLK_SEL pins.
I2C Interface Control
Serial interface controller. Manages the I2C communications protocol.
Internal Registers
The primary method in which the device is configured. Contains a bank of registers. Each bit is
mapped to a specification, function or mode of operation. The internal registers also contain a
range of calibration registers. (Refer to the ‘High Level Description’ section and the Application
Note 5070 for calibration procedures).
Color Controller
Contains the color processing algorithms that operate on the sensor data. The algorithms correct
the PWM output duty factors if there is a mismatch between the desired color and actual color
produced.
Converts the input color coordinates into an internally understood format. Default input format is
CIE RGB (illuminant E).
PWM Generator
Receives the duty factor values from the Color Controller and generates 3 PWM signals.
System Controller
Performs internal functions – housekeeping, interfacing between blocks, generating control
signals, etc.
High Level Description
A hardware reset (by asserting
XRST) should be performed
before starting any operation. It is
assumed that factory calibration
was performed prior to
deployment of HDJD-J822.
Calibration is discussed at the end
of this section.
The user controls and configures
HDJD-J822 by programming a set
of internal registers. The registers
are programmed through the I2C
protocol – a standard,
synchronous, serial interface. The
registers define operation modes
such as sensor slope, reference
voltage selection, color space
format, PWM assertion level, etc.
6
Selection between internal and
external clock can only be made
through pin setup.
A
•
•
•
typical set-up would be:
Positive sensor slope
Internal reference voltage
100 Hz (nominal) sensor
sample rate
• 610 Hz PWM (nominal)
• Active-high PWM output
• 2.5 MHz (nominal) internal
oscillator
HDJD-J822 resets into an “idle”
mode and the PWM outputs are
held low.
If the PWM assertion level bit
(PWML) of register CONFIG1 is
changed to high, the PWM outputs
will then be held high. However,
since the reset condition for that
register bit is low, HDJD-J822
always resets with the PWM
outputs held low.
The next step after setting up the
device is to write the calibration
data to the calibration registers
(address 0x8A to 0xA8). The
calibration data is typically stored
in an external non-volatile
memory. After writing the data,
the user can set the PWM enable
bit (PWME) of register CTRL1 to
begin normal operation.
The operation begins with the
processor taking in the tri-color
sensor’s digitized readings from
the internal ADC. That data is
compared to the desired color/
brightness setting. The PWM duty
factor is adjusted in response to
any error signal generated by that
comparison operation. The user
can change the color/brightness
setting at any time by writing to
the appropriate device registers
(address 0xE8 to 0xED during
normal operation).
The feedback and processing
operation is repeated at a rate of
100 Hz (nominal).
The PWM signal is applied to the
LED drivers and controls the ontime duration of the red, green
and blue LEDs.
The user can input the desired
color/brightness in a variety of
color formats such as CIE XYZ,
Yxy, Yu’v’ and RGB (illuminant E).
There are three indicators in
register ERROR that monitor the
status of the color management
system. Refer to Application Note
5070.
Factory calibration is needed at a
system level to create a ‘snapshot’
of the initial conditions of the
system. The color management
7
algorithm references the snapshot
data. In effect, the calibration data
trims out variation in the entire
signal chain from LEDs to sensor
to filter to ADC. The calibration
discussion below is brief. Refer to
Application Note 5070 for
detailed calibration procedures.
RED LEDs. The readings are stored
in the ADC reading registers
(SENSOR_ADCZ, SENSOR_ADCY,
SENSOR_ADCX registers). The
user must read those registers and
transfer them to the RED LED
sensor calibration registers
(address 0xFA to 0xFF).
First, the device is put into “open
loop” mode by setting the OPMD
bit of register CONFIG1 to high. In
open loop mode, the color
management algorithm is turned
off.
This is repeated for GREEN and
BLUE LEDs.
Second, all LEDs are switched on
to maximum PWM. During this,
the ADC output is read out to
check if the sensor output is
within the dynamic range of the
system i.e., 500 < pass < 1000. An
optional internal 2x gain (1) can
be selected if the ADC reading is
between 250 and 500. This
procedure is performed for each
sensor channel.
Next, only the RED LEDs are
switched on. An external camera
must be set up to capture the CIE
co-ordinates (preferably XYZ) of
the RED LEDs. The scaled XYZ
readings are then sent to the RED
LED camera calibration registers
(address 0xE8 to 0xED during
calibration mode). Next, the GSSR
bit of register CTRL2 is set to
capture the sensor readings of the
The RCAL bit of register CTRL2 is
then set, after which HDJD-J822
will compute the 31 bytes of
calibration data :
CAL_DATA0 to CAL_DATA30
(2)
The 2 pieces of calibration data is
noted as (1), and (2) above. The
user will need to read them from
the device registers via I2C and
store them in an external nonvolatile memory. They will have to
be written to the appropriate
registers prior to the start of
normal operation, and should be
part of the system boot-up
sequence.
Electrical Specifications
Absolute Maximum Ratings (Note 1 & 2)
Parameter
Symbol
Minimum
Maximum
Units
Storage Temperature
TSTG_ABS
-65
150
°C
Digital Supply Voltage, DVDD to DVSS
VDDD_ABS
-0.3
6.0
V
Analog Supply Voltage, AVDD to AVSS
VDDA_ABS
-0.3
6.0
V
Input Voltage
VIN_ABS
-0.3
VDDD + 0.3
V
Solder Reflow Peak Temperature
TL_ABS
260
°C
Latch-Up Current
IL_ABS
100
mA
Human Body Model ESD Rating
ESDHBM_ABS
2
kV
Machine Model ESD Rating
ESDMM_ABS
200
V
-100
Notes
All I/O pins
All pins, human body
model MIL883
Method 3015
Recommended Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Units
Free Air Operating Temperature
TA
-40
25
85
°C
Digital Supply Voltage, DVDD to DVSS
VDDD
4.5
5
5.5
V
Analog Supply Voltage, AVDD to AVSS
VDDA
4.5
5
5.5
V
HIGH Level Output Current
IOH
3
mA
LOW Level Output Current
IOL
3
mA
External Clock Frequency
fCLK_EXT
3.3
MHz
ROSC Resistor
Rosc
VREF_EXT Analog Input Pin Input Voltage
VREF_EXT
2.5
4.0
V
SENSE_* Input Pins Input Voltage
VSENSE
0.0
VREF
V
(Note 4)
VDDD or VDDA Minus SENSE_*
VDIFF_SENSE
1.0
V
(Note 5)
Internal Reference Nominal Voltage
VREF_INT
2.45
2.5
2.55
V
(Note 6)
Internal Oscillator Nominal Frequency
with Rosc = 68 kΩ
fCLK_INT
1.8
2.5
3.3
MHz
(Note 6)
5
%
Internal Oscillator Frequency Variation
over Temperature with Rosc = 68 kΩ
8
1.8
2.5
68
-5
kΩ
Notes
(Note 3)
DC Electrical Specifications
Over Recommended free air Operating Temperature Range, and VDDD = VDDA = 4.5 V/5 V/5.5 V (unless otherwise specified).
Parameter
Symbol
Minimum HIGH Level Input Voltage
(Note 7)
VIH
Maximum LOW Level Input Voltage
(Note 7)
VIL
Digital Input Pin Schmitt +ve Threshold
(Note 7)
VIPOS
Digital Input Pin Schmitt -ve Threshold
(Note 7)
VINEG
0.2 VDDD
V
Digital Input Pin Schmitt Hysteresis
(Note 7) (Note 8)
VIHYS
1.0
V
Minimum HIGH Level Output Voltage
(Note 9)
VOH
VIN = VIH or VIL
IOH = 3 mA
0.9 VDDD
VDDD
V
Maximum LOW Level Output Voltage
(Note 10)
VOL
VIN = VIH or VIL
IOL = 3 mA
0
0.4
V
Dynamic Digital Supply Current
(Note 11)
IDDD_DYN
CLK_SEL=1
fCLK_EXT = 3.3 MHz
4
mA
Sleep-Mode Digital Supply Current
IDDD_SLP
15
µA
Standby Digital Supply Current
IDDD_STNBY
CLK_SEL=1
15
µA
Dynamic Analog Supply Current
(Note 11)
IDDA_DYN
CLK_SEL=1
fCLK_EXT = 3.3 MHz
3
mA
Sleep-mode Analog Supply Current
IDDA_SLP
15
µA
Standby Analog Supply Current
IDDA_STNBY
15
µA
9
Conditions
CLK_SEL=1
Minimum
Typical
Maximum
Units
0.7 VDDD
VDDD
V
0
0.3 VDDD
V
0.8 VDDD
V
I2C Timing (SDA, SCL)
Symbol
Parameter
Min.
Max.
Units
fscl
SCL clock frequency
0
100
kHz
tHD:STA
(Repeated) START condition hold time
4.0
-
µs
tHD:DAT
Data hold time
0
3.45
µs
tLOW
SCL clock low period
4.7
-
µs
tHIGH
SCL clock high period
4.0
-
µs
tSU:STA
Repeated START condition setup time
4.7
-
µs
tSU:DAT
Data setup time
250
-
ns
tSU:STO
STOP condition setup time
4.0
-
µs
tBUF
Bus free time between START and STOP conditions
4.7
-
µs
t HD:STA
t HIGH
t SU:DAT
t SU:STA
t SU:STO
t BUF
SDA
SCL
Sr
S
t LOW
t HD:DAT
P
S
t HD:STA
Figure 1. I2C bus timing waveforms.
Notes:
1. The “Absolute Maximum Ratings” are those values beyond which damage to the device may occur. The device should not be operated at these
limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for actual device operation.
2. Unless otherwise specified, all voltages are referenced to ground.
3. A 1% precision resistor is recommended. This resistor is tied from the ROSC pin to ground.
4. VREF = VREF_INT in internal reference configuration. VREF = VREF_EXT in external reference configuration.
5. The voltage level at any of the SENSE_* pins must be lower than VDDD or VDDA (whichever is lower) by at least VDIFF_SENSE volts.
6. TA = 25°C. Room temperature.
7. Applies to all DI pins.
8. Guaranteed by design.
9. Applies to all DO pins. SDA is an open-drain NMOS. Minimum VOH depends on the pull-up resistor value.
10. Applies to all DO and DIO pins.
11. Dynamic testing is performed when the IC is operating in a mode representative of typical operation.
10
Notes on Sampling Frequency and
PWM Output Frequency
The sampling frequency, fSAMP,
which is the frequency at which
HDJD-J822 samples the tricolor
photosensor, is related to the
system clock frequency, fCLK.
The output PWM frequency,
fPWM, is also related to fCLK. The
system clock is sourced from
either the internal oscillator or
an external clock.
Calculation example:
fCLK = 2.5 MHz (nominal)
fSAMP = fCLK/25087 = 100 Hz
(nominal)
fPWM = fCLK/4095 = 610 Hz
(nominal)
The internal oscillator frequency
varies from part-to-part but it
will not vary significantly during
operation.
Register Description
The user controls and configures
HDJD-J822 by programming a
set of internal registers, through
the I2C protocol. Refer to
Application Note 5070 for
programming guide and register
description.
I2C Interface
Description
The programming interface to
HDJD-J822 is a standard 2-wire
serial bus, which follows the I2C
data transmission protocol. This
protocol defines a transmitter
as a device that sends data to
the bus and a receiver as a
device that receives data from
the bus.
A master is a device that
initiates a data transfer on the
bus, generates the clock signal
and terminates the data
transfer. A device addressed by
the master is called a slave. Both
master and slave can act as a
transmitter or a receiver but the
master controls the direction for
data transfer.
The bus consists of a serial clock
(SCL) and a serial data (SDA)
line. Both lines are bi-directional
and connected to the positive
power supply through a pull-up
resistor. When the bus is free,
both lines are HIGH.
START/STOP Condition
To begin an I2C data transfer,
the master must send a unique
signal to the bus called a START
condition. This is defined as a
HIGH to LOW transition on the
SDA line while SCL is HIGH.
The master terminates the
transfer by sending another
unique signal to the bus called a
STOP condition. This is defined
as a LOW to HIGH transition on
the SDA line while SCL is HIGH.
The bus is considered to be busy
after a START (S) condition. It
will be considered free a certain
time after the STOP (P)
condition. The bus stays busy if
a repeated START (Sr) is sent
instead of a STOP condition.
The START and repeated START
conditions are functionally
identical.
HDJD-J822’s I2C bus interface
always operates as a slave
transceiver in standard mode.
Standard mode has a data
transfer rate of up to 100 kbit/s.
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 2. START/STOP condition.
11
Data Transfer
The master initiates data transfer
after a START condition. Data is
transferred in bits with the
master generating one clock pulse
for each bit sent. For a data bit to
be valid, the SDA data line must
be stable during the HIGH period
of the SCL clock line. Only during
the LOW period of the SCL clock
line can the SDA data line change
state to either HIGH or LOW.
P
SDA
MSB
LSB
ACK
MSB
LSB
NO
ACK
Sr
SCL
S
or
Sr
1
2
8
9
1
2
8
Sr
or
P
9
START or REPEATED
START CONDITION
STOP or REPEATED
START CONDITION
Figure 3. Data bit transfer.
A complete data transfer is 8-bits
long or 1-byte. Each byte is sent
most significant bit (MSB) first
followed by an acknowledge or
not acknowledge bit. Each data
transfer can send an unlimited
number of bytes.
P
SDA
MSB
LSB
ACK
MSB
LSB
NO
ACK
Sr
SCL
S
or
Sr
1
START or REPEATED
START CONDITION
Figure 4. Data byte transfer.
12
2
8
9
1
2
8
9
Sr
or
P
STOP or REPEATED
START CONDITION
Acknowledge/Not Acknowledge
The receiver must always
acknowledge each byte sent in a
data transfer. In the case of the
slave-receiver and mastertransmitter, if the slave-receiver
does not send an acknowledge bit,
the master-transmitter can either
STOP the transfer or generate a
repeated START to start a new
transfer.
SDA PULLED LOW
BY RECEIVER
SDA
(SLAVE-RECEIVER)
ACKNOWLEDGE
SDA
(MASTER-TRANSMITTER)
SCL
(MASTER)
LSB
SDA LEFT HIGH
BY TRANSMITTER
8
9
ACKNOWLEDGE
CLOCK PULSE
Figure 5. Slave-receiver acknowledge.
In the case of the master-receiver
and slave-transmitter, the master
generates a not acknowledge to
signal the end of the data transfer
to the slave-transmitter. The
master can then send a STOP or
repeated START condition to
begin a new data transfer.
In all cases, the master generates
the acknowledge or not
acknowledge SCL clock pulse.
SDA
(SLAVE-TRANSMITTER)
SDA LEFT HIGH
BY TRANSMITTER
LSB
P
SDA
(MASTER-RECEIVER)
NOT
ACKNOWLEDGE
SDA LEFT HIGH
BY RECEIVER
SCL
(MASTER)
8
Sr
9
ACKNOWLEDGE
CLOCK PULSE
Figure 6. Master-receiver acknowledge.
13
STOP OR REPEATED
START CONDITION
Addressing
Each device on the I2C bus needs
to have a unique address. This is
the first byte that is sent by the
master-transmitter after the
START condition. The protocol
defines the address as the first
seven bits of the first byte.
and slave-transmitter). A ‘zero’ in
this position indicates that the
master will write data to the
addressed slave (mastertransmitter and slave-receiver).
A device whose address matches
the address sent by the master
will respond with an acknowledge
for the first byte and set itself up
as a slave-transmitter or slavereceiver depending on the LSB of
the first byte.
The eighth bit or least significant
bit (LSB) determines the direction
of data transfer. A ‘one’ in the
LSB of the first byte indicates that
the master will read data from the
addressed slave (master-receiver
MSB
The slave address in HDJD-J822 is
made up of a fixed part and a
programmable part. The fixed
part is A6 to A2 and is set as
shown in Figure 7. The
programmable part is A1 and A0,
which is set by external package
pins. The programmable address
pins allows a maximum of four
HDJD-J822 chips on the same I2C
bus to be addressed (address
range from 54h to 57h).
LSB
A6
A5
A4
A3
A2
1
0
1
0
1
A1
A0
R/W
SLAVE ADDRESS
Figure 7. Slave addressing.
Data Format
HDJD-J822 uses a register-based
programming architecture. Each
register has a unique address and
controls a specific function inside
the chip.
Then it sends the slave address
for the device it wants to
communicate with. The least
significant bit (LSB) of the slave
address must indicate that the
master wants to write to the slave.
The addressed device will then
acknowledge the master.
To write to a register, the master
first generates a START condition.
START CONDITION
S
MASTER WILL WRITE DATA
A6 A5 A4 A3 A2 A1 A0 W
MASTER SENDS
SLAVE ADDRESS
A
STOP CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ACKNOWLEDGE
14
A
D7 D6 D5 D4 D3 D2 D1 D0
MASTER WRITES
REGISTER ADDRESS
Figure 8. Register byte write protocol.
The master writes the register
address it wants to access and
waits for the slave to
acknowledge. The master then
writes the new register data. Once
the slave acknowledges, the
master generates a STOP
condition to end the data transfer.
SLAVE ACKNOWLEDGE
A
P
MASTER WRITES
REGISTER DATA
SLAVE ACKNOWLEDGE
To read from a register, the
master first generates a START
condition. Then it sends the slave
address for the device it wants to
communicate with. The least
significant bit (LSB) of the slave
address must indicate that the
master wants to write to the slave.
The addressed device will then
acknowledge the master.
START CONDITION
S
MASTER WILL WRITE DATA
A6 A5 A4 A3 A2 A1 A0 W
A
MASTER SENDS
SLAVE ADDRESS
REPEATED START CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
A
Figure 9. Register Byte Read Protocol.
SLAVE ACKNOWLEDGE
slave. The addressed device will
then acknowledge the master.
The master reads the register data
sent by the slave and sends a no
acknowledge signal to stop
reading. The master then
generates a STOP condition to end
the data transfer.
STOP CONDITION
MASTER WILL READ DATA
Sr A6 A5 A4 A3 A2 A1 A0
MASTER WRITES
REGISTER ADDRESS
SLAVE ACKNOWLEDGE
15
The master writes the register
address it wants to access and
waits for the slave to
acknowledge. The master then
generates a repeated START
condition and resends the slave
address sent previously. The least
significant bit (LSB) of the slave
address must indicate that the
master wants to read from the
R
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
MASTER READS
REGISTER DATA
MASTER SENDS
SLAVE ADDRESS
SLAVE ACKNOWLEDGE
MASTER NOT ACKNOWLEDGE
Application Diagrams
68 KΩ, 1 µF
PASSIVE LOW PASS FILTER
LPF
SENSE_*
2.5 V
DVDD
vref = internal = 2.5 V
DVDD
AVDD
0V
SENSOR
AVDD
XRST
SLEEP
SENSE_X
LPF
CH_X
CLK_SEL
A1
SENSE_Y
SENSE_Z
LPF
CH_Y
CH_Z
A0
SDA
VREF_EXT
ROSC
SCL
TEST
AVSS
ERR_FLAG
LPF
68 KΩ
LED DRIVER
COLOR
PWM_R
EN_RED
BRIGHT
CLK_EXT
PWM_G
PWM_B
EN_GREEN
EN_BLUE
DVDD
DVSS
CONTROL BUS
Typical Operation*
68 KΩ, 1 µF
PASSIVE LOW PASS FILTER
LPF
SENSE_*
2.5 V
DVDD
vref = internal = 2.5 V
DVDD
AVDD
0V
DVDD
SLEEP
SENSE_X
LPF
CH_X
CLK_SEL
A1
SENSE_Y
SENSE_Z
LPF
CH_Y
CH_Z
A0
SDA
VREF_EXT
ROSC
SCL
TEST
AVSS
ERR_FLAG
LPF
68 KΩ
LED DRIVER
COLOR
PWM_R
EN_RED
BRIGHT
CLK_EXT
PWM_G
PWM_B
EN_GREEN
EN_BLUE
DVDD
DVSS
CONTROL BUS
Button Mode Operation*
Refer to Application Note 5070
for implementation details.
*The SDA pull-up is only required
at system level. It is shown in the
diagram for reference only.
16
SENSOR
AVDD
XRST
Package Tape and Reel Dimensions
24 Pin Wide Body Carrier Tape
4 ± 0.1
*SEE NOTE 1
2 ± 0.1
*SEE NOTE 6
∅1.5 ± 0.1
0.3 ± 0.1
1.75 ± 0.1
A
R0.3 MAX.
11.5 ± 0.1
*SEE NOTE 6
24 ± 0.3
B0
R0.5 TYP.
K0
12 ± 0.1
A
1.55 + 1.00/–0.05 DIA.
SECTION A-A
A0 = 10.9 mm ± 0.1
B0 = 16.0 mm ± 0.1
K0 = 3.0 mm ± 0.1
A0
Notes:
1. 10 sprocket hole pitch cumulative tolerance is ± 0.2mm.
2. Camber not to exceed 1 mm in 100 mm.
3. Material: Black Conductive Advantek Polystyrene.
4. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket.
5. K0 measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
7. Dimensions are in millimeters.
Peak Fixed Reels
LEGEND
W – Width
A – Shaft Diameter
B – Hub Diameter
C – Window Size
D – Total Reel Diameter
E – Shaft Key Hole
F – Reel Thickness
30
D3 5045 4
P 24/
W
PART NO. (VARIABLE)
SIZE (VARIABLE)
E
A
B
C
Notes:
1. Material: Polystyrene (Blue).
2. Antistatic coated.
3. Flange warpage: 3 mm maximum.
4. All dimensions are in millimeters.
5. ESD – Surface resistivity: 105 to 1011 Ω/sq.
D
PEA
K
F
W
W
A
B
Min.
Max.
Min.
24.4
26.4
12.80 13.20
17
Max.
C
Min.
Max.
98
102
Min.
D
Max.
Min.
225.75 226.25 326
E
Max.
F
Min.
Max.
Min.
Max.
330.25 1.95
2.45
2
2.8
www.agilent.com/semiconductors
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Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
October 11, 2004
5989-1321EN