WEDC W3DG64126V7D2

White Electronic Designs
W3DG64126V-D2
1GB – 2x64Mx64, SDRAM UNBUFFERED
FEATURES
DESCRIPTION
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
The W3DG64126V is a 2x64Mx64 synchronous DRAM
module which consists of sixteen 64Mx8 SDRAM
components in TSOP II package and one 2K EEPROM
in an 8 Pin TSSOP package for Serial Presence Detect
which are mounted on a 168 Pin DIMM multilayer FR4
Substrate.
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
Available with "WP" write protect on pin 81 option
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
• W3DG63126V-D2
3.3V ± 0.3V Power Supply
168 Pin DIMM JEDEC
• PCB: 30.50mm (1.20in)
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
VSS
29
DQM1
57
DQ18
85
VSS
113
DQM5
141
DQ50
2
DQ0
30
CS0#
58
DQ19
86
DQ32
114
CS1#
142
DQ51
3
DQ1
31
DNU
59
VCC
87
DQ33
115
RAS#
143
VCC
4
DQ2
32
VSS
60
DQ20
88
DQ34
116
VSS
144
DQ52
5
DQ3
33
A0
61
NC
89
DQ35
117
A1
145
NC
6
VCC
34
A2
62
*VREF
90
VCC
118
A3
146
*VREF
7
DQ4
35
A4
63
CKE1
91
DQ36
119
A5
147
DNU
8
DQ5
36
A6
64
VSS
92
DQ37
120
A7
148
VSS
9
DQ6
37
A8
65
DQ21
93
DQ38
121
A9
149
DQ53
10
DQ7
38
A10/AP
66
DQ22
94
DQ39
122
BA0
150
DQ54
11
DQ8
39
BA1
67
DQ23
95
DQ40
123
A11
151
DQ55
12
VSS
40
VCC
68
VSS
96
VSS
124
VCC
152
VSS
13
DQ9
41
VCC
69
DQ24
97
DQ41
125
CK1
153
DQ56
14
DQ10
42
CK0
70
DQ25
98
DQ42
126
A12
154
DQ57
15
DQ11
43
VSS
71
DQ26
99
DQ43
127
VSS
155
DQ58
16
DQ12
44
DNU
72
DQ27
100
DQ44
128
CKE0
156
DQ59
17
DQ13
45
CS2#
73
VCC
101
DQ45
129
CS3#
157
VCC
18
VCC
46
DQM2
74
DQ28
102
VCC
130
DQM6
158
DQ60
19
DQ14
47
DQM3
75
DQ29
103
DQ46
131
DQM7
159
DQ61
20
DQ15
48
DNU
76
DQ30
104
DQ47
132
*A13
160
DQ62
21
*CBO
49
VCC
77
DQ31
105
*CB4
133
VCC
161
DQ63
22
*CB1
50
NC
78
VSS
106
*CB5
134
NC
162
VSS
23
Vss
51
NC
79
CK2
107
VSS
135
NC
163
CK3
24
NC
52
*CB2
80
NC
108
NC
136
*CB6
164
NC
25
NC
53
*CB3
81
***WP
109
NC
137
*CB7
165
**SA0
26
VCC
54
VSS
82
**SDA
110
VCC
138
VSS
166
**SA1
27
WE#
55
DQ16
83
**SCL
111
CAS#
139
DQ48
167
**SA2
28
DQM0
56
DQ17
84
VCC
112
DQM4
140
DQ49
168
VCC
A0 – A12
BA0-1
DQ0-63
CK0-CK3
CKE0, CKE1
CS0# - CS3#
RAS#
CAS#
WE#
DQM0-7
VCC
VSS
SDA
SCL
DNU
NC
WP
Address input (Multiplexed)
Select Bank
Data Input/Output
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply
Ground
Serial data I/O
Serial clock
Do not use
No Connect
Write Protect
* These pins are not used in this module.
** These pins should be NC in the system which
does not support SPD.
*** WP available on the W3DG63126V-D2 only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3DG64126V-D2
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQM0
DQM4
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQM
CS#
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQM
CS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
CS#
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS#
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS3#
CS2#
DQM2
DQM6
DQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQM
CS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQM
CS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 ~ A12, BA0 & 1
SDRAM
RAS#
SDRAM
CAS#
SDRAM
WE#
SDRAM
CKE0
8SDRAM
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SCL
WP
A0
VCC
SDA
A1
A2
WP
SA0 SA1 SA2
10K Ω
CKE1
8SDRAM
SDRAM
10Ω
DQn
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM7
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
10Ω
Every DQpin of SDRAM
SDRAM
CK0/1/2/3
SDRAM
VCC
One 0.1uF Capacitors
per each SDRAM
SDRAM
To all SDRAMs
1.5pF
Vss
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3DG64126V-D2
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Storage Temperature
Power Dissipation
PD
8
W
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ +70°C
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
3.0
VCCQ+0.3
V
Note
1
Input Low Voltage
VIL
-0.3
—
0.8
V
2
Output High Voltage
VOH
2.4
—
—
V
IOH = -2mA
Output Low Voltage
VOL
—
—
0.4
V
IOL = -2mA
Input Leakage Current
ILI
-10
—
10
µA
3
Note:
1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VCC
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF=1.4V ± 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
CIN1
66
pF
Input Capacitance (RAS#,CAS#,WE#)
CIN2
66
pF
Input Capacitance (CKE0-CKE1)
CIN3
66
pF
Input Capacitance (CK0-CK3)
CIN4
16
pF
Input Capacitance (CS0#-CS3#)
CIN5
21
pF
Input Capacitance (DQM0-DQM7)
CIN6
15
pF
Input Capacitance (BA0-BA1)
CIN7
66
pF
Data input/output capacitance (DQ0-DQ63)
COUT
15
pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3DG64126V-D2
IDD SPECIFICATIONS AND CONDITIONS
VCC, VCCQ = +3.3V ±0.3V; SDRAM component values only
MAX
SYMBOL
7
7.5
10
UNITS
NOTES
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN)
PARAMETER/CONDITION
IDD1
1,920
1,760
1,760
mA
1
STANDBY CURRENT: Power-Down Mode; All device devicebanks idle; CKE = LOW
IDD2
56
56
56
mA
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks
active after tRCD met; No accesses in progress
IDD3
720
720
720
mA
OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All
device banks active
IDD4
2,000
1,840
1,840
mA
1
AUTO REFRESH CURRENT
tRFC = tRFC (MIN)
IDD5
3,920
3,920
3,920
mA
2
CKE = HIGH; CS# = HIGH
tRFC = 7.8125µs
IDD6
96
96
96
mA
IDD7
96
96
96
mA
SELF REFRESH CURRENT: CKE < 0.2V
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3DG64126V-D2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
VCC, VCCQ = +3.3V ±0.3V
AC CHARACTERISTICS
7
PARAMETER
Access timefrom CLK (pos.edge)
SYMBOL
CL = 3
tAC(3)
CL = 2
tAC(2)
Address hold time
MIN
7.5
MAX
MIN
5.4
10
MAX
MIN
5.4
5.4
6
MAX
UNITS
NOTE
6
ns
27
6
ns
tAH
0.8
0.8
1
ns
Address setup time
tAS
1.5
1.5
2
ns
CLK high-level width
tCH
2.5
2.5
3
ns
CLK low-level width
tCL
2.5
2.5
3
ns
CL = 3
tCK(3)
7
7.5
8
ns
23
CL = 2
tCK(2)
7.5
10
10
ns
23
tCKH
0.8
0.8
1
ns
CKE setup time
tCKS
1.5
1.5
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
0.8
0.8
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
1.5
2
ns
Data-in hold time
tDH
0.8
0.8
1
ns
Data-in setup time
tDS
1.5
1.5
2
ns
Clock cycle time
CKE hold time
Data-out high-impedance time
CL = 3
tHZ(3)
5.4
5.4
6
ns
10
CL = 2
tHZ(2)
5.4
6
6
ns
10
Data-out low-impedance time
tLZ
1
1
1
ns
Data-out hold time (load)
tOH
2.7
2.7
2.7
ns
Data-out hold time (no load)
tOHN
1.8
ACTIVE to PRECHARGE command
tRAS
37
ACTIVE to ACTIVE command period
tRC
60
66
66
ns
ACTIVE to READ or WRITE delay
tRCD
15
20
20
ns
Refresh period
tREF
64
64
64
ms
AUTOREFRESH period
tRFC
66
66
66
ns
PRECHARGE command period
tRP
15
20
20
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
14
tT
0.3
tWR
1 CLK
+
7ns
1 CLK
+
7.5ns
1 CLK
+
7.5ns
14
15
15
ns
25
67
75
80
ns
20
Transition time
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
tXSR
1.8
120,000
1.8
44
120,000
15
1.2
50
ns
120,000
15
0.3
1.2
0.3
28
ns
ns
1.2
ns
7
24
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3DG64126V-D2
AC FUNCTIONAL CHARACTERISTICS
VCC, VCCQ = +3.3V ±0.3V
PARAMETER
SYMBOL
7
7.5
10
UNITS
NOTES
READ/WRITE command to READ/WRITE command
tCCD
1
1
1
tCK
17
CKE to clock disable or power-down entry mode
tCKED
1
1
1
tCK
14
CKE to clock enable or power-down exit setup mode
tPED
1
1
1
tCK
14
DQM to input data delay
tDQD
0
0
0
tCK
17
DQM to data mask during WRITEs
tDQM
0
0
0
tCK
17
DQMto data high-impedance during READs
tDQZ
2
2
2
tCK
17
WRITE command to input data delay
tDWD
0
0
0
tCK
17
Data-into ACTIVE command
tDAL
4
5
5
tCK
15, 21
Data-into PRECHARGE command
tDPL
2
2
2
tCK
16, 21
Last data-in to burst STOP command
tBDL
1
1
1
tCK
17
Last data-in to new READ/WRITE command
tCDL
1
1
1
tCK
17
Lastdata-into PRECHARGE command
tRDL
2
2
2
tCK
16, 21
LOADMODEREGISTER command to ACTIVE or REFRESH command
tMRD
2
2
2
tCK
26
CL = 3
tROH(3)
3
3
3
tCK
17
CL = 2
tROH(2)
2
2
2
tCK
17
Data-out to high-impedance from PRECHARGE command
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25°C; pin under test biased at
1.4V; f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.) The
two AUTO REFRESH command wake-ups should be repeated any time the tREF
refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
W3DG64126V-D2
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5.
22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7;
7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC133, PC100 specify three clocks.
27. tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3DG64126V-D2
ORDERING INFORMATION
Part Number
Speed
CAS Latency
Height*
Speed
CAS Latency
Height*
W3DG64126V10D2
100MHz
CL=2
30.48 (1.20")
Part Number
W3DG63126V10D2
100MHz
CL=2
30.48 (1.20")
W3DG64126V7D2
133MHz
CL=2
30.48 (1.20")
W3DG63126V7D2
133MHz
CL=2
30.48 (1.20")
W3DG64126V75D2
133MHz
CL=3
30.48 (1.20")
W3DG63126V75D2
133MHz
CL=3
30.48 (1.20")
NOTE:
1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS
Compliant)
2 * Product specific part numbers are available for source control if needed, please
consult factory for the correct part number if a specific component vendor is
preferred.
3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options
NOTE: Available with "WP" Write Protect on pin 81.
PACKAGE DIMENSIONS
133.48
(5.255 MAX.)
3.81
(0.150)
MAX.
3.18
(0.125) (2X)
3.99
(0.157)
(2X)
30.48
(1.200)
17.78 MAX.
(0.700)
P1
11.43
(0.450)
8.89
(0.350)
36.83
(1.450)
54.61
(2.150)
6.35
(0.250)
42.16
(1.660)
3.99
(0.157 MIN.)
6.35
(0.250)
1.27 ± 0.10
(0.050 ± 0.004)
115.57
(4.550)
*ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3DG64126V-D2
Document Title
1GB - 2x64Mx64, SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev A
Created
5-3-02
Advanced
Rev B
Corrected mechanical drawing
5-21-02
Advanced
Rev 0
0.1 Update CAP and IDD specs
12-04
Preliminary
1-05
Final
0.2 Moved from Advanced to Preliminary
Rev 1
1.1 Added lead-free and RoHS notes
1.2 Added source control notes
1.3 Added industrial temperature options
1.4 Moved Preliminary to Final
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com