White Electronic Designs W3HG64M72EER-AD7 ADVANCED* 512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM FEATURES DESCRIPTION 244-pin, very low profile dual in-line memory module (VLP Mini-DIMM) Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300*, and PC2-6400* Supports ECC error detection and correction The W3HG64M72EER is a 64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of nine 64Mx8 bit with 4 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 244-pin DIMM FR4 substrate. VCC = VCCQ = 1.8V ±0.1V VCCSPD = 1.7V to 3.6V Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Programmable CAS# latency (CL) Posted CAS# additive latency (AL) On-die termination (ODT) Programmable burst lenghts: 4 or 8 Serial Presence Detect (SPD) with EEPROM Auto and Self Refresh Capability (64ms: 8,192 cycle refresh) Gold (Au) edge contacts RoHS compliant Single Rank Package option * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • Vendor source control options • Industrial temperature option • Parity option • 244 Pin Mini-DIMM • PCB – 18.29mm (0.72") OPERATING FREQUENCIES PC2-3200 PC2-4200 PC2-5300* PC2-6400* Clock Speed 200MHz 266MHz 333MHz 400MHz CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 6-6-6 * Contact factory for availability December 2005 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED PIN CONFIGURATION PIN NAMES Pin No. 1 Symbol VREF Pin No. 62 Symbol A4 Pin No. 123 Symbol VSS Pin No. 184 Symbol VCCQ 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS NC VCCQ CKE0 VCC NC NC/ERR_ OUT VCCQ A11 A7 VCC A5 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 VCCQ A2 VCC VSS VSS NC/PAR_IN VCC A10/AP BA0 VCC WE# VCCQ CAS# VCCQ NC NC VCCQ NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC VCCQ NC VCC NC NC VCCQ 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 A3 A1 VCC CK0 CK0# VCC A0 BA1 VCC RAS# VCCQ S0# VCCQ ODT0 A13 VCC NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 118 119 120 121 122 DQ58 DQ59 VSS SA0 SA1 179 180 181 182 183 A12 A9 VCC A8 A6 240 241 242 243 244 DQ63 VSS SDA SCL VCCSPD 57 58 59 60 61 December 2005 Rev. 1 Pin Name A0-A13 BA0,BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0 CK0,CK0# CKE0 S0# RAS# CAS# WE# RESET# DM (0-8) VCCSPD VCC VCCQ A10/AP VSS PAR_IN ERR_OUT SA0-SA2 SDA SCL NC VREF 2 Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination control Clock Inputs, positive line Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable Register Reset Input Data Masks SPD Power Core Power I/O Power Address Input/Auto Precharge Ground Parity bit for the addess and control bus Parity error found on the address and control bus SPD address SPD Data Input/Output Clock Input No connect Input/Output Reference White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED FUNCTIONAL BLOCK DIAGRAM RS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS# DQS DQS# DQS1 DQS1# DM1 DQS5 DQS5# DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQS2 DQS2# DM2 DQS6 DQS6# DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQS3 DQS3# DM3 DQS7 DQS7# DM7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS# DQS DQS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM/ RDQS I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DQS8 DQS8# DM8 VCCSPD Serial PD VCC/VCCQ DDR SDRAMs VREF DDR SDRAMs VSS DDR SDRAMs Serial PD SCL SDA WP A0 R E G I S T E R S0# BA0 - BA1 A0 - A13 RAS# CAS# WE# CKE0 ODT0 A2 RS0# S0# DDR2 SDRAMs RBA0 - RBA1 BA0 - BA1 DDR2 SDRAMs SA0 SA1 SA2 RA0 - RA13 A0 - A13 DDR2 SDRAMs RRAS# RAS# DDR2 SDRAMs RCAS# RCAS# DDR2 SDRAMs CK0 RWE# WE# DDR2 SDRAMs RCKE0 CKE0 DDR2 SDRAMs P L RODT0 ODT0 DDR2 SDRAMs CK0# RST# RESET# A1 RESET# CK L OE DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM Register CK# NOTE: All resistor values are 22 ohms ±5% unless otherwise specified. December 2005 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage VCCL Supply voltage I/O Reference voltage I/O Termination voltage Symbol VCC VCCQ VCCL VREF VTT Min 1 .7 1 .7 1 .7 0.49 x VCCQ VREF-0.04 Typical 1 .8 1 .8 1 .8 0.50 x VCCQ VREF Max 1 .9 1 .9 1 .9 0.51 x VCCQ VREF + 0.04 Unit V V V V V Notes 1 4 4 2 3 Notes: 1. VCC and VCCQ must track each other. VCCQ must be less than or equal to VCC. 2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not excedd ±1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VCCQ tracks with VCC; VCCL track with VCC. ABSOLUTE MAXIMUM DC RATINGS Symbol VCC VCCQ VCCL VIN, VOUT TSTG TCASE TOPR IL IOZ IVREF Parameter Voltage on VCC pin relative to VSS Voltage on VCCQ pin relative to VSS Voltage on VCCL pin relative to VSS Voltage on any pin relative to VSS Storage temperature Device operating temperature Operating temperature (ambient) Command/Address, RAS#, CAS#, WE#, CS#, CKE CK, CK# DM Input leakage current; Any input 0V<VIN<VCC; VREF input 0V<VIN<0.95V; Other pins not under test = 0V Output leakage current; 0V<VOUT<VCCQ; DQs and ODT are disable VREF leakage current; VREF = Valid VREF level DQ, DQS, DQS# MIN -1.0 -0.5 -0.5 -0.5 -55 0 0 MAX 2.3 2.3 2.3 2.3 100 85 55 U nit V V V V °C °C °C -5 5 µA -5 -5 5 5 µA µA -5 5 µA -18 18 µA Min Max Unit INPUT/OUTPUT CAPACITANCE TA=25 0 C, f=1 00MHz Parameter Symbol Input capacitance (A0 - A1 3, BA0 - BA1 ,RAS#,CAS#,WE#) CIN1 pF Input capacitance ( CKE0), (ODT0) CIN2 pF Input capacitance (CS0#) CIN3 pF Input capacitance (CK0, CK0#) CIN4 pF CIN5 pF COUT1 pF Input capacitance (DM0 - DM8), (DQS0 - DQS8) Input capacitance (DQ0 - DQ63), (CB0 - CB7) December 2005 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED OPERATING TEMPERATURE CONDITION Parameter Operating temperature Symbol Rating Units Notes TOPER 0°C to 85°C °C V Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. Forthe measurement conditions, please refer to JEDEC JESD51 .2 2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit Input High (Logic 1 ) Voltage VIH(DC) VREF + 125 VREF + 300 mV Input Low (Logic 0) Voltage VIL(DC) -300 VREF - 125 mV INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Unit AC Input High (Logic 1 ) Voltage (DDR2-400/533) VIH(AC) VREF + 250 — mV AC Input High (Logic 1) Voltage (DDR2-667) VIH(AC) VREF + 200 AC Input Low (Logic 0) Voltage VIL(AC) — December 2005 Rev. 1 5 mV VREF - 250 mV White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED DDR2 ICC SPECIFICATIONS AND CONDITIONS Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V Symbol Parameter ICCO* Operating one bank active-precharge; ICC1* Operating one bank active-readprecharge; ICC2P** ICC2Q** ICC2N** ICC3P** Precharge powerdown current; Precharge quite standby current; Precharge standby current; Active power-down current; ICC3N** Active standby current; ICC4W* Operating burst write current; ICC4R* Operating burst read current; ICC5** Burst auto refresh current; ICC6** Self refresh current; ICC7* Operating bank interleave read curent; Condition tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING IOUT = OmA; BL = 4; CL = CL(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data pattern is sames as ICC4W. All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING All banks idle; tCK = tCK(ICC); CKE is HIGH; CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Fast PDN Exit All banks open; tCK = tCK(ICC), CKE is LOW; MRS(12) = 0 Other control and address bus inputs are Slow PDN Exit STABLE; Data bus inputs are FLOATING MRS(12) = 1 All banks open; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING All banks open; Continuous burst reads; TOUT = OmA; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(ICC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. tCK = tCK(ICC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING CK and CK# at OV; CKE < 0.2V; Other control and address bus inputs are FLOATING; Data Normal bus inputs are FLOATING All bank interleaving reads; IOUT = OmA; BL = 4; CL = CL(ICC); AL = tRCD(ICC) - 1*tCK(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING 806 667 534 403 Unit TBD 810 720 720 mA TBD 945 855 810 mA TBD 45 45 45 mA TBD 450 360 315 mA TBD 495 405 360 mA TBD 315 270 225 mA TBD 90 90 90 mA TBD 585 495 405 mA TBD 1,395 1,170 990 mA TBD 1,575 1,305 1,035 mA TBD 1,890 1,800 1,710 mA TBD 45 45 45 mA TBD 2,520 2,340 2,070 mA Notes: ICC specification is based on MICRON components. Other DRAM manufacturers specification may be different. * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition. December 2005 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED AC TIMING PARAMETERS 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS 806 PARAMETER MIN MAX tCK (6) TBD TBD CL = 5 tCK (5) TBD TBD 3,000 8,000 ps 16, 24 CL = 4 tCK (4) TBD TBD 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 24 CL = 3 tCK (3) TBD TBD 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 24 CK high-level width tCH TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18 CK low-level width tCL TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18 Half clock period tHP 19 TBD MIN (tCH, tCL) ps TBD TBD TBD -450 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Clock Data tAC Data-out high-impedance window from CK/CK# tHZ Data-out low-impedance window from CK/CK# tLZ DQ and DM input setup time relative to DQS tDSa DQ and DM input hold time relative to DQS tDHa DQ and DM input setup time relative to DQS tDSb DQ and DM input hold time relative to DQS tQHb DQ…DQS hold, DQS to first DQ to go nonvalid, per access relative to DQS tDIPW Data hold skew factor tQHS DQ–DQS hold, DQS to first DQ to go nonvalid, per access tQH Data valid output window (DVW) tDVW DQS input high pulse width MAX MIN 403 SYMBOL DQ output access time from CK/CK# MIN 534 CL = 6 Clock cycle time Data Strobe 667 MIN (tCH, tCL) +450 -500 tAC (MAX) tAC (MIN) MAX tAC (MAX) MIN MIN (tCH, tCL) +500 -600 tAC MAX tAC (MIN) tAC (MAX) tAC (MIN) 8, 9 tAC (MAX) ps 8, 10 400 ps 7, 15, 21 100 100 150 tCK 7, 15, 21 175 225 275 ps 7, 15, 21 0.35 0.35 0.35 ps 340 400 450 tQHtDQSQ tDQSH TBD TBD 0.35 0.35 0.35 DQS input low pulse width tDQSL TBD TBD 0.35 DQS output access time from CK/CK# tDQSCK TBD TBD -400 TBD TBD TBD TBD TBD TBD TBD TBD tRPRE ps 350 tQHtDQSQ DQS read preamble tAC MAX 300 tQHtDQSQ tDQSQ ps 7, 15, 21 TBD DQS–DQ skew, DQS to last DQ valid, per group, per access +600 ps TBD tDSH 16, 24 400 TBD DQS falling edge from CK rising – hold time Notes ps 350 TBD tDSS UNIT 300 tHPtQHS DQS falling edge to CK rising– setup time MAX tHPtQHS tHPtQHS 15, 17 15, 17 0.35 +400 -450 tCK 0.35 +450 -500 tCK +500 ps 0.2 0.2 0.2 tCK 0.2 0.2 0.2 tCK 240 0.9 1.1 300 0.9 1.1 0.9 350 ps 15, 17 1.1 tCK 35 NOTE: • AC specification is based on MICRON components. Other DRAM manufactures specification may be different. December 2005 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED AC TIMING PARAMETERS (Continued) 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS Command and Address Data Strobe PARAMETER 806 665 534 403 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes DQS read preamble tRPST TBD TBD 0.4 0.6 0.4 0.6 0.4 0.6 tCK 35 DQS write preamble setup time tWPRES TBD TBD ps 12, 13, 36 DQS write preamble tWPRE TBD TBD 0.35 DQS write postamble tWPST TBD TBD 0.4 Write command to first DQS latching transition tDQSS TBD TBD WL0.25 WL0.25 WL0.25 tCK Address and control input pulse width for each input tIPW TBD TBD 0.6 0.6 0.6 tCK Address and control input setup time tISa TBD TBD 400 500 600 ps 6, 21 Address and control input hold time tIHa TBD TBD 400 500 600 ps 6, 21 Address and control input setup time tISb TBD TBD 200 250 350 ps 6, 21 Address and control input hold time tIHb TBD TBD 275 375 475 ps 6, 21 CAS# to CAS# command delay tCCD TBD TBD 2 2 2 tCK Active to Active (same bank) command tRC TBD TBD 55 55 55 ns 33 Active bank a to Active b bank command tRRD TBD TBD 7.5 7.5 7.5 ns 27 TBD TBD 15 15 15 ns 37.5 37.5 ns 30 ns 20, 33 0 0 Active to Read or Write delay tRCD Four Bank Activate period tFAW TBD TBD 37.5 0 0.25 0.6 70,000 0.4 40 0.25 0.6 70,000 0.4 40 tCK 0.6 70,000 tCK 11 Active to precharge command tRAS TBD TBD 40 Internal Read to precharge command delay tRTP TBD TBD 7.5 7.5 7.5 ns 23, 27 Write recovery time tWR TBD TBD 15 15 15 ns 27 Auto precharge wirte recovery and precharge time tDAL TBD TBD tWR+tRP tWR+tRP tWR+tRP ns 22 Interval Write to Read command delay tWTR TBD TBD 10 7.5 10 ns 27 Precharge command period tRP TBD TBD 15 15 15 ns 31 Precharge All command period tRPA TBD TBD tRP+tCK tRP+tCK tRP+tCK ns 31 Load Mode command cycle time tMRD TBD TBD 2 2 2 tCK CKE low to CK,CK# uncertainty tDELAY TBD TBD tIS+tCK+tIH tIS+tCK+tIH tIS+tCK+tIH ns 28 NOTE: • AC specification is based on MICRON components. Other DRAM manufactures specification may be different. December 2005 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED AC TIMING PARAMETERS (Continued) 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V Power-Down ODT Self Refresh AC CHARACTERISTICS 806 665 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Refresh to Active or Refresh to Refresh command interval tRFC TBD TBD 105 70,000 105 70,000 105 70,000 ns 14 Average periodic refresh interval tREFI TBD TBD 200 7.8 7.8 µs 14 Exit self refresh to non-read command tXSNR TBD TBD tRFC (MIN)+10 tRFC (MIN)+10 tRFC (MIN)+10 ns Exit self refresh to read command tXSRD TBD TBD 200 200 200 tCK Exit self refresh timing reference tISXR TBD TBD tIS tIS tIS ps ODT turn-on delay tAOND TBD TBD 2 2 2 2 2 2 tCK ODT turn-on tAON TBD TBD tAC(MIN) tAC(MAX) +700 tAC(MIN) tAC(MAX) +1,000 tAC(MIN) tAC(MAX) +1,000 ps ODT turn-off delay tAOFD TBD TBD 2.5 2.5 2.5 2.5 2.5 2.5 tCK ODT turn-off tAOF TBD TBD tAC(MIN) tAC(MAX) +600 tAC(MIN) tAC(MAX) +600 tAC(MIN) tAC(MAX) +600 ps ODT turn-on (power-down mode) tAONPD TBD TBD 2x tCK + tAC (MAX) + 1,000 ps ODT turn-off (power-down mode) tAOFPD TBD TBD 2x tCK + tAC (MAX) + 1,000 tCK ODT to power-down entry latency tANPD TBD TBD 3 3 3 tCK ODT power-down exit latency tAXPD TBD TBD 8 8 8 tCK Exit active power-down to READ command, MR[bit12=0] tXARD TBD TBD 2 2 2 tCK Exit active power-down to READ command, MR[bit12=1] tXARDS TBD TBD 7-AL 6-AL 6-AL tCK Exit precharge power-down to any non-READ command. tXP TBD TBD 2 2 2 tCK CKE minimum high/low time tCKE TBD TBD 3 3 3 tCK tAC(MIN) +2,000 tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000 7.8 tAC(MIN) +2,000 tAC(MIN) +2,000 2x tCK + tAC (MAX) + 1,000 2x tCK + tAC (MAX) + 1,000 tAC(MIN) +2,000 tAC(MIN) +2,000 6, 29 25 26 34 NOTE: • AC specification is based on MICRON components. Other DRAM manufactures specification may be different. December 2005 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED High-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH (DC) prior to tDQSH (MIN). Notes 1. All voltages referenced to VSS 2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. 12. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turn around. 13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 14. The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs. However, a REFRESH command must be asserted at least once every 70.3µs or tRFC (MAX). To ensure all rows of all banks are properly refreshed, 8192 REFRESH commands must be issued every 64ms. 15. Each half-byte lane has a corresponding DQS. 16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2V/ns if measured differentially). 17. The data valid window is derived by achieving other specifications - tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. This value can be greater than the minimum specification limits for tCL and tCH. For example, tCL and tCH are = 50 percent of the period, less the half period jitter [tJIT(HP)] of the clock source, and less the half period jitter due to cross talk [tJIT(cross talk)] into the clock traces. 19. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs. 20. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM devices. 21. VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb DDR2 SDRAM data sheet for more detail. 22. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 + (4) clocks = 8 clocks. 23. The minimum READ to internal PRECHARGE time. This parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) ≤ 1, then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has to be satisfied as well. The DDR2 SDRAM device will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied. Outputs measured with equivalent load: VTT = VCCQ/2 25Ω Output (VOUT) 4. 5. 6. 7. Reference Point AC timing and ICC tests may use a VIL to VIH swing of up to 1.0V in the test environment parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH (AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as specified. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). Command/Address minimum input slew rate is at 1.0V/ns. Command/Address input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated using tISb and the Setup and Hold Time Derating Values table. tIS timing (tISb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timming (tIHb) is referenced from VIH (AC) for a rising signal and VIL (DC) for a falling signal. The timing table also lists the tISb and tIHb values for a 1.0V/ns slew rate; these are the “base” values. Data minimum input slew rate is at 1.0V/ns. Data input timing must be derated if the slew rate is not 1.0V/ns. This is easily accommodated if the timing is referenced from the logic trip points. tDS timing (tDSb) is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH (DC) for a risng signal and VIL (DC) for a falling signal. The timing table lists the tDSb and tDHb values for a 1.0V/ns slew rate. If the DQS/DQS# differential strobe feature is not enabled, timing is no longer referenced to the crosspoint of DQS/DQS#. Data timing is now referenced to VREF, provided the DQS slew rate is not less than 1.0V/ns. If the DQS slew rate is less than 1.0V/ns, then data timing is now referenced to VIH (AC) for a rising DQS and VIL (DC) for a falling DQS. 8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (when the device output is no longer driving (tHZ) or begins driving (tLZ). 9. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. 24. 10. tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition. Operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. 25. 11. The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, low or ODT turn-on time tAON (MIN) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND. December 2005 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED 26. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high impedance. Both are measured from tAOFD. 27. This parameter has a two clock minimum requirement at any tCK. 28. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. 29. tISXR is equal to tIS and is used for CKE setup time during self refresh exit. 30. No more than 4 bank ACTIVE commands may be issued in a given tFAW (MIN) period. tRRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. 31. tRPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices. December 2005 Rev. 1 11 32. Value is minimum pulse width, not the number of clock registrations. 33. Applicable to Read cycles only. Write cycles generally require additional time due to Write recovery time (tWR) during arto precharge. 34. tCKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2* tCK + tIH. 35. This parameter is not referenced to a specific voltage level, but specified when the device output is no longer driving (tRPST) or beginning to drive (tRPRE). 36. When DQS is used single-ended, the minimum limit is reduced by 100ps. White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED ORDERING INFORMATION FOR AD7 Part Number Speed/Data Rate CAS Latency tRCD tRP Height* W3HG64M72EER806AD7xG** 400MHz/800Mb/s 6 6 6 18.29mm (0.72") W3HG64M72EER665AD7xG** 333MHz/667Mb/s 5 5 5 18.29mm (0.72") W3HG64M72EER534AD7xG 266MHz/533Mb/s 4 4 4 18.29mm (0.72") W3HG64M72EER403AD7xG 200MHz/400Mb/s 3 3 3 18.29mm (0.72") **Contact factory for availability. NOTES: • RoHS product. (“G” = RoHS Compliant) • Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR VLP AD7 FRONT VIEW 3.80 (0.150) MAX 82.127 (3.233) 81.873 (3.223) 1.00 (0.039) R X2 18.45 (0.726) 18.15 (0.715) 1.80 (0.071) D X2 10.0 (0.394) TYP 6.0 (0.236) TYP 1.10 (0.043) 0.90 (0.035) 0.50 (0.02) R 1.0 (0.039) TYP 2.0 (0.079) TYP PIN 122 PIN 1 42.9 (1.689) TYP 3.60 (0.142) 78.0 (3.071) TYP FULL R BACK VIEW 3.80 ±0.10 (0.150 ±0.004) 1.30 (0.051) 1.00 ±0.05 (0.039 ±0.002) Detail A 0.25 (0.010) MAX 2.55 (0.100) 3.3 (0.130) TYP 0.60 (0.024) 3.6 (0.142) TYP PIN 123 PIN 244 33.6 (1.323) TYP 3.2 (0.126) TYP 0.45±0.03 (0.018 ±0.001) Detail B 38.4 (1.512) TYP Detail A Detail B Tolerances: + /- 0.13 (0.005) unless otherwise specified. * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) December 2005 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED PART NUMBERING GUIDE W 3 H G 64M 72 E E R xxx AD7 x G WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH (x8) 1.8V REGISTERED SPEED (Mb/s) VLP PACKAGE 244 PIN (0.72) COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT December 2005 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3HG64M72EER-AD7 ADVANCED Document Title 512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM Revision History Rev # History Release Date Status Rev 0 Created September 2005 Advanced Rev 1 1.1 Updated ICC and AC specs December 2005 Advanced December 2005 Rev. 1 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com