White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED* 1GB – 2x64Mx72 DDR2 SDRAM UDIMM, SO-DIMM w/PLL FEATURES DESCRIPTION Unbuffered 200-pin (SO-DIMM) small-outline dual in-line memory module Support ECC detection and correction Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 The WV3HG264M72EEU is a 2x64Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of eighteen 64Mx8 bit DDR2 Synchronous DRAMs in FBGA packages, mounted on a 200-pin SODIMM FR4 substrate. VCC = VCCQ = 1.8V ±0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. Differential clock input (CK,CK#) Four-bit prefetch architecture Multiple internal device banks for concurrent operation Programmable CAS# latency (CL): 3 4, 5*, and 6* Adjustable data-output drive strength 7.8µs average periodic refresh interval On-die termination (ODT) Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM Auto & self refresh (64ms: 8,192 cycle refresh) Gold edge contacts Dual Rank RoHS compliant JEDEC proposed pin-out Package option NOTE: Consult factory for availability of: • Vendor source control options • Industrial temperature option • 200 Pin SO-DIMM: 30.00mm (1.181") TYP OPERATING FREQUENCIES PC2-3200 PC2-4200 PC2-5300* PC2-6400* Clock Speed 200MHz 266MHz 333MHz 400MHz CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 6-6-6 * Consult factory for availability April 2006 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 April 2006 Rev. 2 Symbol VREF VSS DQ0 DQ4 VSS DQ5 DQ1 VSS DQS0# DM0 DQS0 VSS VSS DQ6 DQ2 DQ7 DQ3 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DM1 DQS1# VSS DQS1 DQ14 VSS DQ15 DQ10 VSS DQ11 DQ20 VSS DQ21 DQ16 VSS DQ17 RESET# VSS DM2 DQS2# VSS DQS2 DQ22 VSS DQ23 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol DQ18 VSS DQ19 DQ28 VSS DQ29 DQ24 VSS DQ25 DM3 VSS VSS DQS3# DQ30 DQS3 DQ31 VSS VSS DQ26 CB4 DQ27 CB5 VSS VSS CB0 DM8 CB1 VSS VSS CB6 DQS8# CB7 DQS8 VSS VSS CB2 CKE0 CB3 NC VSS NC NC VCC NC A12 A11 A9 VCC A7 A8 Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol VCC A6 A5 A4 A3 VCC A2 A1 VCC A0 A10/AP BA1 BA0 VCC RAS# WE# VCC CS0# CAS# ODT0 CS1# A13 VCC VCC ODT1 CK NC CK# DQ32 VSS VSS DQ36 DQ33 DQ37 DQS4# VSS DQS4 DM4 VSS VSS DQ34 DQ38 DQ35 DQ39 VSS VSS DQ40 DQ44 DQ41 DQ45 PIN NAMES Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol VSS VSS DQS5# DM5 DQS5 VSS VSS DQ46 DQ42 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 DQS6# VSS DQS6 DQ54 VSS DQ55 DQ50 VSS DQ51 DQ60 VSS DQ61 DQ56 VSS DQ57 DM7 VSS DQ62 DQS7# VSS DQS7 DQ63 DQ58 SDA VSS SCL DQ59 SA1 VCCSPD SA0 2 Pin Name A0-A13 Function Address Inputs BA0, BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0, ODT1 CK,CK# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# RESET# VCC VSS SA0-SA1 SDA VREF DM0-DM8 VCCSPD SCL NC SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement On-die termination controls Clock inputs Clock enable inputs Chip select inputs Row Address Strobe Column Address Strobe Write Enable Register reset input Core Power Ground SPD address Serial Data Input/Output Input/Output Reference Voltage Data-in mask Serial EEPROM power supply SPD Clock Input No connect White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQS1 DQS1# DM1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS5 DQS5# DM5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQS2 DQS2# DM2 DQS6 DQS6# DM6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQS7 DQS7# DM7 DQS3 DQS3# DM3 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS# DQS DQS# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DQS8 DQS8# DM8 Serial PD CS0# CS# : DDR2 SDRAMs CS1# CS# : DDR2 SDRAMs BA0 - BA1 A0 - A13 SCL SDA WP A0 A1 SA0 SA1 VCCSPD A2 SA2 Serial PD VCC/VCCQ DDR2 SDRAMs VREF DDR2 SDRAMs VSS BA0 - BA1 : DDR2 SDRAMs DDR2 SDRAMs A0 - A13 : DDR2 SDRAMs RAS# RAS# : DDR2 SDRAMs CAS# CAS# : DDR2 SDRAMs WE# WE# : DDR2 SDRAMs CKE0 CKE : DDR2 SDRAMs CKE1 CKE : DDR2 SDRAMs ODT0 ODT : DDR2 SDRAMs ODT1 ODT : DDR2 SDRAMs 120Ω CK0 CK0# PLL RESET# CK CK# DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 NOTE: All resistor values are 22 ohms unless otherwise specified. April 2006 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Symbol Min Typical Max Unit Notes Supply Voltage VCC 1.7 1.8 1.9 V 3 I/O Reference Voltage VREF 0.49 x VCC 0.50 x VCC 0.51 x VCC V 1 VTT VREF-0.04 VREF VREF+0.04 V 2 VCCSPD 1.7 - 3.6 V I/O Termination Voltage SPD Supply Voltage Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units VCC Voltage on VCC pin relative to VSS -0.5 2.3 V VIN, VOUT Voltage on any pin relative to VSS IL IOZ IVREF Input leakage current; Any input 0V<VIN<VCC; VREF input 0V,VIN,0.95V; Other pins not under test = 0V Output leakage current; 0V<VIN<VCC; DQs and ODT are disable -0.5 2.3 V Command/Address, RAS#, CAS#, WE#, -90 90 µA CS#, CKE -45 45 µA CK, CK# -10 10 µA DM -10 10 µA DQ, DQS, DQS# -10 10 µA -36 36 µA VREF leakage current; VREF = Valid VREF level INPUT/OUTPUT CAPACITANCE TA=25°C, f=100MHz Parameter Input capacitance (0A~A13, BA0~BA1, RAS#, CAS#, WE#) Input capacitance (CKE0, CKE1), (ODT0, ODT1) Input capacitance (CS0# - CS1#) Input capacitance (CK, CK#) Input capacitance (DM0~DM8), (DQS0~DQS8) Input capacitance (DQ0~DQ63), (CB0~CB7) April 2006 Rev. 2 Symbol Min Max Unit CIN1 22 40 pF CIN2 13 22 pF CIN3 CIN4 CIN5 (665) CIN5 (534, 403) COUT1 (665) COUT1 (534, 403) 13 6 9 9 9 9 22 7 11 12 11 12 pF pF pF pF pF pF 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED OPERATING TEMPERATURE CONDITION Parameter Symbol Rating Units Notes Operating temperature (Commercial) TOPER 0° to 85° °C 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2 2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Symbol Min Max Units Input High (Logic 1) Voltage VIH(DC) VREF + 0.125 VCC + 0.300 V Input Low (Logic 0) Voltage VIL(DC) -0.300 VREF - 0.125 V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 1) Voltage DDR2-667 AC Input High (Logic 0) Voltage DDR2-400 & DDR2-533 AC Input High (Logic 0) Voltage DDR2-667 April 2006 Rev. 2 Symbol Min Max Unit VIH(AC) VREF + 0.250 - V VIH(AC) VREF + 0.200 - V VIL(AC) - VREF - 0.250 V VIL(AC) - VREF - 0.200 V 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED DDR2 ICC SPECIFICATIONS AND CONDITIONS Includes DDR2 SDRAM components only VCC = +1.8V ± 0.1V Symbol Proposed Conditions ICC0* ICC1* ICC2P* ICC2Q** ICC2N** ICC3P** ICC3N** ICC4W* ICC4R* ICC5B** ICC6** ICC7* 806 665 534 403 Units Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,137 1,092 1,092 mA Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W TBD 1,272 1,227 1,227 mA Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 444 444 444 mA Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING TBD 930 840 840 mA Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,020 930 930 mA Fast PDN Exit MRS(12) = 0 TBD 840 840 840 mA Slow PDN Exit MRS(12) = 1 TBD 516 516 516 mA Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,290 1,200 1,200 mA Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 1,632 1,452 1,362 mA Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W TBD 1,677 1,497 1,362 mA Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING TBD 3,000 2,820 2,820 mA Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING TBD 144 144 144 mA TBD 2,352 2,352 2,352 mA Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Normal Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING. ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Note: * Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode. ** Value calculated reflects all module ranks in this operating condition. April 2006 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED AC TIMING PARAMETERS & SPECIFICATIONS VCC = +1.8V ± 0.1V AC CHARACTERISTICS 806 PARAMETER MIN MAX TBD TBD TBD TBD TBD TBD TBD CK high-level width tCH CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ…DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising … setup time DQS falling edge from CK rising … hold time DQS…DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition tCL tHP tJIT tAC Data Clock Clock cycle time Data Strobe 665 SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) CL = 6 CL = 5 CL = 4 CL = 3 Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input hold time tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH 534 403 MIN MAX MIN MAX MIN MAX TBD 3,000 3,750 5,000 8,000 8,000 8,000 3,750 5,000 8,000 8,000 5,000 5,000 8,000 8,000 UNIT ps ps ps ps TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK TBD TBD 0.55 TBD TBD TBD TBD 0.45 MIN(tCH,tCL) -125 -600 0.55 TBD 0.45 MIN(tCH,tCL) -125 -500 0.55 TBD 0.45 MIN(tCH,tCL) -125 -450 125 +600 tCK ps ps ps TBD TBD tAC(MAX) ps TBD TBD tAC(MAX) ps TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 125 +450 tAC(MAX) tAC(MIN) tAC(MAX) 125 +500 tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) 100 100 150 225 225 275 0.35 0.35 0.35 340 400 tCK 450 ps tHP - tQHS tHP - tQHS tHP - tQHS ps tQH - tDQSQ 0.35 0.35 -400 0.2 tQH - tDQSQ 0.35 0.35 -450 0.2 tQH - tDQSQ 0.35 0.35 -500 0.2 ns tCK tCK ps tCK +400 0.2 tDQSQ +450 0.2 240 +500 0.2 300 tCK 350 ps 1.1 0.6 tCK tCK ps tCK tCK tRPRE tRPST TBD TBD TBD TBD tWPRES tWPRE tWPST TBD TBD TBD TBD TBD TBD TBD TBD tIPW TBD TBD 0.6 0.6 0.6 tCK tIS tIH TBD TBD TBD TBD tCCD TBD TBD 200 275 2 250 375 2 250 475 2 ps ps tCK tDQSS 0.9 0.4 0 0.35 0.4 WL0.25 1.1 0.6 0.6 WL+ 0.25 0.9 0.4 0 0.35 0.4 WL0.25 1.1 0.6 0.6 WL+ 0.25 0.9 0.4 0 0.35 0.4 WL0.25 0.6 WL+ 0.25 tCK * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page April 2006 Rev. 2 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED AC TIMING PARAMETERS & SPECIFICATIONS (cont'd) VCC = +1.8V ± 0.1V AC CHARACTERISTICS Self Refresh Command and Address PARAMETER SYMBOL MIN MAX tRC TBD TBD ACTIVE bank a to ACTIVE bank b command tRRD TBD TBD ACTIVE to READ or WRITE delay tRCD TBD TBD Four Bank Activate period tFAW TBD TBD ACTIVE to PRECHARGE command tRAS TBD TBD Internal READ to precharge command delay tRTP TBD TBD Write recovery time tWR TBD TBD Auto precharge write recovery + precharge time tDAL TBD TBD Internal WRITE to READ command delay tWTR TBD TBD PRECHARGE command period tRP TBD TBD PRECHARGE ALL command period tRPA TBD TBD LOAD MODE command cycle time tMRD TBD TBD CKE low to CK,CK# uncertainty tDELAY TBD TBD TBD TBD REFRESH to Active of Refresh to Refresh command interfal tRFC Average periodic refresh interval tREFI TBD TBD Exit self refresh to non-READ command tXSNR TBD TBD Exit self refresh to READ command tXSRD TBD TBD Exit self refresh timing reference tISXR TBD TBD ODT turn-on delay tAOND TBD TBD TBD TBD ODT turn-on tAON ODT turn-off delay tAOFD ODT turn-off (power-down mode) tAOFPD 70,000 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 TBD tAC (MIN) TBD 37.5 70,000 MIN 55 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH 105 7.8 TBD TBD tAONPD 534 MAX 105 TBD tAOF ODT turn-on (power-down mode) MIN 55 7.5 15 37.5 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH TBD TBD Power-Down 665 ACTIVE to ACTIVE (same bank) command ODT turn-off ODT 806 tAC (MIN) + 2000 TBD tAC (MIN) + 2000 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 403 MAX 37.5 70,000 70,000 MIN 55 7.5 15 37.5 45 7.5 15 tWR + tRP 10 15 tRP+tCK 2 tIS + tCK + tIH 105 7.8 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 MAX UNIT ns ns ns 37.5 70,000 ns ns ns ns ns ns ns ns tCK ns 70,000 ns 7.8 µs ns tCK ps 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tCK ps tCK ps ps ps 3 8 3 8 3 8 tCK TBD 2 2 2 tCK TBD TBD 7 - AL 6 - AL 6 - AL tCK tXP TBD TBD 2 2 2 tCK tCKE TBD TBD 3 3 3 tCK ODT to power-down entry latency tANPD TBD TBD ODT power-down exit latency tAXPD TBD TBD Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any nonREAD command. CKE minimum high/low time tXARD TBD tXARDS tCK * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. April 2006 Rev. 2 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED ORDERING INFORMATION FOR PD4 Part Number Speed/Data Rate CAS Latency tRCD tRP Height* WV3HG264M72EEU806PD4xxG** 400MHz/800Mb/s 6 6 6 30.00mm (1.81")TYP WV3HG264M72EEU665PD4xxG** 333MHz/667Mb/s 5 5 5 30.00mm (1.81")TYP WV3HG264M72EEU534PD4xxG 266MHz/533Mb/s 4 4 4 30.00mm (1.81")TYP WV3HG264M72EEU403PD4xxG 200MHz/400Mb/s 3 3 3 30.00mm (1.81")TYP ** Consult factory for availability NOTES: • RoHS product. (“G” = RoHS Compliant) • Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) PACKAGE DIMENSIONS FOR PD4 FRONT VIEW 3.80 (0.150) MAX 67.75 (2.667) 67.45 (2.656) 4.10(0.161) (2X) 3.90(0.154) 30.15 (1.187) 29.85 (1.175) 1.800 (0.071) (2X) 20.00 (0.787) TYP 6.00 (0.236) 2.55 (0.100) 2.15 (0.085) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP PIN 1 0.45 (0.018) TYP 0.60 (0.024) TYP PIN 199 2.504 (63.60) TYP BACK VIEW 4.2 (0.165) TYP PIN 200 47.40 (1.866) TYP PIN 2 11.40 (0.449) TYP * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) Tolerances: ±0.13 (0.005) unless otherwise specified April 2006 Rev. 2 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED PART NUMBERING GUIDE WV 3 H G 2 64M 72 E E U xxx PD4 x x G WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x8 1.8V UNBUFFERED (UDIMM) SPEED (Mb/s) PACKAGE 200 PIN SO-DIMM (P = JEDEC proposed pin-out) INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT April 2006 Rev. 2 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3HG264M72EEU-PD4 ADVANCED Document Title 1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED, SO-DIMM w/PLL DRAM DIE OPTIONS: • SAMSUNG: C-Die, will move to E-Die Q2'06 • MICRON: U37Y: B-Die Revision History Rev # History Release Date Status Rev 0 Created August 2005 Concept Rev 1 1.0 Updated ICC, CAP & AC specs March 2006 Advanced April 2006 Advanced 1.1 Added industrial temp option to part numbering guide 1.2 Changed from concept to advanced Rev 2 2.0 Update ICC, CAP & AC specs 2.1 Added "P" for JEDEC proposed pin-out 2.2 Added die Rev info April 2006 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com