CY28354-400 210-MHz 24-Output Buffer for 4-DDR DIMMS for VIA Chipsets Support Features Functional Description • Supports VIA PRO 266, KT266 and P4x266 The CY28354-400 is a 2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 24 outputs to support four unbuffered DDR DIMMS. The CY28354-400 can be used in conjunction with CY28326 similar clock synthesizer for the PTT880 and KTT880 chipsets. • Dual 1- to 12-output buffer/driver • Supports up to four DDR DIMMs • Low-skew outputs (< 75 ps) • Supports 266-MHz, 333-MHz and 400-MHz DDR SDRAM • SMBus Read and Write support • Space-saving 48-pin SSOP package The CY28354-400 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled. Pin Configuration Block Diagram BUF_INA FB_OUTA DDRAT0 DDRAC0 DDRAT1 DDRAC1 DDRAT2 DDRAC2 DDRAT3 DDRAC3 DDRAT4 DDRAC4 DDRAT5 DDRAC5 DDRBT0 DDRBC0 DDRBT1 DDRBC1 DDRBT2 DDRBC2 DDRBT3 DDRBC3 DDRBT4 DDRBC4 DDRBT5 DDRBC5 FB_OUTB ADDR_SEL SDATA SMBus Decoding SCLOCK I2C_CS BUFF_INB Cypress Semiconductor Corporation Document #: 38-07615 Rev. *B • 3901 North First Street SSOP Top View VDD2.5 GND FB_OUTB BUFF_INB DDRBT0 DDRBC0 DDRBT1 DDRBC1 GND VDD2.5 DDRAT0 DDRAC0 DDRAT1 DDRAC1 GND VDD2.5 FB_OUTA BUF_INA DDRAT2 DDRAC2 DDRAT3 DDRAC3 VDD2.5 GND • 1 2 48 47 3 46 4 45 5 44 6 43 7 42 8 9 41 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 21 22 29 28 27 23 26 24 25 San Jose, CA 95134 VDD2.5 GND ADDR_SEL I2C_CS DDRBT2 DDRBC2 DDRBT3 DDRBC3 GND VDD2.5 DDRAT4 DDRAC4 DDRAT5 DDRAC5 GND VDD2.5 DDRBT4 DDRBC4 DDRBT5 DDRBC5 VDD2.5 GND SDATA SCLK • 408-943-2600 Revised June 22, 2004 CY28354-400 Pin Description Pin Name PWR I/O Description 11, 13, 19, 21, 38, 36, 5, 7, 44, 42, 32, 30 DDRA[0:5]T DDRB[0:5]T VDD2.5 O Clock outputs. These outputs provide copies of BUF_INA and BUF_INB, respectively. 12, 14, 20, 22, 37, 35, 6, 8, 43, 41, 31, 29 DDRA[0:5]C VDD2.5 DDRB[0:5]C O Clock outputs. These outputs provide complementary copies of BUF_INA and BUF_INB, respectively. 18, 4 BUF_INA, BUF_INB VDD2.5 I PD 17, 3 FB_OUTA FB_OUTB VDD2.5 O 45 I2C_CS VDD2.5 I PD CS for I2C allows for multiple devices to be connected with the same I2C address. Internal pull-down. See Table 1. 46 ADDR_SEL VDD2.5 I PD Selects I2C Address D2/DC. Internal Pull-down 25 SCLK VDD2.5 I PU SMBus clock input. Internal Pull-up 26 SDATA VDD2.5 I/O PU SMBus data input. Internal Pull-up Reference input from chipset. 2.5V input. Internal pull-down Feedback clock for chipset. 1, 10, 16, 23, 28, 33, 39, 48 VDD2.5 2.5V voltage supply 2, 9, 15, 24, 27, 34, 40, 47 Ground GND Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operation from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The Block Write and Block Read protocol is outlined in Table 2.The slave receiver address is D2/DC depending on the state of the ADDRSEL pin. Table 1. Command Code Definition Bit 7 Description 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation (6:5) 01 to address chip when I2C_CS = 0 10 to address chip when I2C_CS = 1 (4:0) Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '00000' Document #: 38-07615 Rev. *B Page 2 of 9 CY28354-400 Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bits '00000000' stands for block operation 11:18 Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count from master – 8 bits 20 Repeat start Acknowledge from slave Data byte 0 from master – 8 bits Acknowledge from slave Data byte 1 from master – 8 bits 46 Acknowledge from slave .... Data bytes from master/Acknowledge .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop Serial Configuration Map • The Serial bits will be read by the clock driver in the following order. Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0 Document #: 38-07615 Rev. *B 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 38 39:46 47 48:55 Byte count from slave – 8 bits Acknowledge Data byte 0 from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop • Reserved and unused bits should be programmed to “0” • SMBus Address for the CY28354 is as follows. A6 A5 A4 A3 A2 A1 A0 R/W SEL ADDR = 1 1 1 0 1 0 0 1 — SEL ADDR = 0 1 1 0 1 1 1 0 — Page 3 of 9 CY28354-400 Byte 22: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default (Hi-z) = Active Bit @Pup Pin # Description Bit 7 0 Input Threshold Control 00: Normal (1.25V) 01: 1.20V 10: 1.15V 11: 1.10V Bit 6 0 Bit 5 0 17 FBOUTA Control, 0 = Enable, 1 = Disable Bit 4 0 3 FBOUTB Control, 0 = Enable, 1 = Disable Bit 3 1 30, 29 DDRBT5, DDRBC5 Bit 2 1 32, 31 DDRBT4, DDRBC4 Bit 1 1 42, 41 DDRBT3, DDRBC3 Bit 0 1 44, 43 DDRBT2, DDRBC2 Byte 23: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit @Pup Pin # Description Bit 7 1 7, 8 DDRBT1, DDRBC1 Bit 6 1 5, 6 DDRBT0, DDRBC0 Bit 5 1 36, 35 DDRAT5, DDRAC5 Bit 4 1 38, 37 DDRAT4, DDRAC4 Bit 3 1 21, 22 DDRAT3, DDRAC3 Bit 2 1 19, 20 DDRAT2, DDRAC2 Bit 1 1 13, 14 DDRAT1, DDRAC1 Bit 0 1 11, 12 DDRAT0, DDRAC0 Document #: 38-07615 Rev. *B Page 4 of 9 CY28354-400 Absolute Maximum Conditions[1] Parameter Description Min. Max. Unit VDD Supply Voltage to Ground Potential –0.5 4.6 V Vin DC Input Voltage (except BUFF_IN) –0.3 VDD+0.3 V Vout Output Voltage 1.1 VDD–0.4 V Ts Temperature, Storage –65 +150 °C Ta Temperature, Operating Ambient ØJC Dissipation, Junction to Case (Mil-Spec 883E Method 1012.1) ØJA Dissipation, Junction to Ambient (JEDEC (JESD 51) ESDh ESD Protection (Human Body Model) 0 85 °C 36.39 °C/W 77.99 °C/W – 2000 V DC Electrical Specifications Parameter Description Min. Typ. Max. Unit 2.3 – 2.7 V VDD2.5 Supply Voltage COUT Output Capacitance – 6 – pF CIN Input Capacitance – 5 – pF Max. Unit AC Electrical Specifications Parameter Description VIL Input LOW Voltage VIH Input HIGH Voltage IOH Output HIGH Current IOL Output LOW Current Voltage[2] VOL Output LOW VOH Output HIGH Voltage[2] IDD Conditions For all pins except SMBus Min. Typ. 0.3 – 0.7 V 1.7 – VDD + 0.3 V VDD = 2.375V, VOUT = 1V – – –12 mA VDD = 2.375V, VOUT = 1.2V – – 12 mA IOL = 12 mA, VDD = 2.375V – – 0.5 V IOH = –12 mA, VDD = 2.375V 1.7 – – V Supply Current[2] Unloaded outputs, 133 MHz – – 400 mA IDD Supply Current Loaded outputs, 133 MHz – – 500 mA IDDPD Supply Current All outputs off VOUT Output Voltage Swing See Test Circuity. See Figure 1 VOC Output Crossing Voltage INDC Input Clock Duty Cycle – – 2 mA 0.7 – VDD + 0.6 V VDD/2–0.3 VDD/2 VDD/2+0.3 V 40 – 60 % Switching Characteristics[3] Parameter Name Test Conditions Min. Typ. 60 Max. Unit 210 MHz – Operating Frequency – Duty Cycle[2, 4] = t2 ÷ t1 Measured differentially at VCROSS INDC –2% – INDC +2% % t3d DDR Rising Edge Rate[2] Measured single ended at 20% to 80% of VDIF 1.0 2.0 5.0 V/ns t4d DDR Falling Edge Rate[2] Measured single ended at 80% to 20% of VDIF 1.0 2.0 5.0 V/ns t5 Output to Output Skew for All outputs equally loaded. DDR[2] See Figure 1. – – 75 ps t6 Input to Output Propagation At output load of 15 pFn delay – – 6 ns Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3. All parameters specified with loaded outputs. 4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns. Document #: 38-07615 Rev. *B Page 5 of 9 CY28354-400 Switching Waveforms V OH V V D IF V CROSS OL V SS Duty Cycle Timing t1 t2 Output-Output Skew OUTPUT OUTPUT t5 Figure 1 shows the differential clock directly terminated by a 120Ω resistor. VCC Device Under Test Out Out VCC ) ) 60Ω VTR RT =120Ω 60Ω Receiver VCP Figure 1. Differential Signal Using Direct Termination Resistor Document #: 38-07615 Rev. *B Page 6 of 9 CY28354-400 Layout Example for DDR 2.5V FB VDDQ2 10 mF 0.005 mF C4 G G G G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 G V G G V 48 47 46 45 44 43 42 41 G 40 V 39 G 38 37 36 35 G 34 V 33 G 32 31 30 29 V 28 G 27 26 G 25 V V G G G CY28354-400 G C3 G G G V G G G G FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120 Ceramic Caps C3 = 10–22 µF C4 = 0.005 µF G = VIA to GND plane layer V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 µF ceramic Ordering Information Ordering Code Package Type Operating Range CY28354OXC–400 48-pin SSOP - Lead Free Commercial, 0°C to 85 °C CY28354OXC–400T 48-pin SSOP – Tape and Reel - Lead Free Commercial, 0°C to 85 °C Document #: 38-07615 Rev. *B Page 7 of 9 CY28354-400 Package Drawing and Dimension 48-Lead Shrunk Small Outline Package O48 51-85061-*C All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07615 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. CY28354-400 Document History Page Document Title:CY28354-400 210-MHz 24-Output Buffer for 4-DDR DIMMS for VIA Chipsets Support Document Number: 38-07615 Rev. ECN No. Issue Date Orig. of Change ** 131434 12/09/03 RGL *A 222683 See ECN RGL/TUJ *B 237829 See ECN RGL Document #: 38-07615 Rev. *B Description of Change New Data Sheet Removed the “Outputs are individually enabled/disabled” sentence in the features Fixed the Functional description in the first page Dropped the Operating Frequency from 273 to 210MHz Changed the output crossing voltage to (VDD/2)±0.3 Changed the max. rising/falling edge rate from 3.0 to 5.0 V/ns Removed the IIL and IIH spec. Page 9 of 9